drivers/video/controlfb.h

   1 /*
   2  * controlfb_hw.h: Constants of all sorts for controlfb
   3  *
   4  * Copyright (C) 1998 Daniel Jacobowitz <dan@debian.org>
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * as published by the Free Software Foundation; either version
   9  * 2 of the License, or (at your option) any later version.
  10  *
  11  * Based on an awful lot of code, including:
  12  *
  13  * control.c: Console support for PowerMac "control" display adaptor.
  14  * Copyright (C) 1996 Paul Mackerras.
  15  *
  16  * The so far unpublished platinumfb.c
  17  * Copyright (C) 1998 Jon Howell
  18  */
  19
  20 /*
  21  * Structure of the registers for the RADACAL colormap device.
  22  */
  23 struct cmap_regs {
  24         unsigned char addr;
  25         char pad1[15];
  26         unsigned char d1;
  27         char pad2[15];
  28         unsigned char d2;
  29         char pad3[15];
  30         unsigned char lut;
  31         char pad4[15];
  32 };
  33
  34 /*
  35  * Structure of the registers for the "control" display adaptor.
  36  */
  37 #define PAD(x)  char x[12]
  38
  39 struct preg {                   /* padded register */
  40         unsigned r;
  41         char pad[12];
  42 };
  43
  44 struct control_regs {
  45         struct preg vcount;     /* vertical counter */
  46         /* Vertical parameters are in units of 1/2 scan line */
  47         struct preg vswin;      /* between vsblank and vssync */
  48         struct preg vsblank;    /* vert start blank */
  49         struct preg veblank;    /* vert end blank (display start) */
  50         struct preg vewin;      /* between vesync and veblank */
  51         struct preg vesync;     /* vert end sync */
  52         struct preg vssync;     /* vert start sync */
  53         struct preg vperiod;    /* vert period */
  54         struct preg reg8;
  55         /* Horizontal params are in units of 2 pixels */
  56         struct preg hperiod;    /* horiz period - 2 */
  57         struct preg hsblank;    /* horiz start blank */
  58         struct preg heblank;    /* horiz end blank */
  59         struct preg hesync;     /* horiz end sync */
  60         struct preg hssync;     /* horiz start sync */
  61         struct preg rege;
  62         struct preg regf;
  63         struct preg reg10;
  64         struct preg reg11;
  65         struct preg ctrl;       /* display control */
  66         struct preg start_addr; /* start address: 5 lsbs zero */
  67         struct preg pitch;      /* addrs diff between scan lines */
  68         struct preg mon_sense;  /* monitor sense bits */
  69         struct preg flags;
  70         struct preg mode;
  71         struct preg reg18;
  72         struct preg reg19;
  73         struct preg res[6];
  74 };
  75
  76 struct control_regints {
  77         /* Vertical parameters are in units of 1/2 scan line */
  78         unsigned vswin; /* between vsblank and vssync */
  79         unsigned vsblank;       /* vert start blank */
  80         unsigned veblank;       /* vert end blank (display start) */
  81         unsigned vewin; /* between vesync and veblank */
  82         unsigned vesync;        /* vert end sync */
  83         unsigned vssync;        /* vert start sync */
  84         unsigned vperiod;       /* vert period */
  85         unsigned reg8;
  86         /* Horizontal params are in units of 2 pixels */
  87         /* Except, apparently, for hres > 1024 (or == 1280?) */
  88         unsigned hperiod;       /* horiz period - 2 */
  89         unsigned hsblank;       /* horiz start blank */
  90         unsigned heblank;       /* horiz end blank */
  91         unsigned hesync;        /* horiz end sync */
  92         unsigned hssync;        /* horiz start sync */
  93         unsigned rege;
  94         unsigned regf;
  95         unsigned reg10;
  96 };
  97
  98 /*
  99  * Register initialization tables for the control display.
 100  *
 101  * Dot clock rate is
 102  * 3.9064MHz * 2**clock_params[2] * clock_params[1] / clock_params[0].
 103  *
 104  * The values for vertical frequency (V) in the comments below
 105  * are the values measured using the modes under MacOS.
 106  *
 107  * Pitch is always the same as bytes per line (for these video modes at least).
 108  */
 109 struct control_regvals {
 110         int     offset[3];              /* first pixel address */
 111         unsigned regs[16];              /* for vswin .. reg10 */
 112         unsigned char mode[3];          /* indexed by color_mode */
 113         unsigned char radacal_ctrl[3];
 114         unsigned char clock_params[3];
 115         int     hres;
 116         int     vres;
 117 };
 118
 119 /* Register values for 1280x1024, 75Hz mode (20) */
 120 static struct control_regvals control_reg_init_20 = {
 121         { 0x10, 0x20, 0 },
 122         { 2129, 2128, 80, 42, 4, 2130, 2132, 88,
 123           420, 411, 91, 35, 421, 18, 211, 386, },
 124         { 1, 1, 1},
 125         { 0x50, 0x64, 0x64 },
 126         { 13, 56, 3 },  /* pixel clock = 134.61MHz for V=74.81Hz */
 127         1280, 1024
 128 };
 129
 130 /* Register values for 1280x960, 75Hz mode (19) */
 131 static struct control_regvals control_reg_init_19 = {
 132         { 0x10, 0x20, 0 },
 133         { 1997, 1996, 76, 40, 4, 1998, 2000, 86,
 134           418, 409, 89, 35, 419, 18, 210, 384, },
 135         { 1, 1, 1 },
 136         { 0x50, 0x64, 0x64 },
 137         { 31, 125, 3 }, /* pixel clock = 126.01MHz for V=75.01 Hz */
 138         1280, 960
 139 };
 140
 141 /* Register values for 1152x870, 75Hz mode (18) */
 142 static struct control_regvals control_reg_init_18 = {
 143         { 0x10, 0x28, 0x50 },
 144         { 1825, 1822, 82, 43, 4, 1828, 1830, 120,
 145           726, 705, 129, 63, 727, 32, 364, 664 },
 146         { 2, 1, 1 },
 147         { 0x10, 0x14, 0x28 },
 148         { 19, 61, 3 },  /* pixel clock = 100.33MHz for V=75.31Hz */
 149         1152, 870
 150 };
 151
 152 /* Register values for 1024x768, 75Hz mode (17) */
 153 static struct control_regvals control_reg_init_17 = {
 154         { 0x10, 0x28, 0x50 },
 155         { 1603, 1600, 64, 34, 4, 1606, 1608, 120,
 156           662, 641, 129, 47, 663, 24, 332, 616 },
 157         { 2, 1, 1 },
 158         { 0x10, 0x14, 0x28 },
 159         { 11, 28, 3 },  /* pixel clock = 79.55MHz for V=74.50Hz */
 160         1024, 768
 161 };
 162
 163 /* Register values for 1024x768, 72Hz mode 16 (15?) */
 164 static struct control_regvals control_reg_init_15 = {
 165         { 0x10, 0x28, 0x50 },
 166         { 1607, 1604, 68, 39, 10, 1610, 1612, 132,
 167           670, 653, 141, 67, 671, 34, 336, 604, },
 168         { 2, 1, 1 },
 169         { 0x10, 0x14, 0x28 },
 170         { 12, 30, 3 },  /* pixel clock = 78.12MHz for V=72.12Hz */
 171         1024, 768
 172 };
 173
 174 /* Register values for 1024x768, 60Hz mode (14) */
 175 static struct control_regvals control_reg_init_14 = {
 176         { 0x10, 0x28, 0x50 },
 177         { 1607, 1604, 68, 39, 10, 1610, 1612, 132,
 178           670, 653, 141, 67, 671, 34, 336, 604, },
 179         { 2, 1, 1 },
 180         { 0x10, 0x14, 0x28 },
 181         { 15, 31, 3 },  /* pixel clock = 64.58MHz for V=59.62Hz */
 182         1024, 768
 183 };
 184
 185 /* Register values for 832x624, 75Hz mode (13) */
 186 static struct control_regvals control_reg_init_13 = {
 187         { 0x10, 0x28, 0x50 },
 188         { 1331, 1330, 82, 43, 4, 1332, 1334, 128,
 189           574, 553, 137, 31, 575, 16, 288, 544 },
 190         { 2, 1, 0 }, { 0x10, 0x14, 0x18 },
 191         { 23, 42, 3 },  /* pixel clock = 57.07MHz for V=74.27Hz */
 192         832, 624
 193 };
 194
 195 /* Register values for 800x600, 75Hz mode (12) */
 196 static struct control_regvals control_reg_init_12 = {
 197         { 0x10, 0x28, 0x50 },
 198         { 1247, 1246, 46, 25, 4, 1248, 1250, 104,
 199           526, 513, 113, 39, 527, 20, 264, 488, },
 200         { 2, 1, 0 }, { 0x10, 0x14, 0x18 },
 201         { 7, 11, 3 },   /* pixel clock = 49.11MHz for V=74.40Hz */
 202         800, 600
 203 };
 204
 205 /* Register values for 800x600, 72Hz mode (11) */
 206 static struct control_regvals control_reg_init_11 = {
 207         { 0x10, 0x28, 0x50 },
 208         { 1293, 1256, 56, 33, 10, 1330, 1332, 76,
 209           518, 485, 85, 59, 519, 30, 260, 460, },
 210         { 2, 1, 0 }, { 0x10, 0x14, 0x18 },
 211         { 17, 27, 3 },  /* pixel clock = 49.63MHz for V=71.66Hz */
 212         800, 600
 213 };
 214
 215 /* Register values for 800x600, 60Hz mode (10) */
 216 static struct control_regvals control_reg_init_10 = {
 217         { 0x10, 0x28, 0x50 },
 218         { 1293, 1256, 56, 33, 10, 1330, 1332, 76,
 219           518, 485, 85, 59, 519, 30, 260, 460, },
 220         { 2, 1, 0 }, { 0x10, 0x14, 0x18 },
 221         { 20, 53, 2 },  /* pixel clock = 41.41MHz for V=59.78Hz */
 222         800, 600
 223 };
 224
 225 /* Register values for 640x870, 75Hz Full Page Display (7) */
 226 static struct control_regvals control_reg_init_7 = {
 227         { 0x10, 0x30, 0x68 },
 228         { 0x727, 0x724, 0x58, 0x2e, 0x4, 0x72a, 0x72c, 0x40,
 229           0x19e, 0x18c, 0x4c, 0x27, 0x19f, 0x14, 0xd0, 0x178 },
 230         { 2, 1, 0 }, { 0x10, 0x14, 0x18 },
 231         { 9, 33, 2 },   /* pixel clock = 57.29MHz for V=75.01Hz */
 232         640, 870
 233 };
 234
 235 /* Register values for 640x480, 67Hz mode (6) */
 236 static struct control_regvals control_reg_init_6 = {
 237         { 0, 8, 0x10 },
 238         { 1045, 1042, 82, 43, 4, 1048, 1050, 72,
 239           430, 393, 73, 31, 431, 16, 216, 400 },
 240         { 2, 1, 0 }, { 0x10, 0x14, 0x18 },
 241         { 14, 27, 2 },  /* pixel clock = 30.13MHz for V=66.43Hz */
 242         640, 480
 243 };
 244
 245 /* Register values for 640x480, 60Hz mode (5) */
 246 static struct control_regvals control_reg_init_5 = {
 247         { 0x10, 0x28, 0x50 },
 248         { 1037, 1026, 66, 34, 2, 1048, 1050, 56,
 249           398, 385, 65, 47, 399, 24, 200, 352, },
 250         { 2, 1, 0 }, { 0x10, 0x14, 0x18 },
 251         { 23, 37, 2 },  /* pixel clock = 25.14MHz for V=59.85Hz */
 252         640, 480
 253 };
 254
 255 static struct control_regvals *control_reg_init[VMODE_MAX] = {
 256         NULL, NULL, NULL, NULL,
 257         &control_reg_init_5,
 258         &control_reg_init_6,
 259         &control_reg_init_7,
 260         NULL, NULL,
 261         &control_reg_init_10,
 262         &control_reg_init_11,
 263         &control_reg_init_12,
 264         &control_reg_init_13,
 265         &control_reg_init_14,
 266         &control_reg_init_15,
 267         &control_reg_init_15,
 268         &control_reg_init_17,
 269         &control_reg_init_18,
 270         &control_reg_init_19,
 271         &control_reg_init_20
 272 };