include/asm-alpha/core_tsunami.h

   1 #ifndef __ALPHA_TSUNAMI__H__
   2 #define __ALPHA_TSUNAMI__H__
   3
   4 #include <linux/config.h>
   5 #include <linux/types.h>
   6 #include <asm/compiler.h>
   7
   8 /*
   9  * TSUNAMI/TYPHOON are the internal names for the core logic chipset which
  10  * provides memory controller and PCI access for the 21264 based systems.
  11  *
  12  * This file is based on:
  13  *
  14  * Tsunami System Programmers Manual
  15  * Preliminary, Chapters 2-5
  16  *
  17  */
  18
  19 #define TSUNAMI_DMA_WIN_BASE_DEFAULT    (1024*1024*1024U)
  20 #define TSUNAMI_DMA_WIN_SIZE_DEFAULT    (1024*1024*1024U)
  21
  22 #if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_SRM_SETUP)
  23 #define TSUNAMI_DMA_WIN_BASE            alpha_mv.dma_win_base
  24 #define TSUNAMI_DMA_WIN_SIZE            alpha_mv.dma_win_size
  25 #else
  26 #define TSUNAMI_DMA_WIN_BASE            TSUNAMI_DMA_WIN_BASE_DEFAULT
  27 #define TSUNAMI_DMA_WIN_SIZE            TSUNAMI_DMA_WIN_SIZE_DEFAULT
  28 #endif
  29
  30 /* XXX: Do we need to conditionalize on this?  */
  31 #ifdef USE_48_BIT_KSEG
  32 #define TS_BIAS 0x80000000000UL
  33 #else
  34 #define TS_BIAS 0x10000000000UL
  35 #endif
  36
  37 /*
  38  * CChip, DChip, and PChip registers
  39  */
  40
  41 typedef struct {
  42         volatile unsigned long csr __attribute__((aligned(64)));
  43 } tsunami_64;
  44
  45 typedef struct {
  46         tsunami_64      csc;
  47         tsunami_64      mtr;
  48         tsunami_64      misc;
  49         tsunami_64      mpd;
  50         tsunami_64      aar0;
  51         tsunami_64      aar1;
  52         tsunami_64      aar2;
  53         tsunami_64      aar3;
  54         tsunami_64      dim0;
  55         tsunami_64      dim1;
  56         tsunami_64      dir0;
  57         tsunami_64      dir1;
  58         tsunami_64      drir;
  59         tsunami_64      prben;
  60         tsunami_64      iic;    /* a.k.a. iic0 */
  61         tsunami_64      wdr;    /* a.k.a. iic1 */
  62         tsunami_64      mpr0;
  63         tsunami_64      mpr1;
  64         tsunami_64      mpr2;
  65         tsunami_64      mpr3;
  66         tsunami_64      mctl;
  67         tsunami_64      ttr;
  68         tsunami_64      tdr;
  69         tsunami_64      dim2;
  70         tsunami_64      dim3;
  71         tsunami_64      dir2;
  72         tsunami_64      dir3;
  73         tsunami_64      iic2;
  74         tsunami_64      iic3;
  75 } tsunami_cchip;
  76
  77 typedef struct {
  78         tsunami_64      dsc;
  79         tsunami_64      str;
  80         tsunami_64      drev;
  81 } tsunami_dchip;
  82
  83 typedef struct {
  84         tsunami_64      wsba[4];
  85         tsunami_64      wsm[4];
  86         tsunami_64      tba[4];
  87         tsunami_64      pctl;
  88         tsunami_64      plat;
  89         tsunami_64      reserved;
  90         tsunami_64      perror;
  91         tsunami_64      perrmask;
  92         tsunami_64      perrset;
  93         tsunami_64      tlbiv;
  94         tsunami_64      tlbia;
  95         tsunami_64      pmonctl;
  96         tsunami_64      pmoncnt;
  97 } tsunami_pchip;
  98
  99 #define TSUNAMI_cchip  ((tsunami_cchip *)(IDENT_ADDR+TS_BIAS+0x1A0000000UL))
 100 #define TSUNAMI_dchip  ((tsunami_dchip *)(IDENT_ADDR+TS_BIAS+0x1B0000800UL))
 101 #define TSUNAMI_pchip0 ((tsunami_pchip *)(IDENT_ADDR+TS_BIAS+0x180000000UL))
 102 #define TSUNAMI_pchip1 ((tsunami_pchip *)(IDENT_ADDR+TS_BIAS+0x380000000UL))
 103 extern int TSUNAMI_bootcpu;
 104
 105 /*
 106  * TSUNAMI Pchip Error register.
 107  */
 108
 109 #define perror_m_lost 0x1
 110 #define perror_m_serr 0x2
 111 #define perror_m_perr 0x4
 112 #define perror_m_dcrto 0x8
 113 #define perror_m_sge 0x10
 114 #define perror_m_ape 0x20
 115 #define perror_m_ta 0x40
 116 #define perror_m_rdpe 0x80
 117 #define perror_m_nds 0x100
 118 #define perror_m_rto 0x200
 119 #define perror_m_uecc 0x400
 120 #define perror_m_cre 0x800
 121 #define perror_m_addrl 0xFFFFFFFF0000UL
 122 #define perror_m_addrh 0x7000000000000UL
 123 #define perror_m_cmd 0xF0000000000000UL
 124 #define perror_m_syn 0xFF00000000000000UL
 125 union TPchipPERROR {
 126         struct  {
 127                 unsigned int perror_v_lost : 1;
 128                 unsigned perror_v_serr : 1;
 129                 unsigned perror_v_perr : 1;
 130                 unsigned perror_v_dcrto : 1;
 131                 unsigned perror_v_sge : 1;
 132                 unsigned perror_v_ape : 1;
 133                 unsigned perror_v_ta : 1;
 134                 unsigned perror_v_rdpe : 1;
 135                 unsigned perror_v_nds : 1;
 136                 unsigned perror_v_rto : 1;
 137                 unsigned perror_v_uecc : 1;
 138                 unsigned perror_v_cre : 1;
 139                 unsigned perror_v_rsvd1 : 4;
 140                 unsigned perror_v_addrl : 32;
 141                 unsigned perror_v_addrh : 3;
 142                 unsigned perror_v_rsvd2 : 1;
 143                 unsigned perror_v_cmd : 4;
 144                 unsigned perror_v_syn : 8;
 145         } perror_r_bits;
 146         int perror_q_whole [2];
 147 };
 148
 149 /*
 150  * TSUNAMI Pchip Window Space Base Address register.
 151  */
 152 #define wsba_m_ena 0x1
 153 #define wsba_m_sg 0x2
 154 #define wsba_m_ptp 0x4
 155 #define wsba_m_addr 0xFFF00000
 156 #define wmask_k_sz1gb 0x3FF00000
 157 union TPchipWSBA {
 158         struct  {
 159                 unsigned wsba_v_ena : 1;
 160                 unsigned wsba_v_sg : 1;
 161                 unsigned wsba_v_ptp : 1;
 162                 unsigned wsba_v_rsvd1 : 17;
 163                 unsigned wsba_v_addr : 12;
 164                 unsigned wsba_v_rsvd2 : 32;
 165         } wsba_r_bits;
 166         int wsba_q_whole [2];
 167 };
 168
 169 /*
 170  * TSUNAMI Pchip Control Register
 171  */
 172 #define pctl_m_fdsc 0x1
 173 #define pctl_m_fbtb 0x2
 174 #define pctl_m_thdis 0x4
 175 #define pctl_m_chaindis 0x8
 176 #define pctl_m_tgtlat 0x10
 177 #define pctl_m_hole 0x20
 178 #define pctl_m_mwin 0x40
 179 #define pctl_m_arbena 0x80
 180 #define pctl_m_prigrp 0x7F00
 181 #define pctl_m_ppri 0x8000
 182 #define pctl_m_rsvd1 0x30000
 183 #define pctl_m_eccen 0x40000
 184 #define pctl_m_padm 0x80000
 185 #define pctl_m_cdqmax 0xF00000
 186 #define pctl_m_rev 0xFF000000
 187 #define pctl_m_crqmax 0xF00000000UL
 188 #define pctl_m_ptpmax 0xF000000000UL
 189 #define pctl_m_pclkx 0x30000000000UL
 190 #define pctl_m_fdsdis 0x40000000000UL
 191 #define pctl_m_fdwdis 0x80000000000UL
 192 #define pctl_m_ptevrfy 0x100000000000UL
 193 #define pctl_m_rpp 0x200000000000UL
 194 #define pctl_m_pid 0xC00000000000UL
 195 #define pctl_m_rsvd2 0xFFFF000000000000UL
 196
 197 union TPchipPCTL {
 198         struct {
 199                 unsigned pctl_v_fdsc : 1;
 200                 unsigned pctl_v_fbtb : 1;
 201                 unsigned pctl_v_thdis : 1;
 202                 unsigned pctl_v_chaindis : 1;
 203                 unsigned pctl_v_tgtlat : 1;
 204                 unsigned pctl_v_hole : 1;
 205                 unsigned pctl_v_mwin : 1;
 206                 unsigned pctl_v_arbena : 1;
 207                 unsigned pctl_v_prigrp : 7;
 208                 unsigned pctl_v_ppri : 1;
 209                 unsigned pctl_v_rsvd1 : 2;
 210                 unsigned pctl_v_eccen : 1;
 211                 unsigned pctl_v_padm : 1;
 212                 unsigned pctl_v_cdqmax : 4;
 213                 unsigned pctl_v_rev : 8;
 214                 unsigned pctl_v_crqmax : 4;
 215                 unsigned pctl_v_ptpmax : 4;
 216                 unsigned pctl_v_pclkx : 2;
 217                 unsigned pctl_v_fdsdis : 1;
 218                 unsigned pctl_v_fdwdis : 1;
 219                 unsigned pctl_v_ptevrfy : 1;
 220                 unsigned pctl_v_rpp : 1;
 221                 unsigned pctl_v_pid : 2;
 222                 unsigned pctl_v_rsvd2 : 16;
 223         } pctl_r_bits;
 224         int pctl_q_whole [2];
 225 };
 226
 227 /*
 228  * TSUNAMI Pchip Error Mask Register.
 229  */
 230 #define perrmask_m_lost 0x1
 231 #define perrmask_m_serr 0x2
 232 #define perrmask_m_perr 0x4
 233 #define perrmask_m_dcrto 0x8
 234 #define perrmask_m_sge 0x10
 235 #define perrmask_m_ape 0x20
 236 #define perrmask_m_ta 0x40
 237 #define perrmask_m_rdpe 0x80
 238 #define perrmask_m_nds 0x100
 239 #define perrmask_m_rto 0x200
 240 #define perrmask_m_uecc 0x400
 241 #define perrmask_m_cre 0x800
 242 #define perrmask_m_rsvd 0xFFFFFFFFFFFFF000UL
 243 union TPchipPERRMASK {
 244         struct  {
 245                 unsigned int perrmask_v_lost : 1;
 246                 unsigned perrmask_v_serr : 1;
 247                 unsigned perrmask_v_perr : 1;
 248                 unsigned perrmask_v_dcrto : 1;
 249                 unsigned perrmask_v_sge : 1;
 250                 unsigned perrmask_v_ape : 1;
 251                 unsigned perrmask_v_ta : 1;
 252                 unsigned perrmask_v_rdpe : 1;
 253                 unsigned perrmask_v_nds : 1;
 254                 unsigned perrmask_v_rto : 1;
 255                 unsigned perrmask_v_uecc : 1;
 256                 unsigned perrmask_v_cre : 1;
 257                 unsigned perrmask_v_rsvd1 : 20;
 258                 unsigned perrmask_v_rsvd2 : 32;
 259         } perrmask_r_bits;
 260         int perrmask_q_whole [2];
 261 };
 262
 263 /*
 264  * Memory spaces:
 265  */
 266 #define HOSE(h) (((unsigned long)(h)) << 33)
 267
 268 #define TSUNAMI_MEM(h)       (IDENT_ADDR + TS_BIAS + 0x000000000UL + HOSE(h))
 269 #define _TSUNAMI_IACK_SC(h)  (IDENT_ADDR + TS_BIAS + 0x1F8000000UL + HOSE(h))
 270 #define TSUNAMI_IO(h)        (IDENT_ADDR + TS_BIAS + 0x1FC000000UL + HOSE(h))
 271 #define TSUNAMI_CONF(h)      (IDENT_ADDR + TS_BIAS + 0x1FE000000UL + HOSE(h))
 272
 273 #define TSUNAMI_IACK_SC      _TSUNAMI_IACK_SC(0) /* hack! */
 274
 275
 276 /*
 277  * Data structure for handling TSUNAMI machine checks:
 278  */
 279 struct el_TSUNAMI_sysdata_mcheck {
 280 };
 281
 282
 283 #ifdef __KERNEL__
 284
 285 #ifndef __EXTERN_INLINE
 286 #define __EXTERN_INLINE extern inline
 287 #define __IO_EXTERN_INLINE
 288 #endif
 289
 290 /*
 291  * Translate physical memory address as seen on (PCI) bus into
 292  * a kernel virtual address and vv.
 293  */
 294 __EXTERN_INLINE unsigned long tsunami_virt_to_bus(void * address)
 295 {
 296         return virt_to_phys(address) + TSUNAMI_DMA_WIN_BASE;
 297 }
 298
 299 __EXTERN_INLINE void * tsunami_bus_to_virt(unsigned long address)
 300 {
 301         return phys_to_virt(address - TSUNAMI_DMA_WIN_BASE);
 302 }
 303
 304 /*
 305  * I/O functions:
 306  *
 307  * TSUNAMI, the 21??? PCI/memory support chipset for the EV6 (21264)
 308  * can only use linear accesses to get at PCI memory and I/O spaces.
 309  */
 310
 311 #define vucp    volatile unsigned char *
 312 #define vusp    volatile unsigned short *
 313 #define vuip    volatile unsigned int *
 314 #define vulp    volatile unsigned long *
 315
 316 #define XADDR   ((addr) & 0xffffffffUL)
 317 #define XHOSE   (((addr) >> 32) & 3UL)
 318
 319 __EXTERN_INLINE unsigned int tsunami_inb(unsigned long addr)
 320 {
 321         return __kernel_ldbu(*(vucp)(XADDR + TSUNAMI_IO(XHOSE)));
 322 }
 323
 324 __EXTERN_INLINE void tsunami_outb(unsigned char b, unsigned long addr)
 325 {
 326         __kernel_stb(b, *(vucp)(XADDR + TSUNAMI_IO(XHOSE)));
 327         mb();
 328 }
 329
 330 __EXTERN_INLINE unsigned int tsunami_inw(unsigned long addr)
 331 {
 332         return __kernel_ldwu(*(vusp)(XADDR + TSUNAMI_IO(XHOSE)));
 333 }
 334
 335 __EXTERN_INLINE void tsunami_outw(unsigned short b, unsigned long addr)
 336 {
 337         __kernel_stw(b, *(vusp)(XADDR + TSUNAMI_IO(XHOSE)));
 338         mb();
 339 }
 340
 341 __EXTERN_INLINE unsigned int tsunami_inl(unsigned long addr)
 342 {
 343         return *(vuip)(XADDR + TSUNAMI_IO(XHOSE));
 344 }
 345
 346 __EXTERN_INLINE void tsunami_outl(unsigned int b, unsigned long addr)
 347 {
 348         *(vuip)(XADDR + TSUNAMI_IO(XHOSE)) = b;
 349         mb();
 350 }
 351
 352 /*
 353  * Memory functions.  all accesses are done through linear space.
 354  */
 355
 356 __EXTERN_INLINE unsigned long tsunami_readb(unsigned long addr)
 357 {
 358         return __kernel_ldbu(*(vucp)(XADDR + TSUNAMI_MEM(XHOSE)));
 359 }
 360
 361 __EXTERN_INLINE unsigned long tsunami_readw(unsigned long addr)
 362 {
 363         return __kernel_ldwu(*(vusp)(XADDR + TSUNAMI_MEM(XHOSE)));
 364 }
 365
 366 __EXTERN_INLINE unsigned long tsunami_readl(unsigned long addr)
 367 {
 368         return *(vuip)(XADDR + TSUNAMI_MEM(XHOSE));
 369 }
 370
 371 __EXTERN_INLINE unsigned long tsunami_readq(unsigned long addr)
 372 {
 373         return *(vulp)(XADDR + TSUNAMI_MEM(XHOSE));
 374 }
 375
 376 __EXTERN_INLINE void tsunami_writeb(unsigned char b, unsigned long addr)
 377 {
 378         __kernel_stb(b, *(vucp)(XADDR + TSUNAMI_MEM(XHOSE)));
 379         mb();
 380 }
 381
 382 __EXTERN_INLINE void tsunami_writew(unsigned short b, unsigned long addr)
 383 {
 384         __kernel_stw(b, *(vusp)(XADDR + TSUNAMI_MEM(XHOSE)));
 385         mb();
 386 }
 387
 388 __EXTERN_INLINE void tsunami_writel(unsigned int b, unsigned long addr)
 389 {
 390         *(vuip)(XADDR + TSUNAMI_MEM(XHOSE)) = b;
 391         mb();
 392 }
 393
 394 __EXTERN_INLINE void tsunami_writeq(unsigned long b, unsigned long addr)
 395 {
 396         *(vulp)(XADDR + TSUNAMI_MEM(XHOSE)) = b;
 397         mb();
 398 }
 399
 400 /* Find the DENSE memory area for a given bus address.  */
 401
 402 __EXTERN_INLINE unsigned long tsunami_dense_mem(unsigned long addr)
 403 {
 404         return TSUNAMI_MEM(XHOSE);
 405 }
 406
 407 #undef vucp
 408 #undef vusp
 409 #undef vuip
 410 #undef vulp
 411
 412 #undef XADDR
 413 #undef XHOSE
 414
 415 #ifdef __WANT_IO_DEF
 416
 417 #define virt_to_bus     tsunami_virt_to_bus
 418 #define bus_to_virt     tsunami_bus_to_virt
 419
 420 #define __inb           tsunami_inb
 421 #define __inw           tsunami_inw
 422 #define __inl           tsunami_inl
 423 #define __outb          tsunami_outb
 424 #define __outw          tsunami_outw
 425 #define __outl          tsunami_outl
 426 #define __readb         tsunami_readb
 427 #define __readw         tsunami_readw
 428 #define __writeb        tsunami_writeb
 429 #define __writew        tsunami_writew
 430 #define __readl         tsunami_readl
 431 #define __readq         tsunami_readq
 432 #define __writel        tsunami_writel
 433 #define __writeq        tsunami_writeq
 434 #define dense_mem       tsunami_dense_mem
 435
 436 #define inb(port) __inb((port))
 437 #define inw(port) __inw((port))
 438 #define inl(port) __inl((port))
 439
 440 #define outb(v, port) __outb((v),(port))
 441 #define outw(v, port) __outw((v),(port))
 442 #define outl(v, port) __outl((v),(port))
 443
 444 #define readb(a)        __readb((unsigned long)(a))
 445 #define readw(a)        __readw((unsigned long)(a))
 446 #define readl(a)        __readl((unsigned long)(a))
 447 #define readq(a)        __readq((unsigned long)(a))
 448
 449 #define writeb(v,a)     __writeb((v),(unsigned long)(a))
 450 #define writew(v,a)     __writew((v),(unsigned long)(a))
 451 #define writel(v,a)     __writel((v),(unsigned long)(a))
 452 #define writeq(v,a)     __writeq((v),(unsigned long)(a))
 453
 454 #endif /* __WANT_IO_DEF */
 455
 456 #ifdef __IO_EXTERN_INLINE
 457 #undef __EXTERN_INLINE
 458 #undef __IO_EXTERN_INLINE
 459 #endif
 460
 461 #endif /* __KERNEL__ */
 462
 463 #endif /* __ALPHA_TSUNAMI__H__ */