?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Linux-2.3.3 and a short hiatus..
[davej-history.git] / include / asm-alpha / core_cia.h
blob3407d0159de0b75130eeffeefae0730179562a4e
1 #ifndef __ALPHA_CIA__H__
2 #define __ALPHA_CIA__H__
3
4 #include <linux/config.h>
5 #include <linux/types.h>
6 #include <asm/compiler.h>
7
8 /*
9 * CIA is the internal name for the 2117x chipset which provides
10 * memory controller and PCI access for the 21164 chip based systems.
11 *
12 * This file is based on:
13 *
14 * DECchip 21171 Core Logic Chipset
15 * Technical Reference Manual
16 *
17 * EC-QE18B-TE
18 *
19 * david.rusling@reo.mts.dec.com Initial Version.
20 *
21 */
22
23 /*------------------------------------------------------------------------**
24 ** **
25 ** EB164 I/O procedures **
26 ** **
27 ** inport[b|w|t|l], outport[b|w|t|l] 8:16:24:32 IO xfers **
28 ** inportbxt: 8 bits only **
29 ** inport: alias of inportw **
30 ** outport: alias of outportw **
31 ** **
32 ** inmem[b|w|t|l], outmem[b|w|t|l] 8:16:24:32 ISA memory xfers **
33 ** inmembxt: 8 bits only **
34 ** inmem: alias of inmemw **
35 ** outmem: alias of outmemw **
36 ** **
37 **------------------------------------------------------------------------*/
38
39
40 /* CIA ADDRESS BIT DEFINITIONS
41 *
42 * 3 3 3 3|3 3 3 3|3 3 2 2|2 2 2 2|2 2 2 2|1 1 1 1|1 1 1 1|1 1
43 * 9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0|9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0
44 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
45 * |1| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |0|0|0|
46 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
47 * | \_/ \_/
48 * | | |
49 * +-- IO space, not cached. Byte Enable --+ |
50 * Transfer Length --+
51 *
52 *
53 *
54 * Byte Transfer
55 * Enable Length Transfer Byte Address
56 * adr<6:5> adr<4:3> Length Enable Adder
57 * ---------------------------------------------
58 * 00 00 Byte 1110 0x000
59 * 01 00 Byte 1101 0x020
60 * 10 00 Byte 1011 0x040
61 * 11 00 Byte 0111 0x060
62 *
63 * 00 01 Word 1100 0x008
64 * 01 01 Word 1001 0x028 <= Not supported in this code.
65 * 10 01 Word 0011 0x048
66 *
67 * 00 10 Tribyte 1000 0x010
68 * 01 10 Tribyte 0001 0x030
69 *
70 * 10 11 Longword 0000 0x058
71 *
72 * Note that byte enables are asserted low.
73 *
74 */
75
76 #define CIA_MEM_R1_MASK 0x1fffffff /* SPARSE Mem region 1 mask is 29 bits */
77 #define CIA_MEM_R2_MASK 0x07ffffff /* SPARSE Mem region 2 mask is 27 bits */
78 #define CIA_MEM_R3_MASK 0x03ffffff /* SPARSE Mem region 3 mask is 26 bits */
79
80 #define CIA_DMA_WIN_BASE_DEFAULT (1024*1024*1024)
81 #define CIA_DMA_WIN_SIZE_DEFAULT (1024*1024*1024)
82
83 #if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_SRM_SETUP)
84 #define CIA_DMA_WIN_BASE alpha_mv.dma_win_base
85 #define CIA_DMA_WIN_SIZE alpha_mv.dma_win_size
86 #else
87 #define CIA_DMA_WIN_BASE CIA_DMA_WIN_SIZE_DEFAULT
88 #define CIA_DMA_WIN_SIZE CIA_DMA_WIN_SIZE_DEFAULT
89 #endif
90
91 /*
92 * 21171-CA Control and Status Registers (p4-1)
93 */
94 #define CIA_IOC_CIA_REV (IDENT_ADDR + 0x8740000080UL)
95 #define CIA_IOC_PCI_LAT (IDENT_ADDR + 0x87400000C0UL)
96 #define CIA_IOC_CIA_CTRL (IDENT_ADDR + 0x8740000100UL)
97 #define CIA_IOC_CIA_CNFG (IDENT_ADDR + 0x8740000140UL)
98 #define CIA_IOC_HAE_MEM (IDENT_ADDR + 0x8740000400UL)
99 #define CIA_IOC_HAE_IO (IDENT_ADDR + 0x8740000440UL)
100 #define CIA_IOC_CFG (IDENT_ADDR + 0x8740000480UL)
101 #define CIA_IOC_CACK_EN (IDENT_ADDR + 0x8740000600UL)
102
103 /*
104 * 21171-CA Diagnostic Registers (p4-2)
105 */
106 #define CIA_IOC_CIA_DIAG (IDENT_ADDR + 0x8740002000UL)
107 #define CIA_IOC_DIAG_CHECK (IDENT_ADDR + 0x8740003000UL)
108
109 /*
110 * 21171-CA Performance Monitor registers (p4-3)
111 */
112 #define CIA_IOC_PERF_MONITOR (IDENT_ADDR + 0x8740004000UL)
113 #define CIA_IOC_PERF_CONTROL (IDENT_ADDR + 0x8740004040UL)
114
115 /*
116 * 21171-CA Error registers (p4-3)
117 */
118 #define CIA_IOC_CPU_ERR0 (IDENT_ADDR + 0x8740008000UL)
119 #define CIA_IOC_CPU_ERR1 (IDENT_ADDR + 0x8740008040UL)
120 #define CIA_IOC_CIA_ERR (IDENT_ADDR + 0x8740008200UL)
121 #define CIA_IOC_CIA_STAT (IDENT_ADDR + 0x8740008240UL)
122 #define CIA_IOC_ERR_MASK (IDENT_ADDR + 0x8740008280UL)
123 #define CIA_IOC_CIA_SYN (IDENT_ADDR + 0x8740008300UL)
124 #define CIA_IOC_MEM_ERR0 (IDENT_ADDR + 0x8740008400UL)
125 #define CIA_IOC_MEM_ERR1 (IDENT_ADDR + 0x8740008440UL)
126 #define CIA_IOC_PCI_ERR0 (IDENT_ADDR + 0x8740008800UL)
127 #define CIA_IOC_PCI_ERR1 (IDENT_ADDR + 0x8740008840UL)
128 #define CIA_IOC_PCI_ERR3 (IDENT_ADDR + 0x8740008880UL)
129
130 /*
131 * 2117A-CA PCI Address Translation Registers.
132 */
133 #define CIA_IOC_PCI_TBIA (IDENT_ADDR + 0x8760000100UL)
134
135 #define CIA_IOC_PCI_W0_BASE (IDENT_ADDR + 0x8760000400UL)
136 #define CIA_IOC_PCI_W0_MASK (IDENT_ADDR + 0x8760000440UL)
137 #define CIA_IOC_PCI_T0_BASE (IDENT_ADDR + 0x8760000480UL)
138
139 #define CIA_IOC_PCI_W1_BASE (IDENT_ADDR + 0x8760000500UL)
140 #define CIA_IOC_PCI_W1_MASK (IDENT_ADDR + 0x8760000540UL)
141 #define CIA_IOC_PCI_T1_BASE (IDENT_ADDR + 0x8760000580UL)
142
143 #define CIA_IOC_PCI_W2_BASE (IDENT_ADDR + 0x8760000600UL)
144 #define CIA_IOC_PCI_W2_MASK (IDENT_ADDR + 0x8760000640UL)
145 #define CIA_IOC_PCI_T2_BASE (IDENT_ADDR + 0x8760000680UL)
146
147 #define CIA_IOC_PCI_W3_BASE (IDENT_ADDR + 0x8760000700UL)
148 #define CIA_IOC_PCI_W3_MASK (IDENT_ADDR + 0x8760000740UL)
149 #define CIA_IOC_PCI_T3_BASE (IDENT_ADDR + 0x8760000780UL)
150
151 /*
152 * 21171-CA System configuration registers (p4-3)
153 */
154 #define CIA_IOC_MCR (IDENT_ADDR + 0x8750000000UL)
155 #define CIA_IOC_MBA0 (IDENT_ADDR + 0x8750000600UL)
156 #define CIA_IOC_MBA2 (IDENT_ADDR + 0x8750000680UL)
157 #define CIA_IOC_MBA4 (IDENT_ADDR + 0x8750000700UL)
158 #define CIA_IOC_MBA6 (IDENT_ADDR + 0x8750000780UL)
159 #define CIA_IOC_MBA8 (IDENT_ADDR + 0x8750000800UL)
160 #define CIA_IOC_MBAA (IDENT_ADDR + 0x8750000880UL)
161 #define CIA_IOC_MBAC (IDENT_ADDR + 0x8750000900UL)
162 #define CIA_IOC_MBAE (IDENT_ADDR + 0x8750000980UL)
163 #define CIA_IOC_TMG0 (IDENT_ADDR + 0x8750000B00UL)
164 #define CIA_IOC_TMG1 (IDENT_ADDR + 0x8750000B40UL)
165 #define CIA_IOC_TMG2 (IDENT_ADDR + 0x8750000B80UL)
166
167 /*
168 * Memory spaces:
169 */
170 #define CIA_IACK_SC (IDENT_ADDR + 0x8720000000UL)
171 #define CIA_CONF (IDENT_ADDR + 0x8700000000UL)
172 #define CIA_IO (IDENT_ADDR + 0x8580000000UL)
173 #define CIA_SPARSE_MEM (IDENT_ADDR + 0x8000000000UL)
174 #define CIA_SPARSE_MEM_R2 (IDENT_ADDR + 0x8400000000UL)
175 #define CIA_SPARSE_MEM_R3 (IDENT_ADDR + 0x8500000000UL)
176 #define CIA_DENSE_MEM (IDENT_ADDR + 0x8600000000UL)
177
178 /*
179 * ALCOR's GRU ASIC registers
180 */
181 #define GRU_INT_REQ (IDENT_ADDR + 0x8780000000UL)
182 #define GRU_INT_MASK (IDENT_ADDR + 0x8780000040UL)
183 #define GRU_INT_EDGE (IDENT_ADDR + 0x8780000080UL)
184 #define GRU_INT_HILO (IDENT_ADDR + 0x87800000C0UL)
185 #define GRU_INT_CLEAR (IDENT_ADDR + 0x8780000100UL)
186
187 #define GRU_CACHE_CNFG (IDENT_ADDR + 0x8780000200UL)
188 #define GRU_SCR (IDENT_ADDR + 0x8780000300UL)
189 #define GRU_LED (IDENT_ADDR + 0x8780000800UL)
190 #define GRU_RESET (IDENT_ADDR + 0x8780000900UL)
191
192 #define ALCOR_GRU_INT_REQ_BITS 0x800fffffUL
193 #define XLT_GRU_INT_REQ_BITS 0x80003fffUL
194 #define GRU_INT_REQ_BITS (alpha_mv.sys.cia.gru_int_req_bits+0)
195
196
197 /*
198 * Bit definitions for I/O Controller status register 0:
199 */
200 #define CIA_IOC_STAT0_CMD 0xf
201 #define CIA_IOC_STAT0_ERR (1<<4)
202 #define CIA_IOC_STAT0_LOST (1<<5)
203 #define CIA_IOC_STAT0_THIT (1<<6)
204 #define CIA_IOC_STAT0_TREF (1<<7)
205 #define CIA_IOC_STAT0_CODE_SHIFT 8
206 #define CIA_IOC_STAT0_CODE_MASK 0x7
207 #define CIA_IOC_STAT0_P_NBR_SHIFT 13
208 #define CIA_IOC_STAT0_P_NBR_MASK 0x7ffff
209
210 #define CIA_HAE_ADDRESS CIA_IOC_HAE_MEM
211
212 /*
213 * Data structure for handling CIA machine checks.
214 */
215
216 /* EV5-specific info. */
217 struct el_CIA_procdata {
218 unsigned long shadow[8]; /* PALmode shadow registers */
219 unsigned long paltemp[24]; /* PAL temporary registers */
220 /* EV5-specific fields */
221 unsigned long exc_addr; /* Address of excepting instruction. */
222 unsigned long exc_sum; /* Summary of arithmetic traps. */
223 unsigned long exc_mask; /* Exception mask (from exc_sum). */
224 unsigned long exc_base; /* PALbase at time of exception. */
225 unsigned long isr; /* Interrupt summary register. */
226 unsigned long icsr; /* Ibox control register. */
227 unsigned long ic_perr_stat;
228 unsigned long dc_perr_stat;
229 unsigned long va; /* Effective VA of fault or miss. */
230 unsigned long mm_stat;
231 unsigned long sc_addr;
232 unsigned long sc_stat;
233 unsigned long bc_tag_addr;
234 unsigned long ei_addr;
235 unsigned long fill_syn;
236 unsigned long ei_stat;
237 unsigned long ld_lock;
238 };
239
240 /* System-specific info. */
241 struct el_CIA_sysdata_mcheck {
242 unsigned long coma_gcr;
243 unsigned long coma_edsr;
244 unsigned long coma_ter;
245 unsigned long coma_elar;
246 unsigned long coma_ehar;
247 unsigned long coma_ldlr;
248 unsigned long coma_ldhr;
249 unsigned long coma_base0;
250 unsigned long coma_base1;
251 unsigned long coma_base2;
252 unsigned long coma_cnfg0;
253 unsigned long coma_cnfg1;
254 unsigned long coma_cnfg2;
255 unsigned long epic_dcsr;
256 unsigned long epic_pear;
257 unsigned long epic_sear;
258 unsigned long epic_tbr1;
259 unsigned long epic_tbr2;
260 unsigned long epic_pbr1;
261 unsigned long epic_pbr2;
262 unsigned long epic_pmr1;
263 unsigned long epic_pmr2;
264 unsigned long epic_harx1;
265 unsigned long epic_harx2;
266 unsigned long epic_pmlt;
267 unsigned long epic_tag0;
268 unsigned long epic_tag1;
269 unsigned long epic_tag2;
270 unsigned long epic_tag3;
271 unsigned long epic_tag4;
272 unsigned long epic_tag5;
273 unsigned long epic_tag6;
274 unsigned long epic_tag7;
275 unsigned long epic_data0;
276 unsigned long epic_data1;
277 unsigned long epic_data2;
278 unsigned long epic_data3;
279 unsigned long epic_data4;
280 unsigned long epic_data5;
281 unsigned long epic_data6;
282 unsigned long epic_data7;
283 };
284
285
286 #ifdef __KERNEL__
287
288 #ifndef __EXTERN_INLINE
289 #define __EXTERN_INLINE extern inline
290 #define __IO_EXTERN_INLINE
291 #endif
292
293 /*
294 * Translate physical memory address as seen on (PCI) bus into
295 * a kernel virtual address and vv.
296 */
297
298 __EXTERN_INLINE unsigned long cia_virt_to_bus(void * address)
299 {
300 return virt_to_phys(address) + CIA_DMA_WIN_BASE;
301 }
302
303 __EXTERN_INLINE void * cia_bus_to_virt(unsigned long address)
304 {
305 return phys_to_virt(address - CIA_DMA_WIN_BASE);
306 }
307
308 /*
309 * I/O functions:
310 *
311 * CIA (the 2117x PCI/memory support chipset for the EV5 (21164)
312 * series of processors uses a sparse address mapping scheme to
313 * get at PCI memory and I/O.
314 */
315
316 #define vip volatile int *
317 #define vuip volatile unsigned int *
318 #define vulp volatile unsigned long *
319
320 __EXTERN_INLINE unsigned int cia_inb(unsigned long addr)
321 {
322 long result;
323 result = *(vip) ((addr << 5) + CIA_IO + 0x00);
324 return __kernel_extbl(result, addr & 3);
325 }
326
327 __EXTERN_INLINE void cia_outb(unsigned char b, unsigned long addr)
328 {
329 unsigned long w = __kernel_insbl(b, addr & 3);
330 *(vuip) ((addr << 5) + CIA_IO + 0x00) = w;
331 mb();
332 }
333
334 __EXTERN_INLINE unsigned int cia_inw(unsigned long addr)
335 {
336 long result;
337 result = *(vip) ((addr << 5) + CIA_IO + 0x08);
338 return __kernel_extwl(result, addr & 3);
339 }
340
341 __EXTERN_INLINE void cia_outw(unsigned short b, unsigned long addr)
342 {
343 unsigned long w = __kernel_inswl(b, addr & 3);
344 *(vuip) ((addr << 5) + CIA_IO + 0x08) = w;
345 mb();
346 }
347
348 __EXTERN_INLINE unsigned int cia_inl(unsigned long addr)
349 {
350 return *(vuip) ((addr << 5) + CIA_IO + 0x18);
351 }
352
353 __EXTERN_INLINE void cia_outl(unsigned int b, unsigned long addr)
354 {
355 *(vuip) ((addr << 5) + CIA_IO + 0x18) = b;
356 mb();
357 }
358
359
360 /*
361 * Memory functions. 64-bit and 32-bit accesses are done through
362 * dense memory space, everything else through sparse space.
363 *
364 * For reading and writing 8 and 16 bit quantities we need to
365 * go through one of the three sparse address mapping regions
366 * and use the HAE_MEM CSR to provide some bits of the address.
367 * The following few routines use only sparse address region 1
368 * which gives 1Gbyte of accessible space which relates exactly
369 * to the amount of PCI memory mapping *into* system address space.
370 * See p 6-17 of the specification but it looks something like this:
371 *
372 * 21164 Address:
373 *
374 * 3 2 1
375 * 9876543210987654321098765432109876543210
376 * 1ZZZZ0.PCI.QW.Address............BBLL
377 *
378 * ZZ = SBZ
379 * BB = Byte offset
380 * LL = Transfer length
381 *
382 * PCI Address:
383 *
384 * 3 2 1
385 * 10987654321098765432109876543210
386 * HHH....PCI.QW.Address........ 00
387 *
388 * HHH = 31:29 HAE_MEM CSR
389 *
390 */
391
392 __EXTERN_INLINE unsigned long cia_srm_base(unsigned long addr)
393 {
394 unsigned long mask, base;
395
396 if (addr >= alpha_mv.sm_base_r1
397 && addr <= alpha_mv.sm_base_r1 + CIA_MEM_R1_MASK) {
398 mask = CIA_MEM_R1_MASK;
399 base = CIA_SPARSE_MEM;
400 }
401 else if (addr >= alpha_mv.sm_base_r2
402 && addr <= alpha_mv.sm_base_r2 + CIA_MEM_R2_MASK) {
403 mask = CIA_MEM_R2_MASK;
404 base = CIA_SPARSE_MEM_R2;
405 }
406 else if (addr >= alpha_mv.sm_base_r3
407 && addr <= alpha_mv.sm_base_r3 + CIA_MEM_R3_MASK) {
408 mask = CIA_MEM_R3_MASK;
409 base = CIA_SPARSE_MEM_R3;
410 }
411 else
412 {
413 #if 0
414 printk("cia: address 0x%lx not covered by HAE\n", addr);
415 #endif
416 return 0;
417 }
418
419 return ((addr & mask) << 5) + base;
420 }
421
422 __EXTERN_INLINE unsigned long cia_srm_readb(unsigned long addr)
423 {
424 unsigned long result, work;
425
426 if ((work = cia_srm_base(addr)) == 0)
427 return 0xff;
428 work += 0x00; /* add transfer length */
429
430 result = *(vip) work;
431 return __kernel_extbl(result, addr & 3);
432 }
433
434 __EXTERN_INLINE unsigned long cia_srm_readw(unsigned long addr)
435 {
436 unsigned long result, work;
437
438 if ((work = cia_srm_base(addr)) == 0)
439 return 0xffff;
440 work += 0x08; /* add transfer length */
441
442 result = *(vip) work;
443 return __kernel_extwl(result, addr & 3);
444 }
445
446 __EXTERN_INLINE void cia_srm_writeb(unsigned char b, unsigned long addr)
447 {
448 unsigned long work = cia_srm_base(addr), w;
449 if (work) {
450 work += 0x00; /* add transfer length */
451 w = __kernel_insbl(b, addr & 3);
452 *(vuip) work = w;
453 }
454 }
455
456 __EXTERN_INLINE void cia_srm_writew(unsigned short b, unsigned long addr)
457 {
458 unsigned long work = cia_srm_base(addr), w;
459 if (work) {
460 work += 0x08; /* add transfer length */
461 w = __kernel_inswl(b, addr & 3);
462 *(vuip) work = w;
463 }
464 }
465
466 __EXTERN_INLINE unsigned long cia_readb(unsigned long addr)
467 {
468 unsigned long result, msb;
469
470 msb = addr & 0xE0000000;
471 addr &= CIA_MEM_R1_MASK;
472 set_hae(msb);
473
474 result = *(vip) ((addr << 5) + CIA_SPARSE_MEM + 0x00);
475 return __kernel_extbl(result, addr & 3);
476 }
477
478 __EXTERN_INLINE unsigned long cia_readw(unsigned long addr)
479 {
480 unsigned long result, msb;
481
482 msb = addr & 0xE0000000;
483 addr &= CIA_MEM_R1_MASK;
484 set_hae(msb);
485
486 result = *(vip) ((addr << 5) + CIA_SPARSE_MEM + 0x08);
487 return __kernel_extwl(result, addr & 3);
488 }
489
490 __EXTERN_INLINE void cia_writeb(unsigned char b, unsigned long addr)
491 {
492 unsigned long msb, w;
493
494 msb = addr & 0xE0000000;
495 addr &= CIA_MEM_R1_MASK;
496 set_hae(msb);
497
498 w = __kernel_insbl(b, addr & 3);
499 *(vuip) ((addr << 5) + CIA_SPARSE_MEM + 0x00) = w;
500 }
501
502 __EXTERN_INLINE void cia_writew(unsigned short b, unsigned long addr)
503 {
504 unsigned long msb, w;
505
506 msb = addr & 0xE0000000;
507 addr &= CIA_MEM_R1_MASK;
508 set_hae(msb);
509
510 w = __kernel_inswl(b, addr & 3);
511 *(vuip) ((addr << 5) + CIA_SPARSE_MEM + 0x08) = w;
512 }
513
514 __EXTERN_INLINE unsigned long cia_readl(unsigned long addr)
515 {
516 return *(vuip) (addr + CIA_DENSE_MEM);
517 }
518
519 __EXTERN_INLINE unsigned long cia_readq(unsigned long addr)
520 {
521 return *(vulp) (addr + CIA_DENSE_MEM);
522 }
523
524 __EXTERN_INLINE void cia_writel(unsigned int b, unsigned long addr)
525 {
526 *(vuip) (addr + CIA_DENSE_MEM) = b;
527 }
528
529 __EXTERN_INLINE void cia_writeq(unsigned long b, unsigned long addr)
530 {
531 *(vulp) (addr + CIA_DENSE_MEM) = b;
532 }
533
534 /* Find the DENSE memory area for a given bus address. */
535
536 __EXTERN_INLINE unsigned long cia_dense_mem(unsigned long addr)
537 {
538 return CIA_DENSE_MEM;
539 }
540
541 #undef vip
542 #undef vuip
543 #undef vulp
544
545 #ifdef __WANT_IO_DEF
546
547 #define virt_to_bus cia_virt_to_bus
548 #define bus_to_virt cia_bus_to_virt
549 #define __inb cia_inb
550 #define __inw cia_inw
551 #define __inl cia_inl
552 #define __outb cia_outb
553 #define __outw cia_outw
554 #define __outl cia_outl
555
556 #ifdef CONFIG_ALPHA_SRM_SETUP
557 #define __readb cia_srm_readb
558 #define __readw cia_srm_readw
559 #define __writeb cia_srm_writeb
560 #define __writew cia_srm_writew
561 #else
562 #define __readb cia_readb
563 #define __readw cia_readw
564 #define __writeb cia_writeb
565 #define __writew cia_writew
566 #endif
567
568 #define __readl cia_readl
569 #define __readq cia_readq
570 #define __writel cia_writel
571 #define __writeq cia_writeq
572 #define dense_mem cia_dense_mem
573
574 #define inb(port) \
575 (__builtin_constant_p((port))?__inb(port):_inb(port))
576 #define outb(x, port) \
577 (__builtin_constant_p((port))?__outb((x),(port)):_outb((x),(port)))
578
579 #define inw(port) \
580 (__builtin_constant_p((port))?__inw(port):_inw(port))
581 #define outw(x, port) \
582 (__builtin_constant_p((port))?__outw((x),(port)):_outw((x),(port)))
583
584 #define inl(port) __inl(port)
585 #define outl(x,port) __outl((x),(port))
586
587 #define readl(a) __readl((unsigned long)(a))
588 #define readq(a) __readq((unsigned long)(a))
589 #define writel(v,a) __writel((v),(unsigned long)(a))
590 #define writeq(v,a) __writeq((v),(unsigned long)(a))
591
592 #endif /* __WANT_IO_DEF */
593
594 #ifdef __IO_EXTERN_INLINE
595 #undef __EXTERN_INLINE
596 #undef __IO_EXTERN_INLINE
597 #endif
598
599 #endif /* __KERNEL__ */
600
601 #endif /* __ALPHA_CIA__H__ */
Copy of Dave Jones history.git as used by http://archive.org/details/git-history-of-linux