include/asm-m68k/softirq.h

   1 #ifndef __M68K_SOFTIRQ_H
   2 #define __M68K_SOFTIRQ_H
   3
   4 /*
   5  * Software interrupts.. no SMP here either.
   6  */
   7
   8 #include <asm/atomic.h>
   9
  10 #define get_active_bhs()        (bh_mask & bh_active)
  11 #define clear_active_bhs(x)     atomic_clear_mask((x),&bh_active)
  12
  13 extern inline void init_bh(int nr, void (*routine)(void))
  14 {
  15         bh_base[nr] = routine;
  16         bh_mask_count[nr] = 0;
  17         bh_mask |= 1 << nr;
  18 }
  19
  20 extern inline void mark_bh(int nr)
  21 {
  22         set_bit(nr, &bh_active);
  23 }
  24
  25 /*
  26  * These use a mask count to correctly handle
  27  * nested disable/enable calls
  28  */
  29 extern inline void disable_bh(int nr)
  30 {
  31         bh_mask &= ~(1 << nr);
  32         bh_mask_count[nr]++;
  33 }
  34
  35 extern inline void enable_bh(int nr)
  36 {
  37         if (!--bh_mask_count[nr])
  38                 bh_mask |= 1 << nr;
  39 }
  40
  41 extern inline void remove_bh(int nr)
  42 {
  43         bh_base[nr] = NULL;
  44         bh_mask &= ~(1 << nr);
  45 }
  46
  47 extern unsigned int local_bh_count[NR_CPUS];
  48
  49 extern inline void start_bh_atomic(void)
  50 {
  51         local_bh_count[smp_processor_id()]++;
  52         barrier();
  53 }
  54
  55 extern inline void end_bh_atomic(void)
  56 {
  57         barrier();
  58         local_bh_count[smp_processor_id()]--;
  59 }
  60
  61 /* These are for the irq's testing the lock */
  62 #define softirq_trylock(cpu)  (local_bh_count[cpu] ? 0 : (local_bh_count[cpu]=1))
  63 #define softirq_endlock(cpu)  (local_bh_count[cpu] = 0)
  64 #define synchronize_bh()        do { } while (0)
  65
  66 #endif