2 * Intel IO-APIC support for multi-Pentium hosts.
4 * Copyright (C) 1997, 1998 Ingo Molnar, Hajnalka Szabo
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
10 #include <linux/sched.h>
11 #include <linux/smp_lock.h>
12 #include <linux/init.h>
13 #include <linux/delay.h>
19 * volatile is justified in this case, IO-APIC register contents
20 * might change spontaneously, GCC should not cache it
22 #define IO_APIC_BASE ((volatile int *)fix_to_virt(FIX_IO_APIC_BASE))
25 * The structure of the IO-APIC:
28 struct IO_APIC_reg_00
{
29 __u32 __reserved_2
: 24,
32 } __attribute__ ((packed
));
34 struct IO_APIC_reg_01
{
39 } __attribute__ ((packed
));
41 struct IO_APIC_reg_02
{
42 __u32 __reserved_2
: 24,
45 } __attribute__ ((packed
));
48 * # of IRQ routing registers
50 int nr_ioapic_registers
= 0;
52 enum ioapic_irq_destination_types
{
58 struct IO_APIC_route_entry
{
60 delivery_mode
: 3, /* 000: FIXED
64 dest_mode
: 1, /* 0: physical, 1: logical */
68 trigger
: 1, /* 0: edge, 1: level */
69 mask
: 1, /* 0: enabled, 1: disabled */
72 union { struct { __u32
84 } __attribute__ ((packed
));
87 * MP-BIOS irq configuration table structures:
90 enum mp_irq_source_types
{
97 int mp_irq_entries
= 0; /* # of MP IRQ source entries */
98 struct mpc_config_intsrc mp_irqs
[MAX_IRQ_SOURCES
];
99 /* MP IRQ source entries */
100 int mpc_default_type
= 0; /* non-0 if default (table-less)
105 * This is performance-critical, we want to do it O(1)
107 static int irq_2_pin
[NR_IRQS
];
109 static inline unsigned int io_apic_read(unsigned int reg
)
112 return *(IO_APIC_BASE
+4);
115 static inline void io_apic_write(unsigned int reg
, unsigned int value
)
118 *(IO_APIC_BASE
+4) = value
;
122 * Synchronize the IO-APIC and the CPU by doing
123 * a dummy read from the IO-APIC
125 static inline void io_apic_sync(void)
127 (void) *(IO_APIC_BASE
+4);
131 * We disable IO-APIC IRQs by setting their 'destination CPU mask' to
132 * zero. Trick, trick.
134 static inline void disable_IO_APIC_irq(unsigned int irq
)
136 int pin
= irq_2_pin
[irq
];
137 struct IO_APIC_route_entry entry
;
140 *(((int *)&entry
) + 1) = io_apic_read(0x11 + pin
* 2);
141 entry
.dest
.logical
.logical_dest
= 0x0;
142 io_apic_write(0x11 + 2 * pin
, *(((int *)&entry
) + 1));
147 static inline void enable_IO_APIC_irq(unsigned int irq
)
149 int pin
= irq_2_pin
[irq
];
150 struct IO_APIC_route_entry entry
;
153 *(((int *)&entry
) + 1) = io_apic_read(0x11 + pin
* 2);
154 entry
.dest
.logical
.logical_dest
= 0xff;
155 io_apic_write(0x11 + 2 * pin
, *(((int *)&entry
) + 1));
159 static inline void mask_IO_APIC_irq(unsigned int irq
)
161 int pin
= irq_2_pin
[irq
];
162 struct IO_APIC_route_entry entry
;
165 *(((int *)&entry
) + 0) = io_apic_read(0x10 + pin
* 2);
167 io_apic_write(0x10 + 2 * pin
, *(((int *)&entry
) + 0));
172 static inline void unmask_IO_APIC_irq(unsigned int irq
)
174 int pin
= irq_2_pin
[irq
];
175 struct IO_APIC_route_entry entry
;
178 *(((int *)&entry
) + 0) = io_apic_read(0x10 + pin
* 2);
180 io_apic_write(0x10 + 2 * pin
, *(((int *)&entry
) + 0));
184 static void __init
clear_IO_APIC_pin(unsigned int pin
)
186 struct IO_APIC_route_entry entry
;
189 * Disable it in the IO-APIC irq-routing table:
191 memset(&entry
, 0, sizeof(entry
));
193 io_apic_write(0x10 + 2 * pin
, *(((int *)&entry
) + 0));
194 io_apic_write(0x11 + 2 * pin
, *(((int *)&entry
) + 1));
199 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
200 * specific CPU-side IRQs.
204 int pirq_entries
[MAX_PIRQS
];
207 void __init
ioapic_pirq_setup(char *str
, int *ints
)
211 for (i
= 0; i
< MAX_PIRQS
; i
++)
212 pirq_entries
[i
] = -1;
216 printk("PIRQ redirection, trusting MP-BIOS.\n");
220 printk("PIRQ redirection, working around broken MP-BIOS.\n");
222 if (ints
[0] < MAX_PIRQS
)
225 for (i
= 0; i
< max
; i
++) {
226 printk("... PIRQ%d -> IRQ %d\n", i
, ints
[i
+1]);
228 * PIRQs are mapped upside down, usually.
230 pirq_entries
[MAX_PIRQS
-i
-1] = ints
[i
+1];
236 * Find the IRQ entry number of a certain pin.
238 static int __init
find_irq_entry(int pin
, int type
)
242 for (i
= 0; i
< mp_irq_entries
; i
++)
243 if ( (mp_irqs
[i
].mpc_irqtype
== type
) &&
244 (mp_irqs
[i
].mpc_dstirq
== pin
))
252 * Find the pin to which IRQ0 (ISA) is connected
254 static int __init
find_timer_pin(int type
)
258 for (i
= 0; i
< mp_irq_entries
; i
++) {
259 int lbus
= mp_irqs
[i
].mpc_srcbus
;
261 if ((mp_bus_id_to_type
[lbus
] == MP_BUS_ISA
) &&
262 (mp_irqs
[i
].mpc_irqtype
== type
) &&
263 (mp_irqs
[i
].mpc_srcbusirq
== 0x00))
265 return mp_irqs
[i
].mpc_dstirq
;
271 * Find a specific PCI IRQ entry.
272 * Not an initfunc, possibly needed by modules
274 int IO_APIC_get_PCI_irq_vector(int bus
, int slot
, int pci_pin
)
278 for (i
= 0; i
< mp_irq_entries
; i
++) {
279 int lbus
= mp_irqs
[i
].mpc_srcbus
;
281 if (IO_APIC_IRQ(mp_irqs
[i
].mpc_dstirq
) &&
282 (mp_bus_id_to_type
[lbus
] == MP_BUS_PCI
) &&
283 !mp_irqs
[i
].mpc_irqtype
&&
284 (bus
== mp_bus_id_to_pci_bus
[mp_irqs
[i
].mpc_srcbus
]) &&
285 (slot
== ((mp_irqs
[i
].mpc_srcbusirq
>> 2) & 0x1f)) &&
286 (pci_pin
== (mp_irqs
[i
].mpc_srcbusirq
& 3)))
288 return mp_irqs
[i
].mpc_dstirq
;
294 * There are broken mptables which register ISA+high-active+level IRQs,
295 * these are illegal and are converted here to ISA+high-active+edge
296 * IRQ sources. Careful, ISA+low-active+level is another broken entry
297 * type, it represents PCI IRQs 'embedded into an ISA bus', they have
298 * to be accepted. Yes, ugh.
301 static int __init
MPBIOS_polarity(int idx
)
303 int bus
= mp_irqs
[idx
].mpc_srcbus
;
307 * Determine IRQ line polarity (high active or low active):
309 switch (mp_irqs
[idx
].mpc_irqflag
& 3)
311 case 0: /* conforms, ie. bus-type dependent polarity */
313 switch (mp_bus_id_to_type
[bus
])
315 case MP_BUS_ISA
: /* ISA pin */
320 case MP_BUS_PCI
: /* PCI pin */
327 printk("broken BIOS!!\n");
334 case 1: /* high active */
339 case 2: /* reserved */
341 printk("broken BIOS!!\n");
345 case 3: /* low active */
350 default: /* invalid */
352 printk("broken BIOS!!\n");
360 static int __init
MPBIOS_trigger(int idx
)
362 int bus
= mp_irqs
[idx
].mpc_srcbus
;
366 * Determine IRQ trigger mode (edge or level sensitive):
368 switch ((mp_irqs
[idx
].mpc_irqflag
>>2) & 3)
370 case 0: /* conforms, ie. bus-type dependent */
372 switch (mp_bus_id_to_type
[bus
])
374 case MP_BUS_ISA
: /* ISA pin, edge */
379 case MP_BUS_PCI
: /* PCI pin, level */
386 printk("broken BIOS!!\n");
398 case 2: /* reserved */
400 printk("broken BIOS!!\n");
409 default: /* invalid */
411 printk("broken BIOS!!\n");
419 static int __init
trigger_flag_broken(int idx
)
421 int bus
= mp_irqs
[idx
].mpc_srcbus
;
422 int polarity
= MPBIOS_polarity(idx
);
423 int trigger
= MPBIOS_trigger(idx
);
425 if ( (mp_bus_id_to_type
[bus
] == MP_BUS_ISA
) &&
426 (polarity
== 0) /* active-high */ &&
427 (trigger
== 1) /* level */ )
429 return 1; /* broken */
434 static inline int irq_polarity(int idx
)
437 * There are no known BIOS bugs wrt polarity. yet.
439 return MPBIOS_polarity(idx
);
442 static inline int irq_trigger(int idx
)
444 int trigger
= MPBIOS_trigger(idx
);
446 if (trigger_flag_broken(idx
))
451 static int __init
pin_2_irq(int idx
, int pin
)
454 int bus
= mp_irqs
[idx
].mpc_srcbus
;
457 * Debugging check, we are in big trouble if this message pops up!
459 if (mp_irqs
[idx
].mpc_dstirq
!= pin
)
460 printk("broken BIOS or MPTABLE parser, ayiee!!\n");
462 switch (mp_bus_id_to_type
[bus
])
464 case MP_BUS_ISA
: /* ISA pin */
466 irq
= mp_irqs
[idx
].mpc_srcbusirq
;
469 case MP_BUS_PCI
: /* PCI pin */
472 * PCI IRQs are 'directly mapped'
479 printk("unknown bus type %d.\n",bus
);
486 * PCI IRQ command line redirection. Yes, limits are hardcoded.
488 if ((pin
>= 16) && (pin
<= 23)) {
489 if (pirq_entries
[pin
-16] != -1) {
490 if (!pirq_entries
[pin
-16]) {
491 printk("disabling PIRQ%d\n", pin
-16);
493 irq
= pirq_entries
[pin
-16];
494 printk("using PIRQ%d -> IRQ %d\n",
502 static inline int IO_APIC_irq_trigger(int irq
)
506 for (pin
= 0; pin
< nr_ioapic_registers
; pin
++) {
507 idx
= find_irq_entry(pin
,mp_INT
);
508 if ((idx
!= -1) && (irq
== pin_2_irq(idx
,pin
)))
509 return irq_trigger(idx
);
512 * nonexistent IRQs are edge default
517 static int __init
assign_irq_vector(int irq
)
519 static int current_vector
= IRQ0_TRAP_VECTOR
, offset
= 0;
520 if (IO_APIC_VECTOR(irq
) > 0)
521 return IO_APIC_VECTOR(irq
);
523 if (current_vector
> 0xFE) {
525 current_vector
= IRQ0_TRAP_VECTOR
+ offset
;
526 printk("WARNING: ASSIGN_IRQ_VECTOR wrapped back to %02X\n",
529 IO_APIC_VECTOR(irq
) = current_vector
;
530 return current_vector
;
533 void __init
setup_IO_APIC_irqs(void)
535 struct IO_APIC_route_entry entry
;
536 int pin
, idx
, bus
, irq
, first_notcon
= 1;
538 printk("init IO_APIC IRQs\n");
540 for (pin
= 0; pin
< nr_ioapic_registers
; pin
++) {
543 * add it to the IO-APIC irq-routing table:
545 memset(&entry
,0,sizeof(entry
));
547 entry
.delivery_mode
= dest_LowestPrio
;
548 entry
.dest_mode
= 1; /* logical delivery */
549 entry
.mask
= 0; /* enable IRQ */
550 entry
.dest
.logical
.logical_dest
= 0xff; /* all CPUs */
552 idx
= find_irq_entry(pin
,mp_INT
);
555 printk(" IO-APIC pin %d", pin
);
562 entry
.trigger
= irq_trigger(idx
);
563 entry
.polarity
= irq_polarity(idx
);
565 irq
= pin_2_irq(idx
,pin
);
566 irq_2_pin
[irq
] = pin
;
568 if (!IO_APIC_IRQ(irq
))
571 entry
.vector
= assign_irq_vector(irq
);
573 bus
= mp_irqs
[idx
].mpc_srcbus
;
575 if (trigger_flag_broken (idx
))
576 printk("broken BIOS, changing pin %d to edge\n", pin
);
578 io_apic_write(0x10+2*pin
, *(((int *)&entry
)+0));
579 io_apic_write(0x11+2*pin
, *(((int *)&entry
)+1));
583 printk(" not connected.\n");
586 void __init
setup_IO_APIC_irq_ISA_default(unsigned int irq
)
588 struct IO_APIC_route_entry entry
;
591 * add it to the IO-APIC irq-routing table:
593 memset(&entry
,0,sizeof(entry
));
595 entry
.delivery_mode
= dest_LowestPrio
; /* lowest prio */
596 entry
.dest_mode
= 1; /* logical delivery */
597 entry
.mask
= 0; /* unmask IRQ now */
598 entry
.dest
.logical
.logical_dest
= 0xff; /* all CPUs */
600 entry
.vector
= assign_irq_vector(irq
);
605 io_apic_write(0x10+2*irq
, *(((int *)&entry
)+0));
606 io_apic_write(0x11+2*irq
, *(((int *)&entry
)+1));
610 * Set up a certain pin as ExtINT delivered interrupt
612 void __init
setup_ExtINT_pin(unsigned int pin
)
614 struct IO_APIC_route_entry entry
;
617 * add it to the IO-APIC irq-routing table:
619 memset(&entry
,0,sizeof(entry
));
621 entry
.delivery_mode
= dest_ExtINT
;
622 entry
.dest_mode
= 1; /* logical delivery */
623 entry
.mask
= 0; /* unmask IRQ now */
624 entry
.dest
.logical
.logical_dest
= 0x01; /* all CPUs */
626 entry
.vector
= 0; /* it's ignored */
631 io_apic_write(0x10+2*pin
, *(((int *)&entry
)+0));
632 io_apic_write(0x11+2*pin
, *(((int *)&entry
)+1));
635 void __init
UNEXPECTED_IO_APIC(void)
637 printk(" WARNING: unexpected IO-APIC, please mail\n");
638 printk(" to linux-smp@vger.rutgers.edu\n");
641 void __init
print_IO_APIC(void)
644 struct IO_APIC_reg_00 reg_00
;
645 struct IO_APIC_reg_01 reg_01
;
646 struct IO_APIC_reg_02 reg_02
;
648 printk("number of MP IRQ sources: %d.\n", mp_irq_entries
);
649 printk("number of IO-APIC registers: %d.\n", nr_ioapic_registers
);
651 *(int *)®_00
= io_apic_read(0);
652 *(int *)®_01
= io_apic_read(1);
653 *(int *)®_02
= io_apic_read(2);
656 * We are a bit conservative about what we expect. We have to
657 * know about every hardware change ASAP.
659 printk("testing the IO APIC.......................\n");
661 printk(".... register #00: %08X\n", *(int *)®_00
);
662 printk("....... : physical APIC id: %02X\n", reg_00
.ID
);
663 if (reg_00
.__reserved_1
|| reg_00
.__reserved_2
)
664 UNEXPECTED_IO_APIC();
666 printk(".... register #01: %08X\n", *(int *)®_01
);
667 printk("....... : max redirection entries: %04X\n", reg_01
.entries
);
668 if ( (reg_01
.entries
!= 0x0f) && /* ISA-only Neptune boards */
669 (reg_01
.entries
!= 0x17) /* ISA+PCI boards */
671 UNEXPECTED_IO_APIC();
672 if (reg_01
.entries
== 0x0f)
673 printk("....... [IO-APIC cannot route PCI PIRQ 0-3]\n");
675 printk("....... : IO APIC version: %04X\n", reg_01
.version
);
676 if ( (reg_01
.version
!= 0x10) && /* oldest IO-APICs */
677 (reg_01
.version
!= 0x11) /* my IO-APIC */
679 UNEXPECTED_IO_APIC();
680 if (reg_01
.__reserved_1
|| reg_01
.__reserved_2
)
681 UNEXPECTED_IO_APIC();
683 printk(".... register #02: %08X\n", *(int *)®_02
);
684 printk("....... : arbitration: %02X\n", reg_02
.arbitration
);
685 if (reg_02
.__reserved_1
|| reg_02
.__reserved_2
)
686 UNEXPECTED_IO_APIC();
688 printk(".... IRQ redirection table:\n");
690 printk(" NR Log Phy ");
691 printk("Mask Trig IRR Pol Stat Dest Deli Vect: \n");
693 for (i
= 0; i
<= reg_01
.entries
; i
++) {
694 struct IO_APIC_route_entry entry
;
696 *(((int *)&entry
)+0) = io_apic_read(0x10+i
*2);
697 *(((int *)&entry
)+1) = io_apic_read(0x11+i
*2);
699 printk(" %02x %03X %02X ",
701 entry
.dest
.logical
.logical_dest
,
702 entry
.dest
.physical
.physical_dest
705 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
710 entry
.delivery_status
,
717 printk("IRQ to pin mappings:\n");
718 for (i
= 0; i
< NR_IRQS
; i
++)
719 printk("%d->%d ", i
, irq_2_pin
[i
]);
722 printk(".................................... done.\n");
727 static void __init
init_sym_mode(void)
731 for (i
= 0; i
< NR_IRQS
; i
++)
734 for (i
= 0; i
< MAX_PIRQS
; i
++)
735 pirq_entries
[i
] =- 1;
737 printk("enabling symmetric IO mode... ");
742 printk("...done.\n");
745 * The number of IO-APIC IRQ registers (== #pins):
748 struct IO_APIC_reg_01 reg_01
;
750 *(int *)®_01
= io_apic_read(1);
751 nr_ioapic_registers
= reg_01
.entries
+1;
755 * Do not trust the IO-APIC being empty at bootup
757 for (pin
= 0; pin
< nr_ioapic_registers
; pin
++)
758 clear_IO_APIC_pin(pin
);
762 * Not an initfunc, needed by the reboot code
764 void init_pic_mode(void)
766 printk("disabling symmetric IO mode... ");
769 printk("...done.\n");
772 char ioapic_OEM_ID
[16];
773 char ioapic_Product_ID
[16];
775 struct ioapic_list_entry
{
780 struct ioapic_list_entry __initdata ioapic_whitelist
[] = {
782 { "INTEL " , "PR440FX " },
783 { "INTEL " , "82440FX " },
788 struct ioapic_list_entry __initdata ioapic_blacklist
[] = {
790 { "OEM00000" , "PROD00000000" },
794 static int __init
in_ioapic_list(struct ioapic_list_entry
* table
)
796 for ( ; table
->oem_id
; table
++)
797 if ((!strcmp(table
->oem_id
,ioapic_OEM_ID
)) &&
798 (!strcmp(table
->product_id
,ioapic_Product_ID
)))
803 static int __init
ioapic_whitelisted(void)
806 * Right now, whitelist everything to see whether the new parsing
807 * routines really do work for everybody.
812 return in_ioapic_list(ioapic_whitelist
);
816 static int __init
ioapic_blacklisted(void)
818 return in_ioapic_list(ioapic_blacklist
);
821 static void __init
setup_ioapic_id(void)
823 struct IO_APIC_reg_00 reg_00
;
826 * 'default' mptable configurations mean a hardwired setup,
827 * 2 CPUs, 16 APIC registers. IO-APIC ID is usually set to 0,
828 * setting it to ID 2 should be fine.
832 * Sanity check, is ID 2 really free? Every APIC in the
833 * system must have a unique ID or we get lots of nice
834 * 'stuck on smp_invalidate_needed IPI wait' messages.
836 if (cpu_present_map
& (1<<0x2))
837 panic("APIC ID 2 already used");
842 *(int *)®_00
= io_apic_read(0);
843 printk("...changing IO-APIC physical APIC ID to 2...\n");
845 io_apic_write(0, *(int *)®_00
);
850 *(int *)®_00
= io_apic_read(0);
851 if (reg_00
.ID
!= 0x2)
852 panic("could not set ID");
855 static void __init
construct_default_ISA_mptable(void)
859 for (i
= 0; i
< 16; i
++) {
863 mp_irqs
[pos
].mpc_irqtype
= 0;
864 mp_irqs
[pos
].mpc_irqflag
= 0;
865 mp_irqs
[pos
].mpc_srcbus
= 0;
866 mp_irqs
[pos
].mpc_srcbusirq
= i
;
867 mp_irqs
[pos
].mpc_dstapic
= 0;
868 mp_irqs
[pos
].mpc_dstirq
= i
;
871 mp_irq_entries
= pos
;
872 mp_bus_id_to_type
[0] = MP_BUS_ISA
;
875 * MP specification 1.4 defines some extra rules for default
876 * configurations, fix them up here:
879 switch (mpc_default_type
)
887 mp_irqs
[0].mpc_dstirq
= 2;
894 * There is a nasty bug in some older SMP boards, their mptable lies
895 * about the timer IRQ. We do the following to work around the situation:
897 * - timer IRQ defaults to IO-APIC IRQ
898 * - if this function detects that timer IRQs are defunct, then we fall
899 * back to ISA timer IRQs
901 static int __init
timer_irq_works(void)
903 unsigned int t1
= jiffies
;
915 * In the SMP+IOAPIC case it might happen that there are an unspecified
916 * number of pending IRQ events unhandled. These cases are very rare,
917 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
918 * better to do it this way as thus we do not have to be aware of
919 * 'pending' interrupts in the IRQ path, except at this point.
921 static inline void self_IPI(unsigned int irq
)
923 irq_desc_t
*desc
= irq_desc
+ irq
;
925 if (desc
->events
&& !desc
->ipi
) {
927 send_IPI(APIC_DEST_SELF
, IO_APIC_VECTOR(irq
));
932 * Edge triggered needs to resend any interrupt
935 static void enable_edge_ioapic_irq(unsigned int irq
)
938 enable_IO_APIC_irq(irq
);
941 static void disable_edge_ioapic_irq(unsigned int irq
)
943 disable_IO_APIC_irq(irq
);
947 * Level triggered interrupts can just be masked.
949 static void enable_level_ioapic_irq(unsigned int irq
)
951 unmask_IO_APIC_irq(irq
);
954 static void disable_level_ioapic_irq(unsigned int irq
)
956 mask_IO_APIC_irq(irq
);
959 static void do_edge_ioapic_IRQ(unsigned int irq
, int cpu
, struct pt_regs
* regs
)
961 irq_desc_t
*desc
= irq_desc
+ irq
;
962 struct irqaction
* action
;
964 spin_lock(&irq_controller_lock
);
967 * Edge triggered IRQs can be acknowledged immediately
968 * and do not need to be masked.
975 * If the IRQ is disabled for whatever reason, we cannot
976 * use the action we have.
979 if (!(desc
->status
& (IRQ_DISABLED
| IRQ_INPROGRESS
))) {
980 action
= desc
->action
;
981 desc
->status
= IRQ_INPROGRESS
;
984 spin_unlock(&irq_controller_lock
);
987 * If there is no IRQ handler or it was disabled, exit early.
995 * Edge triggered interrupts need to remember
1001 handle_IRQ_event(irq
, regs
);
1003 spin_lock(&irq_controller_lock
);
1004 pending
= desc
->events
;
1008 spin_unlock(&irq_controller_lock
);
1010 desc
->status
&= IRQ_DISABLED
;
1011 spin_unlock(&irq_controller_lock
);
1016 static void do_level_ioapic_IRQ(unsigned int irq
, int cpu
,
1017 struct pt_regs
* regs
)
1019 irq_desc_t
*desc
= irq_desc
+ irq
;
1020 struct irqaction
* action
;
1022 spin_lock(&irq_controller_lock
);
1024 * In the level triggered case we first disable the IRQ
1025 * in the IO-APIC, then we 'early ACK' the IRQ, then we
1026 * handle it and enable the IRQ when finished.
1028 * disable has to happen before the ACK, to avoid IRQ storms.
1029 * So this all has to be within the spinlock.
1031 mask_IO_APIC_irq(irq
);
1036 * If the IRQ is disabled for whatever reason, we must
1037 * not enter the IRQ action.
1040 if (!(desc
->status
& (IRQ_DISABLED
| IRQ_INPROGRESS
))) {
1041 action
= desc
->action
;
1042 desc
->status
= IRQ_INPROGRESS
;
1046 spin_unlock(&irq_controller_lock
);
1048 /* Exit early if we had no action or it was disabled */
1052 irq_enter(cpu
, irq
);
1054 handle_IRQ_event(irq
, regs
);
1056 spin_lock(&irq_controller_lock
);
1057 desc
->status
&= ~IRQ_INPROGRESS
;
1059 unmask_IO_APIC_irq(irq
);
1060 spin_unlock(&irq_controller_lock
);
1066 * Level and edge triggered IO-APIC interrupts need different handling,
1067 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
1068 * handled with the level-triggered descriptor, but that one has slightly
1069 * more overhead. Level-triggered interrupts cannot be handled with the
1070 * edge-triggered handler, without risking IRQ storms and other ugly
1074 static struct hw_interrupt_type ioapic_edge_irq_type
= {
1077 enable_edge_ioapic_irq
,
1078 disable_edge_ioapic_irq
1081 static struct hw_interrupt_type ioapic_level_irq_type
= {
1083 do_level_ioapic_IRQ
,
1084 enable_level_ioapic_irq
,
1085 disable_level_ioapic_irq
1088 static inline void init_IO_APIC_traps(void)
1092 * NOTE! The local APIC isn't very good at handling
1093 * multiple interrupts at the same interrupt level.
1094 * As the interrupt level is determined by taking the
1095 * vector number and shifting that right by 4, we
1096 * want to spread these out a bit so that they don't
1097 * all fall in the same interrupt level.
1099 * Also, we've got to be careful not to trash gate
1100 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1102 for (i
= 0; i
< NR_IRQS
; i
++) {
1103 if (IO_APIC_IRQ(i
)) {
1104 if (IO_APIC_irq_trigger(i
))
1105 irq_desc
[i
].handler
= &ioapic_level_irq_type
;
1107 irq_desc
[i
].handler
= &ioapic_edge_irq_type
;
1109 * disable it in the 8259A:
1112 disable_8259A_irq(i
);
1118 * This code may look a bit paranoid, but it's supposed to cooperate with
1119 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
1120 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
1121 * fanatically on his truly buggy board.
1123 static inline void check_timer(void)
1127 pin1
= find_timer_pin(mp_INT
);
1128 pin2
= find_timer_pin(mp_ExtINT
);
1130 if (!timer_irq_works()) {
1132 printk("..MP-BIOS bug: 8254 timer not connected to IO-APIC\n");
1133 printk("...trying to set up timer as ExtINT... ");
1136 printk(".. (found pin %d) ...", pin2
);
1137 setup_ExtINT_pin(pin2
);
1141 if (!timer_irq_works()) {
1142 printk(" failed.\n");
1143 printk("...trying to set up timer as BP IRQ...");
1148 clear_IO_APIC_pin(pin1
);
1150 clear_IO_APIC_pin(pin2
);
1154 if (!timer_irq_works()) {
1155 printk(" failed.\n");
1156 panic("IO-APIC + timer doesn't work!");
1159 printk(" works.\n");
1163 void __init
setup_IO_APIC(void)
1168 * Determine the range of IRQs handled by the IO-APIC. The
1169 * following boards can be fully enabled:
1171 * - whitelisted ones
1172 * - those which have no PCI pins connected
1173 * - those for which the user has specified a pirq= parameter
1175 if ( ioapic_whitelisted() ||
1176 (nr_ioapic_registers
== 16) ||
1179 printk("ENABLING IO-APIC IRQs\n");
1180 io_apic_irqs
= ~((1<<2)|(1<<9)|(1<<13));
1182 if (ioapic_blacklisted())
1183 printk(" blacklisted board, DISABLING IO-APIC IRQs\n");
1185 printk(" unlisted board, DISABLING IO-APIC IRQs\n");
1187 printk(" see Documentation/IO-APIC.txt to enable them\n");
1192 * If there are no explicit MP IRQ entries, it's either one of the
1193 * default configuration types or we are broken. In both cases it's
1194 * fine to set up most of the low 16 IO-APIC pins to ISA defaults.
1196 if (!mp_irq_entries
) {
1197 printk("no explicit IRQ entries, using default mptable\n");
1198 construct_default_ISA_mptable();
1201 init_IO_APIC_traps();
1204 * Set up the IO-APIC IRQ routing table by parsing the MP-BIOS
1207 setup_IO_APIC_irqs();