drivers/scsi/blz1230.c

   1 /* blz1230.c: Driver for Blizzard 1230 SCSI IV Controller.
   2  *
   3  * Copyright (C) 1996 Jesper Skov (jskov@cygnus.co.uk)
   4  *
   5  * This driver is based on the CyberStorm driver, hence the occasional
   6  * reference to CyberStorm.
   7  */
   8
   9 /* TODO:
  10  *
  11  * 1) Figure out how to make a cleaner merge with the sparc driver with regard
  12  *    to the caches and the Sparc MMU mapping.
  13  * 2) Make as few routines required outside the generic driver. A lot of the
  14  *    routines in this file used to be inline!
  15  */
  16
  17 #include <linux/kernel.h>
  18 #include <linux/delay.h>
  19 #include <linux/types.h>
  20 #include <linux/string.h>
  21 #include <linux/malloc.h>
  22 #include <linux/blk.h>
  23 #include <linux/proc_fs.h>
  24 #include <linux/stat.h>
  25
  26 #include "scsi.h"
  27 #include "hosts.h"
  28 #include "NCR53C9x.h"
  29 #include "blz1230.h"
  30
  31 #include <linux/zorro.h>
  32 #include <asm/irq.h>
  33 #include <asm/amigaints.h>
  34 #include <asm/amigahw.h>
  35
  36 #include <asm/pgtable.h>
  37
  38 #define MKIV 1
  39
  40 static int  dma_bytes_sent(struct NCR_ESP *esp, int fifo_count);
  41 static int  dma_can_transfer(struct NCR_ESP *esp, Scsi_Cmnd *sp);
  42 static void dma_dump_state(struct NCR_ESP *esp);
  43 static void dma_init_read(struct NCR_ESP *esp, __u32 addr, int length);
  44 static void dma_init_write(struct NCR_ESP *esp, __u32 addr, int length);
  45 static void dma_ints_off(struct NCR_ESP *esp);
  46 static void dma_ints_on(struct NCR_ESP *esp);
  47 static int  dma_irq_p(struct NCR_ESP *esp);
  48 static int  dma_ports_p(struct NCR_ESP *esp);
  49 static void dma_setup(struct NCR_ESP *esp, __u32 addr, int count, int write);
  50
  51 volatile unsigned char cmd_buffer[16];
  52                                 /* This is where all commands are put
  53                                  * before they are transfered to the ESP chip
  54                                  * via PIO.
  55                                  */
  56
  57 /***************************************************************** Detection */
  58 int blz1230_esp_detect(Scsi_Host_Template *tpnt)
  59 {
  60         struct NCR_ESP *esp;
  61         const struct ConfigDev *esp_dev;
  62         unsigned int key;
  63         unsigned long address;
  64         struct ESP_regs *eregs;
  65
  66 #if MKIV
  67         if ((key = zorro_find(ZORRO_PROD_PHASE5_BLIZZARD_1230_IV_1260, 0, 0))){
  68 #else
  69         if ((key = zorro_find(ZORRO_PROD_PHASE5_BLIZZARD_1230_II_FASTLANE_Z3_CYBERSCSI_CYBERSTORM060, 0, 0))){
  70 #endif
  71                 esp_dev = zorro_get_board(key);
  72
  73                 /* Do some magic to figure out if the blizzard is
  74                  * equipped with a SCSI controller
  75                  */
  76                 address = (unsigned long)ZTWO_VADDR(esp_dev->cd_BoardAddr);
  77 #if MKIV
  78                 eregs = (struct ESP_regs *)(address + BLZ1230_ESP_ADDR);
  79 #else
  80                 eregs = (struct ESP_regs *)(address + BLZ1230II_ESP_ADDR);
  81 #endif
  82
  83                 eregs->esp_cfg1 = (ESP_CONFIG1_PENABLE | 7);
  84                 udelay(5);
  85                 if(eregs->esp_cfg1 != (ESP_CONFIG1_PENABLE | 7))
  86                         return 0; /* Bail out if address did not hold data */
  87
  88                 esp = esp_allocate(tpnt, (void *) esp_dev);
  89
  90                 /* Do command transfer with programmed I/O */
  91                 esp->do_pio_cmds = 1;
  92
  93                 /* Required functions */
  94                 esp->dma_bytes_sent = &dma_bytes_sent;
  95                 esp->dma_can_transfer = &dma_can_transfer;
  96                 esp->dma_dump_state = &dma_dump_state;
  97                 esp->dma_init_read = &dma_init_read;
  98                 esp->dma_init_write = &dma_init_write;
  99                 esp->dma_ints_off = &dma_ints_off;
 100                 esp->dma_ints_on = &dma_ints_on;
 101                 esp->dma_irq_p = &dma_irq_p;
 102                 esp->dma_ports_p = &dma_ports_p;
 103                 esp->dma_setup = &dma_setup;
 104
 105                 /* Optional functions */
 106                 esp->dma_barrier = 0;
 107                 esp->dma_drain = 0;
 108                 esp->dma_invalidate = 0;
 109                 esp->dma_irq_entry = 0;
 110                 esp->dma_irq_exit = 0;
 111                 esp->dma_led_on = 0;
 112                 esp->dma_led_off = 0;
 113                 esp->dma_poll = 0;
 114                 esp->dma_reset = 0;
 115
 116                 /* SCSI chip speed */
 117                 esp->cfreq = 40000000;
 118
 119                 /* The DMA registers on the Blizzard are mapped
 120                  * relative to the device (i.e. in the same Zorro
 121                  * I/O block).
 122                  */
 123 #if MKIV
 124                 esp->dregs = (void *)(address + BLZ1230_DMA_ADDR);
 125 #else
 126                 esp->dregs = (void *)(address + BLZ1230II_DMA_ADDR);
 127 #endif
 128
 129                 /* ESP register base */
 130                 esp->eregs = eregs;
 131
 132                 /* Set the command buffer */
 133                 esp->esp_command = (volatile unsigned char*) cmd_buffer;
 134                 esp->esp_command_dvma = virt_to_bus((unsigned long) cmd_buffer);
 135
 136                 esp->irq = IRQ_AMIGA_PORTS;
 137                 request_irq(IRQ_AMIGA_PORTS, esp_intr, 0,
 138                             "Blizzard 1230 SCSI IV", esp_intr);
 139
 140                 /* Figure out our scsi ID on the bus */
 141                 esp->scsi_id = 7;
 142
 143                 /* Check for differential SCSI-bus */
 144                 /* What is this stuff? */
 145                 esp->diff = 0;
 146
 147                 esp_initialize(esp);
 148
 149                 zorro_config_board(key, 0);
 150
 151                 printk("\nESP: Total of %d ESP hosts found, %d actually in use.\n", nesps,esps_in_use);
 152                 esps_running = esps_in_use;
 153                 return esps_in_use;
 154         }
 155         return 0;
 156 }
 157
 158 /************************************************************* DMA Functions */
 159 static int dma_bytes_sent(struct NCR_ESP *esp, int fifo_count)
 160 {
 161         /* Since the Blizzard DMA is fully dedicated to the ESP chip,
 162          * the number of bytes sent (to the ESP chip) equals the number
 163          * of bytes in the FIFO - there is no buffering in the DMA controller.
 164          * XXXX Do I read this right? It is from host to ESP, right?
 165          */
 166         return fifo_count;
 167 }
 168
 169 static int dma_can_transfer(struct NCR_ESP *esp, Scsi_Cmnd *sp)
 170 {
 171         /* I don't think there's any limit on the Blizzard DMA. So we use what
 172          * the ESP chip can handle (24 bit).
 173          */
 174         unsigned long sz = sp->SCp.this_residual;
 175         if(sz > 0x1000000)
 176                 sz = 0x1000000;
 177         return sz;
 178 }
 179
 180 static void dma_dump_state(struct NCR_ESP *esp)
 181 {
 182         ESPLOG(("intreq:<%04x>, intena:<%04x>\n",
 183                 custom.intreqr, custom.intenar));
 184 }
 185
 186 void dma_init_read(struct NCR_ESP *esp, __u32 addr, int length)
 187 {
 188 #if MKIV
 189         struct blz1230_dma_registers *dregs =
 190                 (struct blz1230_dma_registers *) (esp->dregs);
 191 #else
 192         struct blz1230II_dma_registers *dregs =
 193                 (struct blz1230II_dma_registers *) (esp->dregs);
 194 #endif
 195
 196         cache_clear(addr, length);
 197
 198         addr >>= 1;
 199         addr &= ~(BLZ1230_DMA_WRITE);
 200
 201         /* First set latch */
 202         dregs->dma_latch = (addr >> 24) & 0xff;
 203
 204         /* Then pump the address to the DMA address register */
 205 #if MKIV
 206         dregs->dma_addr = (addr >> 24) & 0xff;
 207 #endif
 208         dregs->dma_addr = (addr >> 16) & 0xff;
 209         dregs->dma_addr = (addr >>  8) & 0xff;
 210         dregs->dma_addr = (addr      ) & 0xff;
 211 }
 212
 213 void dma_init_write(struct NCR_ESP *esp, __u32 addr, int length)
 214 {
 215 #if MKIV
 216         struct blz1230_dma_registers *dregs =
 217                 (struct blz1230_dma_registers *) (esp->dregs);
 218 #else
 219         struct blz1230II_dma_registers *dregs =
 220                 (struct blz1230II_dma_registers *) (esp->dregs);
 221 #endif
 222
 223         cache_push(addr, length);
 224
 225         addr >>= 1;
 226         addr |= BLZ1230_DMA_WRITE;
 227
 228         /* First set latch */
 229         dregs->dma_latch = (addr >> 24) & 0xff;
 230
 231         /* Then pump the address to the DMA address register */
 232 #if MKIV
 233         dregs->dma_addr = (addr >> 24) & 0xff;
 234 #endif
 235         dregs->dma_addr = (addr >> 16) & 0xff;
 236         dregs->dma_addr = (addr >>  8) & 0xff;
 237         dregs->dma_addr = (addr      ) & 0xff;
 238 }
 239
 240 static void dma_ints_off(struct NCR_ESP *esp)
 241 {
 242         disable_irq(esp->irq);
 243 }
 244
 245 static void dma_ints_on(struct NCR_ESP *esp)
 246 {
 247         enable_irq(esp->irq);
 248 }
 249
 250 static int dma_irq_p(struct NCR_ESP *esp)
 251 {
 252         return (esp->eregs->esp_status & ESP_STAT_INTR);
 253 }
 254
 255 static int dma_ports_p(struct NCR_ESP *esp)
 256 {
 257         return ((custom.intenar) & IF_PORTS);
 258 }
 259
 260 static void dma_setup(struct NCR_ESP *esp, __u32 addr, int count, int write)
 261 {
 262         /* On the Sparc, DMA_ST_WRITE means "move data from device to memory"
 263          * so when (write) is true, it actually means READ!
 264          */
 265         if(write){
 266                 dma_init_read(esp, addr, count);
 267         } else {
 268                 dma_init_write(esp, addr, count);
 269         }
 270 }