1 /* $Id: blockops.S,v 1.16 1998/10/20 03:09:04 jj Exp $
2 * blockops.S: UltraSparc block zero optimized routines.
4 * Copyright (C) 1996,1998 David S. Miller (davem@caip.rutgers.edu)
5 * Copyright (C) 1997 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
9 #include <asm/visasm.h>
11 #include <asm/pgtable.h>
12 #include <asm/asm_offsets.h>
14 #define TOUCH(reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7) \
15 fmovd %reg0, %f48; fmovd %reg1, %f50; \
16 fmovd %reg2, %f52; fmovd %reg3, %f54; \
17 fmovd %reg4, %f56; fmovd %reg5, %f58; \
18 fmovd %reg6, %f60; fmovd %reg7, %f62;
20 #define TLBTEMP_BASE (8 * 1024 * 1024)
21 #define DCACHE_SIZE (PAGE_SIZE * 2)
22 #define TLBTEMP_ENT1 (61 << 3)
23 #define TLBTEMP_ENT2 (62 << 3)
24 #define TLBTEMP_ENTSZ (1 << 3)
29 .type copy_page,@function
30 copy_page: /* %o0=dest, %o1=src */
32 ldx [%g6 + AOFF_task_mm], %o2
34 sethi %uhi(_PAGE_VALID), %g3
37 ldx [%o2 + AOFF_mm_segments], %o0
38 or %g3, (_PAGE_CP | _PAGE_CV | _PAGE_P | _PAGE_L | _PAGE_W), %g3
41 mov TLB_TAG_ACCESS, %o2
42 sethi %hi(TLBTEMP_BASE), %o3
43 sethi %hi(DCACHE_SIZE), %o1
46 sethi %hi(TLBTEMP_ENT1), %o3
48 wrpr %g3, PSTATE_IE, %pstate
49 ldxa [%o3] ASI_DTLB_TAG_READ, %o4
50 ldxa [%o3] ASI_DTLB_DATA_ACCESS, %o5
51 stxa %o0, [%o2] ASI_DMMU
52 stxa %g1, [%o3] ASI_DTLB_DATA_ACCESS
54 add %o3, (TLBTEMP_ENTSZ), %o3
55 ldxa [%o3] ASI_DTLB_TAG_READ, %g5
56 ldxa [%o3] ASI_DTLB_DATA_ACCESS, %g7
57 stxa %o1, [%o2] ASI_DMMU
58 stxa %g2, [%o3] ASI_DTLB_DATA_ACCESS
61 membar #LoadStore | #StoreStore | #StoreLoad
62 ldda [%o1] ASI_BLK_P, %f0
64 ldda [%o1] ASI_BLK_P, %f16
67 1: TOUCH(f0, f2, f4, f6, f8, f10, f12, f14)
68 ldda [%o1] ASI_BLK_P, %f32
71 stda %f48, [%o0] ASI_BLK_P
73 TOUCH(f16, f18, f20, f22, f24, f26, f28, f30)
74 ldda [%o1] ASI_BLK_P, %f0
77 stda %f48, [%o0] ASI_BLK_P
79 TOUCH(f32, f34, f36, f38, f40, f42, f44, f46)
80 ldda [%o1] ASI_BLK_P, %f16
83 stda %f48, [%o0] ASI_BLK_P
88 stda %f0, [%o0] ASI_BLK_P
90 stda %f16, [%o0] ASI_BLK_P
94 mov TLB_TAG_ACCESS, %o2
95 stxa %g5, [%o2] ASI_DMMU
96 stxa %g7, [%o3] ASI_DTLB_DATA_ACCESS
98 sub %o3, (TLBTEMP_ENTSZ), %o3
99 stxa %o4, [%o2] ASI_DMMU
100 stxa %o5, [%o3] ASI_DTLB_DATA_ACCESS
103 wrpr %g3, 0x0, %pstate
107 .type clear_page,@function
108 clear_page: /* %o0=dest */
110 ldx [%g6 + AOFF_task_mm], %o2
112 sethi %uhi(_PAGE_VALID), %g3
114 or %g3, (_PAGE_CP | _PAGE_CV | _PAGE_P | _PAGE_L | _PAGE_W), %g3
115 ldx [%o2 + AOFF_mm_segments], %o0
117 mov TLB_TAG_ACCESS, %o2
118 sethi %hi(TLBTEMP_BASE), %o3
120 sethi %hi(TLBTEMP_ENT2), %o3
122 wrpr %g3, PSTATE_IE, %pstate
123 ldxa [%o3] ASI_DTLB_TAG_READ, %g5
124 ldxa [%o3] ASI_DTLB_DATA_ACCESS, %g7
125 stxa %o0, [%o2] ASI_DMMU
126 stxa %g1, [%o3] ASI_DTLB_DATA_ACCESS
129 fzero %f0 ! FPA Group
131 fzero %f2 ! FPA Group
132 faddd %f0, %f2, %f4 ! FPA Group
133 fmuld %f0, %f2, %f6 ! FPM
134 faddd %f0, %f2, %f8 ! FPA Group
135 fmuld %f0, %f2, %f10 ! FPM
137 faddd %f0, %f2, %f12 ! FPA Group
138 fmuld %f0, %f2, %f14 ! FPM
139 wr %g0, ASI_BLK_P, %asi ! LSU Group
140 membar #StoreLoad | #StoreStore | #LoadStore ! LSU Group
141 1: stda %f0, [%o0 + 0x00] %asi ! Store Group
142 stda %f0, [%o0 + 0x40] %asi ! Store Group
143 stda %f0, [%o0 + 0x80] %asi ! Store Group
144 stda %f0, [%o0 + 0xc0] %asi ! Store Group
146 subcc %o1, 1, %o1 ! IEU1
147 bne,pt %icc, 1b ! CTI
148 add %o0, 0x100, %o0 ! IEU0 Group
149 membar #Sync ! LSU Group
152 stxa %g5, [%o2] ASI_DMMU
153 stxa %g7, [%o3] ASI_DTLB_DATA_ACCESS
156 wrpr %g3, 0x0, %pstate