| blob | 9be111134bd4be1685ed0c97fd8347ffd970f7f5 |
1 /* $Id: VISmemset.S,v 1.8 1998/06/12 14:53:59 jj Exp $
2 * VISmemset.S: High speed memset operations utilizing the UltraSparc
3 * Visual Instruction Set.
4 *
5 * Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu)
6 * Copyright (C) 1996, 1997 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
7 */
9 #include "VIS.h"
11 #ifdef REGS_64BIT
12 #define SET_BLOCKS(base, offset, source) \
13 stx source, [base - offset - 0x18]; \
14 stx source, [base - offset - 0x10]; \
15 stx source, [base - offset - 0x08]; \
16 stx source, [base - offset - 0x00];
17 #else
18 #define SET_BLOCKS(base, offset, source) \
19 stw source, [base - offset - 0x18]; \
20 stw source, [base - offset - 0x14]; \
21 stw source, [base - offset - 0x10]; \
22 stw source, [base - offset - 0x0c]; \
23 stw source, [base - offset - 0x08]; \
24 stw source, [base - offset - 0x04]; \
25 stw source, [base - offset - 0x00]; \
26 stw source, [base - offset + 0x04];
27 #endif
29 #ifndef __KERNEL__
30 /* So that the brz,a,pt in memset doesn't have to get through PLT, here we go... */
31 #include "VISbzero.S"
32 #endif
34 #ifdef __KERNEL__
36 #include <asm/visasm.h>
38 #define RETL clr %o0
39 #else
40 #define RETL mov %g3, %o0
41 #endif
43 /* Well, memset is a lot easier to get right than bcopy... */
44 .text
45 .align 32
46 #ifdef __KERNEL__
47 .globl __memset
48 __memset:
49 #endif
50 .globl memset
51 memset:
52 #ifndef __KERNEL__
53 brz,a,pt %o1, bzero_private
54 mov %o2, %o1
55 #ifndef REGS_64BIT
56 srl %o2, 0, %o2
57 #endif
58 mov %o0, %g3
59 #endif
60 cmp %o2, 7
61 bleu,pn %xcc, 17f
62 andcc %o0, 3, %g5
63 be,pt %xcc, 4f
64 and %o1, 0xff, %o1
65 cmp %g5, 3
66 be,pn %xcc, 2f
67 stb %o1, [%o0 + 0x00]
68 cmp %g5, 2
69 be,pt %xcc, 2f
70 stb %o1, [%o0 + 0x01]
71 stb %o1, [%o0 + 0x02]
72 2: sub %g5, 4, %g5
73 sub %o0, %g5, %o0
74 add %o2, %g5, %o2
75 4: sllx %o1, 8, %g1
76 andcc %o0, 4, %g0
77 or %o1, %g1, %o1
78 sllx %o1, 16, %g1
79 or %o1, %g1, %o1
80 be,pt %xcc, 2f
81 #ifdef REGS_64BIT
82 sllx %o1, 32, %g1
83 #else
84 cmp %o2, 128
85 #endif
86 stw %o1, [%o0]
87 sub %o2, 4, %o2
88 add %o0, 4, %o0
89 2:
90 #ifdef REGS_64BIT
91 cmp %o2, 128
92 or %o1, %g1, %o1
93 #endif
94 blu,pn %xcc, 9f
95 andcc %o0, 0x38, %g5
96 be,pn %icc, 6f
97 mov 64, %o5
98 andcc %o0, 8, %g0
99 be,pn %icc, 1f
100 sub %o5, %g5, %o5
101 #ifdef REGS_64BIT
102 stx %o1, [%o0]
103 #else
104 stw %o1, [%o0]
105 stw %o1, [%o0 + 4]
106 #endif
107 add %o0, 8, %o0
108 1: andcc %o5, 16, %g0
109 be,pn %icc, 1f
110 sub %o2, %o5, %o2
111 #ifdef REGS_64BIT
112 stx %o1, [%o0]
113 stx %o1, [%o0 + 8]
114 #else
115 stw %o1, [%o0]
116 stw %o1, [%o0 + 4]
117 stw %o1, [%o0 + 8]
118 stw %o1, [%o0 + 12]
119 #endif
120 add %o0, 16, %o0
121 1: andcc %o5, 32, %g0
122 be,pn %icc, 7f
123 andncc %o2, 0x3f, %o3
124 #ifdef REGS_64BIT
125 stx %o1, [%o0]
126 stx %o1, [%o0 + 8]
127 stx %o1, [%o0 + 16]
128 stx %o1, [%o0 + 24]
129 #else
130 stw %o1, [%o0]
131 stw %o1, [%o0 + 4]
132 stw %o1, [%o0 + 8]
133 stw %o1, [%o0 + 12]
134 stw %o1, [%o0 + 16]
135 stw %o1, [%o0 + 20]
136 stw %o1, [%o0 + 24]
137 stw %o1, [%o0 + 28]
138 #endif
139 add %o0, 32, %o0
140 7: be,pn %xcc, 9f
141 nop
142 #ifdef __KERNEL__
143 VISEntryHalf
144 #endif
145 ldd [%o0 - 8], %f0
146 18: wr %g0, ASI_BLK_P, %asi
147 membar #StoreStore | #LoadStore
148 andcc %o3, 0xc0, %g5
149 and %o2, 0x3f, %o2
150 fmovd %f0, %f2
151 fmovd %f0, %f4
152 andn %o3, 0xff, %o3
153 fmovd %f0, %f6
154 cmp %g5, 64
155 fmovd %f0, %f8
156 fmovd %f0, %f10
157 fmovd %f0, %f12
158 brz,pn %g5, 10f
159 fmovd %f0, %f14
160 be,pn %icc, 2f
161 stda %f0, [%o0 + 0x00] %asi
162 cmp %g5, 128
163 be,pn %icc, 2f
164 stda %f0, [%o0 + 0x40] %asi
165 stda %f0, [%o0 + 0x80] %asi
166 2: brz,pn %o3, 12f
167 add %o0, %g5, %o0
168 10: stda %f0, [%o0 + 0x00] %asi
169 stda %f0, [%o0 + 0x40] %asi
170 stda %f0, [%o0 + 0x80] %asi
171 stda %f0, [%o0 + 0xc0] %asi
172 11: subcc %o3, 256, %o3
173 bne,pt %xcc, 10b
174 add %o0, 256, %o0
175 12:
176 #ifdef __KERNEL__
177 VISExitHalf
178 #else
179 #ifndef REGS_64BIT
180 wr %g0, FPRS_FEF, %fprs
181 #endif
182 #endif
183 membar #StoreLoad | #StoreStore
184 9: andcc %o2, 0x78, %g5
185 be,pn %xcc, 13f
186 andcc %o2, 7, %o2
187 #ifdef __KERNEL__
188 14: srl %g5, 1, %o3
189 sethi %hi(13f), %o4
190 sub %o4, %o3, %o4
191 jmpl %o4 + %lo(13f), %g0
192 add %o0, %g5, %o0
193 #else
194 14: rd %pc, %o4
195 #ifdef REGS_64BIT
196 srl %g5, 1, %o3
197 sub %o4, %o3, %o4
198 #else
199 sub %o4, %g5, %o4
200 #endif
201 jmpl %o4 + (13f - 14b), %g0
202 add %o0, %g5, %o0
203 #endif
204 12: SET_BLOCKS(%o0, 0x68, %o1)
205 SET_BLOCKS(%o0, 0x48, %o1)
206 SET_BLOCKS(%o0, 0x28, %o1)
207 SET_BLOCKS(%o0, 0x08, %o1)
208 13: be,pn %xcc, 8f
209 andcc %o2, 4, %g0
210 be,pn %xcc, 1f
211 andcc %o2, 2, %g0
212 stw %o1, [%o0]
213 add %o0, 4, %o0
214 1: be,pn %xcc, 1f
215 andcc %o2, 1, %g0
216 sth %o1, [%o0]
217 add %o0, 2, %o0
218 1: bne,a,pn %xcc, 8f
219 stb %o1, [%o0]
220 8: retl
221 RETL
222 17: brz,pn %o2, 0f
223 8: add %o0, 1, %o0
224 subcc %o2, 1, %o2
225 bne,pt %xcc, 8b
226 stb %o1, [%o0 - 1]
227 0: retl
228 RETL
229 6:
230 #ifdef REGS_64BIT
231 stx %o1, [%o0]
232 #else
233 stw %o1, [%o0]
234 stw %o1, [%o0 + 4]
235 #endif
236 andncc %o2, 0x3f, %o3
237 be,pn %xcc, 9b
238 nop
239 #ifdef __KERNEL__
240 VISEntryHalf
241 #endif
242 ba,pt %xcc, 18b
243 ldd [%o0], %f0