2 * linux/arch/i386/kernel/visws_apic.c
4 * Copyright (C) 1999 Bent Hagemark, Ingo Molnar
6 * SGI Visual Workstation interrupt controller
8 * The Cobalt system ASIC in the Visual Workstation contains a "Cobalt" APIC
9 * which serves as the main interrupt controller in the system. Non-legacy
10 * hardware in the system uses this controller directly. Legacy devices
11 * are connected to the PIIX4 which in turn has its 8259(s) connected to
12 * a of the Cobalt APIC entry.
15 #include <linux/ptrace.h>
16 #include <linux/errno.h>
17 #include <linux/kernel_stat.h>
18 #include <linux/signal.h>
19 #include <linux/sched.h>
20 #include <linux/ioport.h>
21 #include <linux/interrupt.h>
22 #include <linux/timex.h>
23 #include <linux/malloc.h>
24 #include <linux/random.h>
25 #include <linux/smp.h>
26 #include <linux/tasks.h>
27 #include <linux/smp_lock.h>
28 #include <linux/init.h>
30 #include <asm/system.h>
33 #include <asm/bitops.h>
35 #include <asm/pgtable.h>
36 #include <asm/delay.h>
39 #include <asm/cobalt.h>
44 * This is the PIIX4-based 8259 that is wired up indirectly to Cobalt
45 * -- not the manner expected by the normal 8259 code in irq.c.
47 * there is a 'master' physical interrupt source that gets sent to
48 * the CPU. But in the chipset there are various 'virtual' interrupts
49 * waiting to be handled. We represent this to Linux through a 'master'
50 * interrupt controller type, and through a special virtual interrupt-
51 * controller. Device drivers only see the virtual interrupt sources.
54 #define CO_IRQ_BASE 0x20 /* This is the 0x20 in init_IRQ()! */
56 static void startup_piix4_master_irq(unsigned int irq
);
57 static void shutdown_piix4_master_irq(unsigned int irq
);
58 static void do_piix4_master_IRQ(unsigned int irq
, struct pt_regs
* regs
);
59 #define enable_piix4_master_irq startup_piix4_master_irq
60 #define disable_piix4_master_irq shutdown_piix4_master_irq
62 static struct hw_interrupt_type piix4_master_irq_type
= {
64 startup_piix4_master_irq
,
65 shutdown_piix4_master_irq
,
67 enable_piix4_master_irq
,
68 disable_piix4_master_irq
71 static void enable_piix4_virtual_irq(unsigned int irq
);
72 static void disable_piix4_virtual_irq(unsigned int irq
);
73 #define startup_piix4_virtual_irq enable_piix4_virtual_irq
74 #define shutdown_piix4_virtual_irq disable_piix4_virtual_irq
76 static struct hw_interrupt_type piix4_virtual_irq_type
= {
78 startup_piix4_virtual_irq
,
79 shutdown_piix4_virtual_irq
,
80 0, /* no handler, it's never called physically */
81 enable_piix4_virtual_irq
,
82 disable_piix4_virtual_irq
86 * This is the SGI Cobalt (IO-)APIC:
89 static void do_cobalt_IRQ(unsigned int irq
, struct pt_regs
* regs
);
90 static void enable_cobalt_irq(unsigned int irq
);
91 static void disable_cobalt_irq(unsigned int irq
);
92 static void startup_cobalt_irq(unsigned int irq
);
93 #define shutdown_cobalt_irq disable_cobalt_irq
95 static struct hw_interrupt_type cobalt_irq_type
= {
106 * Not an initfunc, needed by the reboot code
108 void init_pic_mode(void)
114 * Cobalt (IO)-APIC functions to handle PCI devices.
117 static void disable_cobalt_irq(unsigned int irq
)
119 /* XXX undo the APIC entry here? */
122 * definitely, we do not want to have IRQ storms from
123 * unused devices --mingo
127 static void enable_cobalt_irq(unsigned int irq
)
132 * Set the given Cobalt APIC Redirection Table entry to point
133 * to the given IDT vector/index.
135 static void co_apic_set(int entry
, int idtvec
)
137 co_apic_write(CO_APIC_LO(entry
), CO_APIC_LEVEL
| (CO_IRQ_BASE
+idtvec
));
138 co_apic_write(CO_APIC_HI(entry
), 0);
140 printk("Cobalt APIC Entry %d IDT Vector %d\n", entry
, idtvec
);
144 * "irq" really just serves to identify the device. Here is where we
145 * map this to the Cobalt APIC entry where it's physically wired.
146 * This is called via request_irq -> setup_x86_irq -> irq_desc->startup()
148 static void startup_cobalt_irq(unsigned int irq
)
151 * These "irq"'s are wired to the same Cobalt APIC entries
152 * for all (known) motherboard types/revs
155 case CO_IRQ_TIMER
: co_apic_set(CO_APIC_CPU
, CO_IRQ_TIMER
);
158 case CO_IRQ_ENET
: co_apic_set(CO_APIC_ENET
, CO_IRQ_ENET
);
161 case CO_IRQ_SERIAL
: return; /* XXX move to piix4-8259 "virtual" */
163 case CO_IRQ_8259
: co_apic_set(CO_APIC_8259
, CO_IRQ_8259
);
167 switch (visws_board_type
) {
169 switch (visws_board_rev
) {
171 co_apic_set(CO_APIC_0_5_IDE0
, CO_IRQ_IDE
);
172 co_apic_set(CO_APIC_0_5_IDE1
, CO_IRQ_IDE
);
175 co_apic_set(CO_APIC_0_6_IDE0
, CO_IRQ_IDE
);
176 co_apic_set(CO_APIC_0_6_IDE1
, CO_IRQ_IDE
);
180 switch (visws_board_rev
) {
182 co_apic_set(CO_APIC_1_2_IDE0
, CO_IRQ_IDE
);
193 * This is the handle() op in do_IRQ()
195 static void do_cobalt_IRQ(unsigned int irq
, struct pt_regs
* regs
)
197 struct irqaction
* action
;
198 irq_desc_t
*desc
= irq_desc
+ irq
;
200 spin_lock(&irq_controller_lock
);
204 status
= desc
->status
& ~(IRQ_REPLAY
| IRQ_WAITING
);
206 if (!(status
& (IRQ_DISABLED
| IRQ_INPROGRESS
))) {
207 action
= desc
->action
;
208 status
|= IRQ_INPROGRESS
;
210 desc
->status
= status
;
212 spin_unlock(&irq_controller_lock
);
214 /* Exit early if we had no action or it was disabled */
218 handle_IRQ_event(irq
, regs
, action
);
220 (void)co_cpu_read(CO_CPU_REV
); /* Sync driver ack to its h/w */
221 apic_write(APIC_EOI
, APIC_EIO_ACK
); /* Send EOI to Cobalt APIC */
223 spin_lock(&irq_controller_lock
);
225 unsigned int status
= desc
->status
& ~IRQ_INPROGRESS
;
226 desc
->status
= status
;
227 if (!(status
& IRQ_DISABLED
))
228 enable_cobalt_irq(irq
);
230 spin_unlock(&irq_controller_lock
);
234 * PIIX4-8259 master/virtual functions to handle:
241 * None of these get Cobalt APIC entries, neither do they have IDT
242 * entries. These interrupts are purely virtual and distributed from
243 * the 'master' interrupt source: CO_IRQ_8259.
245 * When the 8259 interrupts its handler figures out which of these
246 * devices is interrupting and dispatches to it's handler.
248 * CAREFUL: devices see the 'virtual' interrupt only. Thus disable/
249 * enable_irq gets the right irq. This 'master' irq is never directly
250 * manipulated by any driver.
253 static void startup_piix4_master_irq(unsigned int irq
)
271 /* OCW1 - disable all interrupts in both 8259's */
275 startup_cobalt_irq(irq
);
278 static void shutdown_piix4_master_irq(unsigned int irq
)
281 * [we skip the 8259 magic here, not strictly necessary]
284 shutdown_cobalt_irq(irq
);
287 static void do_piix4_master_IRQ(unsigned int irq
, struct pt_regs
* regs
)
291 /* Find out what's interrupting in the PIIX4 8259 */
293 spin_lock(&irq_controller_lock
);
294 outb(0x0c, 0x20); /* OCW3 Poll command */
297 if (!(realirq
& 0x80)) {
299 * Bit 7 == 0 means invalid/spurious
306 * mask and ack the 8259
309 if ((mask
>> realirq
) & 0x01)
311 * This IRQ is masked... ignore
315 outb(mask
| (1<<realirq
), 0x21);
317 * OCW2 - non-specific EOI
321 spin_unlock(&irq_controller_lock
);
324 * handle this 'virtual interrupt' as a Cobalt one now.
326 kstat
.irqs
[smp_processor_id()][irq
]++;
327 do_cobalt_IRQ(realirq
, regs
);
329 spin_lock(&irq_controller_lock
);
331 irq_desc_t
*desc
= irq_desc
+ realirq
;
333 if (!(desc
->status
& IRQ_DISABLED
))
334 enable_piix4_virtual_irq(realirq
);
336 spin_unlock(&irq_controller_lock
);
340 spin_unlock(&irq_controller_lock
);
344 static void enable_piix4_virtual_irq(unsigned int irq
)
347 * assumes this irq is one of the legacy devices
350 unsigned int mask
= inb(0x21);
353 enable_cobalt_irq(irq
);
357 * assumes this irq is one of the legacy devices
359 static void disable_piix4_virtual_irq(unsigned int irq
)
363 disable_cobalt_irq(irq
);
370 static struct irqaction master_action
=
371 { no_action
, 0, 0, "PIIX4-8259", NULL
, NULL
};
373 void init_VISWS_APIC_irqs(void)
377 for (i
= 0; i
< 16; i
++) {
378 irq_desc
[i
].status
= IRQ_DISABLED
;
379 irq_desc
[i
].action
= 0;
380 irq_desc
[i
].depth
= 0;
383 * Cobalt IRQs are mapped to standard ISA
388 * Only CO_IRQ_8259 will be raised
392 irq_desc
[i
].handler
= &piix4_master_irq_type
;
396 irq_desc
[i
].handler
= &piix4_virtual_irq_type
;
399 irq_desc
[i
].handler
= &cobalt_irq_type
;
405 * The master interrupt is always present:
407 setup_x86_irq(CO_IRQ_8259
, &master_action
);