drivers/pcmcia/yenta.c

   1 /*
   2  * Regular lowlevel cardbus driver ("yenta")
   3  *
   4  * (C) Copyright 1999, 2000 Linus Torvalds
   5  */
   6 #include <linux/init.h>
   7 #include <linux/pci.h>
   8 #include <linux/sched.h>
   9 #include <linux/interrupt.h>
  10 #include <linux/delay.h>
  11 #include <linux/module.h>
  12
  13 #include <pcmcia/ss.h>
  14
  15 #include <asm/io.h>
  16
  17 #include "yenta.h"
  18 #include "i82365.h"
  19
  20 #if 0
  21 #define DEBUG(x,args...)        printk(__FUNCTION__ ": " x,##args)
  22 #else
  23 #define DEBUG(x,args...)
  24 #endif
  25
  26 /* Don't ask.. */
  27 #define to_cycles(ns)   ((ns)/120)
  28 #define to_ns(cycles)   ((cycles)*120)
  29
  30 /*
  31  * Generate easy-to-use ways of reading a cardbus sockets
  32  * regular memory space ("cb_xxx"), configuration space
  33  * ("config_xxx") and compatibility space ("exca_xxxx")
  34  */
  35 static inline u32 cb_readl(pci_socket_t *socket, unsigned reg)
  36 {
  37         u32 val = readl(socket->base + reg);
  38         DEBUG("%p %04x %08x\n", socket, reg, val);
  39         return val;
  40 }
  41
  42 static inline void cb_writel(pci_socket_t *socket, unsigned reg, u32 val)
  43 {
  44         DEBUG("%p %04x %08x\n", socket, reg, val);
  45         writel(val, socket->base + reg);
  46 }
  47
  48 static inline u8 config_readb(pci_socket_t *socket, unsigned offset)
  49 {
  50         u8 val;
  51         pci_read_config_byte(socket->dev, offset, &val);
  52         DEBUG("%p %04x %02x\n", socket, offset, val);
  53         return val;
  54 }
  55
  56 static inline u16 config_readw(pci_socket_t *socket, unsigned offset)
  57 {
  58         u16 val;
  59         pci_read_config_word(socket->dev, offset, &val);
  60         DEBUG("%p %04x %04x\n", socket, offset, val);
  61         return val;
  62 }
  63
  64 static inline u32 config_readl(pci_socket_t *socket, unsigned offset)
  65 {
  66         u32 val;
  67         pci_read_config_dword(socket->dev, offset, &val);
  68         DEBUG("%p %04x %08x\n", socket, offset, val);
  69         return val;
  70 }
  71
  72 static inline void config_writeb(pci_socket_t *socket, unsigned offset, u8 val)
  73 {
  74         DEBUG("%p %04x %02x\n", socket, offset, val);
  75         pci_write_config_byte(socket->dev, offset, val);
  76 }
  77
  78 static inline void config_writew(pci_socket_t *socket, unsigned offset, u16 val)
  79 {
  80         DEBUG("%p %04x %04x\n", socket, offset, val);
  81         pci_write_config_word(socket->dev, offset, val);
  82 }
  83
  84 static inline void config_writel(pci_socket_t *socket, unsigned offset, u32 val)
  85 {
  86         DEBUG("%p %04x %08x\n", socket, offset, val);
  87         pci_write_config_dword(socket->dev, offset, val);
  88 }
  89
  90 static inline u8 exca_readb(pci_socket_t *socket, unsigned reg)
  91 {
  92         u8 val = readb(socket->base + 0x800 + reg);
  93         DEBUG("%p %04x %02x\n", socket, reg, val);
  94         return val;
  95 }
  96
  97 static inline u8 exca_readw(pci_socket_t *socket, unsigned reg)
  98 {
  99         u16 val;
 100         val = readb(socket->base + 0x800 + reg);
 101         val |= readb(socket->base + 0x800 + reg + 1) << 8;
 102         DEBUG("%p %04x %04x\n", socket, reg, val);
 103         return val;
 104 }
 105
 106 static inline void exca_writeb(pci_socket_t *socket, unsigned reg, u8 val)
 107 {
 108         DEBUG("%p %04x %02x\n", socket, reg, val);
 109         writeb(val, socket->base + 0x800 + reg);
 110 }
 111
 112 static void exca_writew(pci_socket_t *socket, unsigned reg, u16 val)
 113 {
 114         DEBUG("%p %04x %04x\n", socket, reg, val);
 115         writeb(val, socket->base + 0x800 + reg);
 116         writeb(val >> 8, socket->base + 0x800 + reg + 1);
 117 }
 118
 119 /*
 120  * Ugh, mixed-mode cardbus and 16-bit pccard state: things depend
 121  * on what kind of card is inserted..
 122  */
 123 static int yenta_get_status(pci_socket_t *socket, unsigned int *value)
 124 {
 125         unsigned int val;
 126         u32 state = cb_readl(socket, CB_SOCKET_STATE);
 127
 128         val  = (state & CB_3VCARD) ? SS_3VCARD : 0;
 129         val |= (state & CB_XVCARD) ? SS_XVCARD : 0;
 130
 131         if (state & CB_CBCARD) {
 132                 val |= SS_CARDBUS;
 133                 val |= (state & CB_CARDSTS) ? SS_STSCHG : 0;
 134                 val |= (state & (CB_CDETECT1 | CB_CDETECT2)) ? 0 : SS_DETECT;
 135                 val |= (state & CB_PWRCYCLE) ? SS_POWERON | SS_READY : 0;
 136         } else {
 137                 u8 status = exca_readb(socket, I365_STATUS);
 138                 val |= ((status & I365_CS_DETECT) == I365_CS_DETECT) ? SS_DETECT : 0;
 139                 if (exca_readb(socket, I365_INTCTL) & I365_PC_IOCARD) {
 140                         val |= (status & I365_CS_STSCHG) ? 0 : SS_STSCHG;
 141                 } else {
 142                         val |= (status & I365_CS_BVD1) ? 0 : SS_BATDEAD;
 143                         val |= (status & I365_CS_BVD2) ? 0 : SS_BATWARN;
 144                 }
 145                 val |= (status & I365_CS_WRPROT) ? SS_WRPROT : 0;
 146                 val |= (status & I365_CS_READY) ? SS_READY : 0;
 147                 val |= (status & I365_CS_POWERON) ? SS_POWERON : 0;
 148         }
 149
 150         *value = val;
 151         return 0;
 152 }
 153
 154 static int yenta_Vcc_power(u32 control)
 155 {
 156         switch (control & CB_SC_VCC_MASK) {
 157         case CB_SC_VCC_5V: return 50;
 158         case CB_SC_VCC_3V: return 33;
 159         default: return 0;
 160         }
 161 }
 162
 163 static int yenta_Vpp_power(u32 control)
 164 {
 165         switch (control & CB_SC_VPP_MASK) {
 166         case CB_SC_VPP_12V: return 120;
 167         case CB_SC_VPP_5V: return 50;
 168         case CB_SC_VPP_3V: return 33;
 169         default: return 0;
 170         }
 171 }
 172
 173 static int yenta_get_socket(pci_socket_t *socket, socket_state_t *state)
 174 {
 175         u8 reg;
 176         u32 control;
 177
 178         control = cb_readl(socket, CB_SOCKET_CONTROL);
 179
 180         state->Vcc = yenta_Vcc_power(control);
 181         state->Vpp = yenta_Vpp_power(control);
 182         state->io_irq = socket->io_irq;
 183
 184         if (cb_readl(socket, CB_SOCKET_STATE) & CB_CBCARD) {
 185                 u16 bridge = config_readw(socket, CB_BRIDGE_CONTROL);
 186                 if (bridge & CB_BRIDGE_CRST)
 187                         state->flags |= SS_RESET;
 188                 return 0;
 189         }
 190
 191         /* 16-bit card state.. */
 192         reg = exca_readb(socket, I365_POWER);
 193         state->flags = (reg & I365_PWR_AUTO) ? SS_PWR_AUTO : 0;
 194         state->flags |= (reg & I365_PWR_OUT) ? SS_OUTPUT_ENA : 0;
 195
 196         reg = exca_readb(socket, I365_INTCTL);
 197         state->flags |= (reg & I365_PC_RESET) ? 0 : SS_RESET;
 198         state->flags |= (reg & I365_PC_IOCARD) ? SS_IOCARD : 0;
 199
 200         reg = exca_readb(socket, I365_CSCINT);
 201         state->csc_mask = (reg & I365_CSC_DETECT) ? SS_DETECT : 0;
 202         if (state->flags & SS_IOCARD) {
 203                 state->csc_mask |= (reg & I365_CSC_STSCHG) ? SS_STSCHG : 0;
 204         } else {
 205                 state->csc_mask |= (reg & I365_CSC_BVD1) ? SS_BATDEAD : 0;
 206                 state->csc_mask |= (reg & I365_CSC_BVD2) ? SS_BATWARN : 0;
 207                 state->csc_mask |= (reg & I365_CSC_READY) ? SS_READY : 0;
 208         }
 209
 210         return 0;
 211 }
 212
 213 static void yenta_set_power(pci_socket_t *socket, socket_state_t *state)
 214 {
 215         u32 reg = 0;    /* CB_SC_STPCLK? */
 216         switch (state->Vcc) {
 217         case 33: reg = CB_SC_VCC_3V; break;
 218         case 50: reg = CB_SC_VCC_5V; break;
 219         default: reg = 0; break;
 220         }
 221         switch (state->Vpp) {
 222         case 33:  reg |= CB_SC_VPP_3V; break;
 223         case 50:  reg |= CB_SC_VPP_5V; break;
 224         case 120: reg |= CB_SC_VPP_12V; break;
 225         }
 226         if (reg != cb_readl(socket, CB_SOCKET_CONTROL))
 227                 cb_writel(socket, CB_SOCKET_CONTROL, reg);
 228 }
 229
 230 static int yenta_set_socket(pci_socket_t *socket, socket_state_t *state)
 231 {
 232         u16 bridge;
 233
 234         yenta_set_power(socket, state);
 235         socket->io_irq = state->io_irq;
 236         bridge = config_readw(socket, CB_BRIDGE_CONTROL) & ~(CB_BRIDGE_CRST | CB_BRIDGE_INTR);
 237         if (cb_readl(socket, CB_SOCKET_STATE) & CB_CBCARD) {
 238                 bridge |= (state->flags & SS_RESET) ? CB_BRIDGE_CRST : 0;
 239
 240                 /* ISA interrupt control? */
 241                 if (!socket->cb_irq) {
 242                         u8 intr = exca_readb(socket, I365_INTCTL);
 243                         intr = (intr & ~0xf) | state->io_irq;
 244                         exca_writeb(socket, I365_INTCTL, intr);
 245                         bridge |= CB_BRIDGE_INTR;
 246                 }
 247         } else {
 248                 u8 reg;
 249
 250                 bridge |= CB_BRIDGE_INTR;
 251                 reg = exca_readb(socket, I365_INTCTL) & (I365_RING_ENA | I365_INTR_ENA);
 252                 reg |= (state->flags & SS_RESET) ? 0 : I365_PC_RESET;
 253                 reg |= (state->flags & SS_IOCARD) ? I365_PC_IOCARD : 0;
 254                 reg |= state->io_irq;
 255                 exca_writeb(socket, I365_INTCTL, reg);
 256
 257                 reg = exca_readb(socket, I365_POWER) & (I365_VCC_MASK|I365_VPP1_MASK);
 258                 reg |= I365_PWR_NORESET;
 259                 if (state->flags & SS_PWR_AUTO) reg |= I365_PWR_AUTO;
 260                 if (state->flags & SS_OUTPUT_ENA) reg |= I365_PWR_OUT;
 261                 if (exca_readb(socket, I365_POWER) != reg)
 262                         exca_writeb(socket, I365_POWER, reg);
 263
 264                 /* CSC interrupt: no ISA irq for CSC */
 265                 reg = I365_CSC_DETECT;
 266                 if (state->flags & SS_IOCARD) {
 267                         if (state->csc_mask & SS_STSCHG) reg |= I365_CSC_STSCHG;
 268                 } else {
 269                         if (state->csc_mask & SS_BATDEAD) reg |= I365_CSC_BVD1;
 270                         if (state->csc_mask & SS_BATWARN) reg |= I365_CSC_BVD2;
 271                         if (state->csc_mask & SS_READY) reg |= I365_CSC_READY;
 272                 }
 273                 exca_writeb(socket, I365_CSCINT, reg);
 274                 exca_readb(socket, I365_CSC);
 275         }
 276         config_writew(socket, CB_BRIDGE_CONTROL, bridge);
 277         /* Socket event mask: get card insert/remove events.. */
 278         cb_writel(socket, CB_SOCKET_EVENT, -1);
 279         cb_writel(socket, CB_SOCKET_MASK, CB_CDMASK);
 280         return 0;
 281 }
 282
 283 static int yenta_get_io_map(pci_socket_t *socket, struct pccard_io_map *io)
 284 {
 285         int map;
 286         unsigned char ioctl, addr;
 287
 288         map = io->map;
 289         if (map > 1)
 290                 return -EINVAL;
 291
 292         io->start = exca_readw(socket, I365_IO(map)+I365_W_START);
 293         io->stop = exca_readw(socket, I365_IO(map)+I365_W_STOP);
 294
 295         ioctl = exca_readb(socket, I365_IOCTL);
 296         addr = exca_readb(socket, I365_ADDRWIN);
 297         io->speed = to_ns(ioctl & I365_IOCTL_WAIT(map)) ? 1 : 0;
 298         io->flags  = (addr & I365_ENA_IO(map)) ? MAP_ACTIVE : 0;
 299         io->flags |= (ioctl & I365_IOCTL_0WS(map)) ? MAP_0WS : 0;
 300         io->flags |= (ioctl & I365_IOCTL_16BIT(map)) ? MAP_16BIT : 0;
 301         io->flags |= (ioctl & I365_IOCTL_IOCS16(map)) ? MAP_AUTOSZ : 0;
 302
 303         return 0;
 304 }
 305
 306 static int yenta_set_io_map(pci_socket_t *socket, struct pccard_io_map *io)
 307 {
 308         int map;
 309         unsigned char ioctl, addr, enable;
 310
 311         map = io->map;
 312
 313         if (map > 1)
 314                 return -EINVAL;
 315
 316         enable = I365_ENA_IO(map);
 317         addr = exca_readb(socket, I365_ADDRWIN);
 318
 319         /* Disable the window before changing it.. */
 320         if (addr & enable) {
 321                 addr &= ~enable;
 322                 exca_writeb(socket, I365_ADDRWIN, addr);
 323         }
 324
 325         exca_writew(socket, I365_IO(map)+I365_W_START, io->start);
 326         exca_writew(socket, I365_IO(map)+I365_W_STOP, io->stop);
 327
 328         ioctl = exca_readb(socket, I365_IOCTL) & ~I365_IOCTL_MASK(map);
 329         if (io->flags & MAP_0WS) ioctl |= I365_IOCTL_0WS(map);
 330         if (io->flags & MAP_16BIT) ioctl |= I365_IOCTL_16BIT(map);
 331         if (io->flags & MAP_AUTOSZ) ioctl |= I365_IOCTL_IOCS16(map);
 332         exca_writeb(socket, I365_IOCTL, ioctl);
 333
 334         if (io->flags & MAP_ACTIVE)
 335                 exca_writeb(socket, I365_ADDRWIN, addr | enable);
 336         return 0;
 337 }
 338
 339 static int yenta_get_mem_map(pci_socket_t *socket, struct pccard_mem_map *mem)
 340 {
 341         int map;
 342         unsigned char addr;
 343         unsigned int start, stop, page, offset;
 344
 345         map = mem->map;
 346         if (map > 4)
 347                 return -EINVAL;
 348
 349         addr = exca_readb(socket, I365_ADDRWIN);
 350         mem->flags = (addr & I365_ENA_MEM(map)) ? MAP_ACTIVE : 0;
 351
 352         start = exca_readw(socket, I365_MEM(map) + I365_W_START);
 353         mem->flags |= (start & I365_MEM_16BIT) ? MAP_16BIT : 0;
 354         mem->flags |= (start & I365_MEM_0WS) ? MAP_0WS : 0;
 355         start = (start & 0x0fff) << 12;
 356
 357         stop = exca_readw(socket, I365_MEM(map) + I365_W_STOP);
 358         mem->speed = to_ns(stop >> 14);
 359         stop = ((stop & 0x0fff) << 12) + 0x0fff;
 360
 361         offset = exca_readw(socket, I365_MEM(map) + I365_W_OFF);
 362         mem->flags |= (offset & I365_MEM_WRPROT) ? MAP_WRPROT : 0;
 363         mem->flags |= (offset & I365_MEM_REG) ? MAP_ATTRIB : 0;
 364         offset = ((offset & 0x3fff) << 12) + start;
 365         mem->card_start = offset & 0x3ffffff;
 366
 367         page = exca_readb(socket, CB_MEM_PAGE(map)) << 24;
 368         mem->sys_start = start + page;
 369         mem->sys_stop = start + page;
 370
 371         return 0;
 372 }
 373
 374 static int yenta_set_mem_map(pci_socket_t *socket, struct pccard_mem_map *mem)
 375 {
 376         int map;
 377         unsigned char addr, enable;
 378         unsigned int start, stop, card_start;
 379         unsigned short word;
 380
 381         map = mem->map;
 382         start = mem->sys_start;
 383         stop = mem->sys_stop;
 384         card_start = mem->card_start;
 385
 386         if (map > 4 || start > stop || ((start ^ stop) >> 24) ||
 387             (card_start >> 26) || mem->speed > 1000)
 388                 return -EINVAL;
 389
 390         enable = I365_ENA_MEM(map);
 391         addr = exca_readb(socket, I365_ADDRWIN);
 392         if (addr & enable) {
 393                 addr &= ~enable;
 394                 exca_writeb(socket, I365_ADDRWIN, addr);
 395         }
 396
 397         exca_writeb(socket, CB_MEM_PAGE(map), start >> 24);
 398
 399         word = (start >> 12) & 0x0fff;
 400         if (mem->flags & MAP_16BIT)
 401                 word |= I365_MEM_16BIT;
 402         if (mem->flags & MAP_0WS)
 403                 word |= I365_MEM_0WS;
 404         exca_writew(socket, I365_MEM(map) + I365_W_START, word);
 405
 406         word = (stop >> 12) & 0x0fff;
 407         switch (to_cycles(mem->speed)) {
 408                 case 0: break;
 409                 case 1:  word |= I365_MEM_WS0; break;
 410                 case 2:  word |= I365_MEM_WS1; break;
 411                 default: word |= I365_MEM_WS1 | I365_MEM_WS0; break;
 412         }
 413         exca_writew(socket, I365_MEM(map) + I365_W_STOP, word);
 414
 415         word = ((card_start - start) >> 12) & 0x3fff;
 416         if (mem->flags & MAP_WRPROT)
 417                 word |= I365_MEM_WRPROT;
 418         if (mem->flags & MAP_ATTRIB)
 419                 word |= I365_MEM_REG;
 420         exca_writew(socket, I365_MEM(map) + I365_W_OFF, word);
 421
 422         if (mem->flags & MAP_ACTIVE)
 423                 exca_writeb(socket, I365_ADDRWIN, addr | enable);
 424         return 0;
 425 }
 426
 427 static void yenta_proc_setup(pci_socket_t *socket, struct proc_dir_entry *base)
 428 {
 429         /* Not done yet */
 430 }
 431
 432 static unsigned int yenta_events(pci_socket_t *socket)
 433 {
 434         u8 csc;
 435         u32 cb_event;
 436         unsigned int events;
 437
 438         /* Clear interrupt status for the event */
 439         cb_event = cb_readl(socket, CB_SOCKET_EVENT);
 440         cb_writel(socket, CB_SOCKET_EVENT, cb_event);
 441
 442         csc = exca_readb(socket, I365_CSC);
 443
 444         events = (cb_event & (CB_CD1EVENT | CB_CD2EVENT)) ? SS_DETECT : 0 ;
 445         events |= (csc & I365_CSC_DETECT) ? SS_DETECT : 0;
 446         if (exca_readb(socket, I365_INTCTL) & I365_PC_IOCARD) {
 447                 events |= (csc & I365_CSC_STSCHG) ? SS_STSCHG : 0;
 448         } else {
 449                 events |= (csc & I365_CSC_BVD1) ? SS_BATDEAD : 0;
 450                 events |= (csc & I365_CSC_BVD2) ? SS_BATWARN : 0;
 451                 events |= (csc & I365_CSC_READY) ? SS_READY : 0;
 452         }
 453         return events;
 454 }
 455
 456 static void yenta_interrupt(int irq, void *dev_id, struct pt_regs *regs)
 457 {
 458         unsigned int events;
 459         pci_socket_t *socket = (pci_socket_t *) dev_id;
 460
 461         events = yenta_events(socket);
 462         if (events) {
 463                 socket->events |= events;
 464                 wake_up_interruptible(&socket->wait);
 465         }
 466 }
 467
 468 /*
 469  * Watch a socket every second (and possibly in a
 470  * more timely manner if the state change interrupt
 471  * works..)
 472  */
 473 static int yenta_socket_thread(void * data)
 474 {
 475         pci_socket_t * socket = (pci_socket_t *) data;
 476         DECLARE_WAITQUEUE(wait, current);
 477
 478         daemonize();
 479         strcpy(current->comm, "CardBus Watcher");
 480
 481         do {
 482                 unsigned int events = socket->events | yenta_events(socket);
 483
 484                 if (events) {
 485                         socket->events = 0;
 486                         if (socket->handler)
 487                                 socket->handler(socket->info, events);
 488                 }
 489
 490                 current->state = TASK_INTERRUPTIBLE;
 491                 add_wait_queue(&socket->wait, &wait);
 492                 if (!socket->events)
 493                         schedule_timeout(HZ);
 494                 remove_wait_queue(&socket->wait, &wait);
 495         } while (!signal_pending(current));
 496         return 0;
 497 }
 498
 499 static unsigned int yenta_probe_irq(pci_socket_t *socket)
 500 {
 501         int i;
 502         unsigned long val;
 503         u16 bridge_ctrl;
 504         u32 mask;
 505
 506         /* Set up ISA irq routing to probe the ISA irqs.. */
 507         bridge_ctrl = config_readw(socket, CB_BRIDGE_CONTROL);
 508         if (!(bridge_ctrl & CB_BRIDGE_INTR)) {
 509                 bridge_ctrl |= CB_BRIDGE_INTR;
 510                 config_writew(socket, CB_BRIDGE_CONTROL, bridge_ctrl);
 511         }
 512
 513         /*
 514          * Probe for usable interrupts using the force
 515          * register to generate bogus card status events.
 516          */
 517         cb_writel(socket, CB_SOCKET_EVENT, -1);
 518         cb_writel(socket, CB_SOCKET_MASK, CB_CSTSMASK);
 519         val = probe_irq_on();
 520         for (i = 1; i < 16; i++) {
 521                 if (!((val >> i) & 1))
 522                         continue;
 523                 exca_writeb(socket, I365_CSCINT, I365_CSC_STSCHG | (i << 4));
 524                 cb_writel(socket, CB_SOCKET_FORCE, CB_FCARDSTS);
 525                 udelay(100);
 526                 cb_writel(socket, CB_SOCKET_EVENT, -1);
 527         }
 528         cb_writel(socket, CB_SOCKET_MASK, 0);
 529
 530         mask = probe_irq_mask(val) & 0xffff;
 531
 532         bridge_ctrl &= ~CB_BRIDGE_INTR;
 533         config_writew(socket, CB_BRIDGE_CONTROL, bridge_ctrl);
 534
 535         return mask;
 536 }
 537
 538 static void yenta_clear_maps(pci_socket_t *socket)
 539 {
 540         int i;
 541         pccard_io_map io = { 0, 0, 0, 0, 1 };
 542         pccard_mem_map mem = { 0, 0, 0, 0, 0, 0 };
 543
 544         mem.sys_stop = 0x0fff;
 545         yenta_set_socket(socket, &dead_socket);
 546         for (i = 0; i < 2; i++) {
 547                 io.map = i;
 548                 yenta_set_io_map(socket, &io);
 549         }
 550         for (i = 0; i < 5; i++) {
 551                 mem.map = i;
 552                 yenta_set_mem_map(socket, &mem);
 553         }
 554 }
 555
 556 /* Called at resume and initialization events */
 557 static int yenta_init(pci_socket_t *socket)
 558 {
 559         u16 bridge;
 560         struct pci_dev *dev = socket->dev;
 561
 562         pci_set_power_state(socket->dev, 0);
 563
 564         config_writel(socket, CB_LEGACY_MODE_BASE, 0);
 565         config_writel(socket, PCI_BASE_ADDRESS_0, dev->resource[0].start);
 566         config_writew(socket, PCI_COMMAND,
 567                         PCI_COMMAND_IO |
 568                         PCI_COMMAND_MEMORY |
 569                         PCI_COMMAND_MASTER |
 570                         PCI_COMMAND_WAIT);
 571
 572         /* MAGIC NUMBERS! Fixme */
 573         config_writeb(socket, PCI_CACHE_LINE_SIZE, 32);
 574         config_writeb(socket, PCI_LATENCY_TIMER, 168);
 575         config_writeb(socket, PCI_SEC_LATENCY_TIMER, 176);
 576         config_writeb(socket, PCI_PRIMARY_BUS, dev->bus->number);
 577         config_writeb(socket, PCI_SECONDARY_BUS, dev->subordinate->number);
 578         config_writeb(socket, PCI_SUBORDINATE_BUS, dev->subordinate->number);
 579
 580         /*
 581          * Set up the bridging state:
 582          *  - enable write posting.
 583          *  - memory window 0 prefetchable, window 1 non-prefetchable
 584          *  - PCI interrupts enabled if a PCI interrupt exists..
 585          */
 586         bridge = config_readw(socket, CB_BRIDGE_CONTROL);
 587         bridge &= ~(CB_BRIDGE_CRST | CB_BRIDGE_PREFETCH1 | CB_BRIDGE_INTR | CB_BRIDGE_ISAEN | CB_BRIDGE_VGAEN);
 588         bridge |= CB_BRIDGE_PREFETCH0 | CB_BRIDGE_POSTEN;
 589         if (!socket->cb_irq)
 590                 bridge |= CB_BRIDGE_INTR;
 591         config_writew(socket, CB_BRIDGE_CONTROL, bridge);
 592
 593         exca_writeb(socket, I365_GBLCTL, 0x00);
 594         exca_writeb(socket, I365_GENCTL, 0x00);
 595
 596         yenta_clear_maps(socket);
 597         return 0;
 598 }
 599
 600 static int yenta_suspend(pci_socket_t *socket)
 601 {
 602         yenta_set_socket(socket, &dead_socket);
 603         pci_set_power_state(socket->dev, 3);
 604         return 0;
 605 }
 606
 607 /*
 608  * Set static data that doesn't need re-initializing..
 609  */
 610 static void yenta_get_socket_capabilities(pci_socket_t *socket)
 611 {
 612         socket->cap.features |= SS_CAP_PAGE_REGS | SS_CAP_PCCARD | SS_CAP_CARDBUS;
 613         socket->cap.map_size = 0x1000;
 614         socket->cap.pci_irq = socket->cb_irq;
 615         socket->cap.irq_mask = yenta_probe_irq(socket);
 616         socket->cap.cb_dev = socket->dev;
 617         socket->cap.bus = NULL;
 618
 619         printk("Yenta IRQ list %04x, PCI irq%d\n", socket->cap.irq_mask, socket->cb_irq);
 620 }
 621
 622 static void yenta_allocate_res(pci_socket_t *socket, int nr, unsigned type)
 623 {
 624         struct pci_bus *bus;
 625         struct resource *root, *res;
 626         u32 start, end;
 627         u32 align, size, min, max;
 628         unsigned offset;
 629
 630         offset = 0x1c + 8*nr;
 631         bus = socket->dev->subordinate;
 632         res = socket->dev->resource + PCI_BRIDGE_RESOURCES + nr;
 633         res->name = bus->name;
 634         res->flags = type;
 635         res->start = 0;
 636         res->end = 0;
 637         root = pci_find_parent_resource(socket->dev, res);
 638
 639         if (!root)
 640                 return;
 641
 642         start = config_readl(socket, offset);
 643         end = config_readl(socket, offset+4) | 0xfff;
 644         if (start && end > start) {
 645                 res->start = start;
 646                 res->end = end;
 647                 request_resource(root, res);
 648                 return;
 649         }
 650
 651         align = size = 4*1024*1024;
 652         min = PCIBIOS_MIN_MEM; max = ~0U;
 653         if (type & IORESOURCE_IO) {
 654                 align = 1024;
 655                 size = 256;
 656                 min = PCIBIOS_MIN_IO;
 657                 max = 0xffff;
 658         }
 659
 660         if (allocate_resource(root, res, size, min, max, align, NULL, NULL) < 0)
 661                 return;
 662
 663         config_writel(socket, offset, res->start);
 664         config_writel(socket, offset+4, res->end);
 665 }
 666
 667 /*
 668  * Allocate the bridge mappings for the device..
 669  */
 670 static void yenta_allocate_resources(pci_socket_t *socket)
 671 {
 672         yenta_allocate_res(socket, 0, IORESOURCE_MEM|IORESOURCE_PREFETCH);
 673         yenta_allocate_res(socket, 1, IORESOURCE_MEM);
 674         yenta_allocate_res(socket, 2, IORESOURCE_IO);
 675 }
 676
 677 /*
 678  * Close it down - release our resources and go home..
 679  */
 680 static void yenta_close(pci_socket_t *sock)
 681 {
 682         if (sock->cb_irq)
 683                 free_irq(sock->cb_irq, sock);
 684         if (sock->base)
 685                 iounmap(sock->base);
 686 }
 687
 688 #include "ti113x.h"
 689 #include "ricoh.h"
 690
 691 /*
 692  * Different cardbus controllers have slightly different
 693  * initialization sequences etc details. List them here..
 694  */
 695 #define PD(x,y) PCI_VENDOR_ID_##x, PCI_DEVICE_ID_##x##_##y
 696 static struct cardbus_override_struct {
 697         unsigned short vendor;
 698         unsigned short device;
 699         struct pci_socket_ops *op;
 700 } cardbus_override[] = {
 701         { PD(TI,1130),  &ti113x_ops },
 702         { PD(TI,1131),  &ti113x_ops },
 703         { PD(TI,1250),  &ti1250_ops },
 704
 705         { PD(RICOH,RL5C465), &ricoh_ops },
 706         { PD(RICOH,RL5C466), &ricoh_ops },
 707         { PD(RICOH,RL5C475), &ricoh_ops },
 708         { PD(RICOH,RL5C476), &ricoh_ops },
 709         { PD(RICOH,RL5C478), &ricoh_ops }
 710 };
 711
 712 #define NR_OVERRIDES (sizeof(cardbus_override)/sizeof(struct cardbus_override_struct))
 713
 714 /*
 715  * Initialize a cardbus controller. Make sure we have a usable
 716  * interrupt, and that we can map the cardbus area. Fill in the
 717  * socket information structure..
 718  */
 719 static int yenta_open(pci_socket_t *socket)
 720 {
 721         int i;
 722         struct pci_dev *dev = socket->dev;
 723
 724         /*
 725          * Do some basic sanity checking..
 726          */
 727         if (pci_enable_device(dev)) {
 728                 printk("Unable to enable device\n");
 729                 return -1;
 730         }
 731         if (!dev->resource[0].start) {
 732                 printk("No cardbus resource!\n");
 733                 return -1;
 734         }
 735
 736         /*
 737          * Ok, start setup.. Map the cardbus registers,
 738          * and request the IRQ.
 739          */
 740         socket->base = ioremap(dev->resource[0].start, 0x1000);
 741         if (!socket->base)
 742                 return -1;
 743
 744         /* Disable all events */
 745         cb_writel(socket, CB_SOCKET_MASK, 0x0);
 746
 747         /* Set up the bridge regions.. */
 748         yenta_allocate_resources(socket);
 749
 750         if (dev->irq && !request_irq(dev->irq, yenta_interrupt, SA_SHIRQ, dev->name, socket))
 751                 socket->cb_irq = dev->irq;
 752
 753         /* And figure out what the dang thing can do for the PCMCIA layer... */
 754         yenta_get_socket_capabilities(socket);
 755
 756         /* Do we have special options for the device? */
 757         for (i = 0; i < NR_OVERRIDES; i++) {
 758                 struct cardbus_override_struct *d = cardbus_override+i;
 759                 if (dev->vendor == d->vendor && dev->device == d->device) {
 760                         socket->op = d->op;
 761                         if (d->op->open) {
 762                                 int retval = d->op->open(socket);
 763                                 if (retval < 0)
 764                                         return retval;
 765                         }
 766                 }
 767         }
 768
 769         kernel_thread(yenta_socket_thread, socket, CLONE_FS | CLONE_FILES | CLONE_SIGHAND);
 770         printk("Socket status: %08x\n", cb_readl(socket, CB_SOCKET_STATE));
 771         return 0;
 772 }
 773
 774 /*
 775  * Standard plain cardbus - no frills, no extensions
 776  */
 777 struct pci_socket_ops yenta_operations = {
 778         yenta_open,
 779         yenta_close,
 780         yenta_init,
 781         yenta_suspend,
 782         yenta_get_status,
 783         yenta_get_socket,
 784         yenta_set_socket,
 785         yenta_get_io_map,
 786         yenta_set_io_map,
 787         yenta_get_mem_map,
 788         yenta_set_mem_map,
 789         yenta_proc_setup
 790 };
 791 EXPORT_SYMBOL(yenta_operations);
 792
 793 /*
 794  * Ricoh cardbus bridge: standard cardbus, except it needs
 795  * some extra init code to set timings etc.
 796  */
 797 struct pci_socket_ops ricoh_operations = {
 798         yenta_open,
 799         yenta_close,
 800         ricoh_init,
 801         yenta_suspend,
 802         yenta_get_status,
 803         yenta_get_socket,
 804         yenta_set_socket,
 805         yenta_get_io_map,
 806         yenta_set_io_map,
 807         yenta_get_mem_map,
 808         yenta_set_mem_map,
 809         yenta_proc_setup
 810 };