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[davej-history.git] / include / linux / pci.h
blob1efa437bb08ff038a352592342b593fbae827f38
1 /*
2 * $Id: pci.h,v 1.87 1998/10/11 15:13:12 mj Exp $
3 *
4 * PCI defines and function prototypes
5 * Copyright 1994, Drew Eckhardt
6 * Copyright 1997--1999 Martin Mares <mj@suse.cz>
7 *
8 * For more information, please consult the following manuals (look at
9 * http://www.pcisig.com/ for how to get them):
10 *
11 * PCI BIOS Specification
12 * PCI Local Bus Specification
13 * PCI to PCI Bridge Specification
14 * PCI System Design Guide
15 */
16
17 #ifndef LINUX_PCI_H
18 #define LINUX_PCI_H
19
20 /*
21 * Under PCI, each device has 256 bytes of configuration address space,
22 * of which the first 64 bytes are standardized as follows:
23 */
24 #define PCI_VENDOR_ID 0x00 /* 16 bits */
25 #define PCI_DEVICE_ID 0x02 /* 16 bits */
26 #define PCI_COMMAND 0x04 /* 16 bits */
27 #define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */
28 #define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */
29 #define PCI_COMMAND_MASTER 0x4 /* Enable bus mastering */
30 #define PCI_COMMAND_SPECIAL 0x8 /* Enable response to special cycles */
31 #define PCI_COMMAND_INVALIDATE 0x10 /* Use memory write and invalidate */
32 #define PCI_COMMAND_VGA_PALETTE 0x20 /* Enable palette snooping */
33 #define PCI_COMMAND_PARITY 0x40 /* Enable parity checking */
34 #define PCI_COMMAND_WAIT 0x80 /* Enable address/data stepping */
35 #define PCI_COMMAND_SERR 0x100 /* Enable SERR */
36 #define PCI_COMMAND_FAST_BACK 0x200 /* Enable back-to-back writes */
37
38 #define PCI_STATUS 0x06 /* 16 bits */
39 #define PCI_STATUS_CAP_LIST 0x10 /* Support Capability List */
40 #define PCI_STATUS_66MHZ 0x20 /* Support 66 Mhz PCI 2.1 bus */
41 #define PCI_STATUS_UDF 0x40 /* Support User Definable Features [obsolete] */
42 #define PCI_STATUS_FAST_BACK 0x80 /* Accept fast-back to back */
43 #define PCI_STATUS_PARITY 0x100 /* Detected parity error */
44 #define PCI_STATUS_DEVSEL_MASK 0x600 /* DEVSEL timing */
45 #define PCI_STATUS_DEVSEL_FAST 0x000
46 #define PCI_STATUS_DEVSEL_MEDIUM 0x200
47 #define PCI_STATUS_DEVSEL_SLOW 0x400
48 #define PCI_STATUS_SIG_TARGET_ABORT 0x800 /* Set on target abort */
49 #define PCI_STATUS_REC_TARGET_ABORT 0x1000 /* Master ack of " */
50 #define PCI_STATUS_REC_MASTER_ABORT 0x2000 /* Set on master abort */
51 #define PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 /* Set when we drive SERR */
52 #define PCI_STATUS_DETECTED_PARITY 0x8000 /* Set on parity error */
53
54 #define PCI_CLASS_REVISION 0x08 /* High 24 bits are class, low 8
55 revision */
56 #define PCI_REVISION_ID 0x08 /* Revision ID */
57 #define PCI_CLASS_PROG 0x09 /* Reg. Level Programming Interface */
58 #define PCI_CLASS_DEVICE 0x0a /* Device class */
59
60 #define PCI_CACHE_LINE_SIZE 0x0c /* 8 bits */
61 #define PCI_LATENCY_TIMER 0x0d /* 8 bits */
62 #define PCI_HEADER_TYPE 0x0e /* 8 bits */
63 #define PCI_HEADER_TYPE_NORMAL 0
64 #define PCI_HEADER_TYPE_BRIDGE 1
65 #define PCI_HEADER_TYPE_CARDBUS 2
66
67 #define PCI_BIST 0x0f /* 8 bits */
68 #define PCI_BIST_CODE_MASK 0x0f /* Return result */
69 #define PCI_BIST_START 0x40 /* 1 to start BIST, 2 secs or less */
70 #define PCI_BIST_CAPABLE 0x80 /* 1 if BIST capable */
71
72 /*
73 * Base addresses specify locations in memory or I/O space.
74 * Decoded size can be determined by writing a value of
75 * 0xffffffff to the register, and reading it back. Only
76 * 1 bits are decoded.
77 */
78 #define PCI_BASE_ADDRESS_0 0x10 /* 32 bits */
79 #define PCI_BASE_ADDRESS_1 0x14 /* 32 bits [htype 0,1 only] */
80 #define PCI_BASE_ADDRESS_2 0x18 /* 32 bits [htype 0 only] */
81 #define PCI_BASE_ADDRESS_3 0x1c /* 32 bits */
82 #define PCI_BASE_ADDRESS_4 0x20 /* 32 bits */
83 #define PCI_BASE_ADDRESS_5 0x24 /* 32 bits */
84 #define PCI_BASE_ADDRESS_SPACE 0x01 /* 0 = memory, 1 = I/O */
85 #define PCI_BASE_ADDRESS_SPACE_IO 0x01
86 #define PCI_BASE_ADDRESS_SPACE_MEMORY 0x00
87 #define PCI_BASE_ADDRESS_MEM_TYPE_MASK 0x06
88 #define PCI_BASE_ADDRESS_MEM_TYPE_32 0x00 /* 32 bit address */
89 #define PCI_BASE_ADDRESS_MEM_TYPE_1M 0x02 /* Below 1M [obsolete] */
90 #define PCI_BASE_ADDRESS_MEM_TYPE_64 0x04 /* 64 bit address */
91 #define PCI_BASE_ADDRESS_MEM_PREFETCH 0x08 /* prefetchable? */
92 #define PCI_BASE_ADDRESS_MEM_MASK (~0x0fUL)
93 #define PCI_BASE_ADDRESS_IO_MASK (~0x03UL)
94 /* bit 1 is reserved if address_space = 1 */
95
96 /* Header type 0 (normal devices) */
97 #define PCI_CARDBUS_CIS 0x28
98 #define PCI_SUBSYSTEM_VENDOR_ID 0x2c
99 #define PCI_SUBSYSTEM_ID 0x2e
100 #define PCI_ROM_ADDRESS 0x30 /* Bits 31..11 are address, 10..1 reserved */
101 #define PCI_ROM_ADDRESS_ENABLE 0x01
102 #define PCI_ROM_ADDRESS_MASK (~0x7ffUL)
103
104 #define PCI_CAPABILITY_LIST 0x34 /* Offset of first capability list entry */
105
106 /* 0x35-0x3b are reserved */
107 #define PCI_INTERRUPT_LINE 0x3c /* 8 bits */
108 #define PCI_INTERRUPT_PIN 0x3d /* 8 bits */
109 #define PCI_MIN_GNT 0x3e /* 8 bits */
110 #define PCI_MAX_LAT 0x3f /* 8 bits */
111
112 /* Header type 1 (PCI-to-PCI bridges) */
113 #define PCI_PRIMARY_BUS 0x18 /* Primary bus number */
114 #define PCI_SECONDARY_BUS 0x19 /* Secondary bus number */
115 #define PCI_SUBORDINATE_BUS 0x1a /* Highest bus number behind the bridge */
116 #define PCI_SEC_LATENCY_TIMER 0x1b /* Latency timer for secondary interface */
117 #define PCI_IO_BASE 0x1c /* I/O range behind the bridge */
118 #define PCI_IO_LIMIT 0x1d
119 #define PCI_IO_RANGE_TYPE_MASK 0x0f /* I/O bridging type */
120 #define PCI_IO_RANGE_TYPE_16 0x00
121 #define PCI_IO_RANGE_TYPE_32 0x01
122 #define PCI_IO_RANGE_MASK ~0x0f
123 #define PCI_SEC_STATUS 0x1e /* Secondary status register, only bit 14 used */
124 #define PCI_MEMORY_BASE 0x20 /* Memory range behind */
125 #define PCI_MEMORY_LIMIT 0x22
126 #define PCI_MEMORY_RANGE_TYPE_MASK 0x0f
127 #define PCI_MEMORY_RANGE_MASK ~0x0f
128 #define PCI_PREF_MEMORY_BASE 0x24 /* Prefetchable memory range behind */
129 #define PCI_PREF_MEMORY_LIMIT 0x26
130 #define PCI_PREF_RANGE_TYPE_MASK 0x0f
131 #define PCI_PREF_RANGE_TYPE_32 0x00
132 #define PCI_PREF_RANGE_TYPE_64 0x01
133 #define PCI_PREF_RANGE_MASK ~0x0f
134 #define PCI_PREF_BASE_UPPER32 0x28 /* Upper half of prefetchable memory range */
135 #define PCI_PREF_LIMIT_UPPER32 0x2c
136 #define PCI_IO_BASE_UPPER16 0x30 /* Upper half of I/O addresses */
137 #define PCI_IO_LIMIT_UPPER16 0x32
138 /* 0x34 same as for htype 0 */
139 /* 0x35-0x3b is reserved */
140 #define PCI_ROM_ADDRESS1 0x38 /* Same as PCI_ROM_ADDRESS, but for htype 1 */
141 /* 0x3c-0x3d are same as for htype 0 */
142 #define PCI_BRIDGE_CONTROL 0x3e
143 #define PCI_BRIDGE_CTL_PARITY 0x01 /* Enable parity detection on secondary interface */
144 #define PCI_BRIDGE_CTL_SERR 0x02 /* The same for SERR forwarding */
145 #define PCI_BRIDGE_CTL_NO_ISA 0x04 /* Disable bridging of ISA ports */
146 #define PCI_BRIDGE_CTL_VGA 0x08 /* Forward VGA addresses */
147 #define PCI_BRIDGE_CTL_MASTER_ABORT 0x20 /* Report master aborts */
148 #define PCI_BRIDGE_CTL_BUS_RESET 0x40 /* Secondary bus reset */
149 #define PCI_BRIDGE_CTL_FAST_BACK 0x80 /* Fast Back2Back enabled on secondary interface */
150
151 /* Header type 2 (CardBus bridges) */
152 #define PCI_CB_CAPABILITY_LIST 0x14
153 /* 0x15 reserved */
154 #define PCI_CB_SEC_STATUS 0x16 /* Secondary status */
155 #define PCI_CB_PRIMARY_BUS 0x18 /* PCI bus number */
156 #define PCI_CB_CARD_BUS 0x19 /* CardBus bus number */
157 #define PCI_CB_SUBORDINATE_BUS 0x1a /* Subordinate bus number */
158 #define PCI_CB_LATENCY_TIMER 0x1b /* CardBus latency timer */
159 #define PCI_CB_MEMORY_BASE_0 0x1c
160 #define PCI_CB_MEMORY_LIMIT_0 0x20
161 #define PCI_CB_MEMORY_BASE_1 0x24
162 #define PCI_CB_MEMORY_LIMIT_1 0x28
163 #define PCI_CB_IO_BASE_0 0x2c
164 #define PCI_CB_IO_BASE_0_HI 0x2e
165 #define PCI_CB_IO_LIMIT_0 0x30
166 #define PCI_CB_IO_LIMIT_0_HI 0x32
167 #define PCI_CB_IO_BASE_1 0x34
168 #define PCI_CB_IO_BASE_1_HI 0x36
169 #define PCI_CB_IO_LIMIT_1 0x38
170 #define PCI_CB_IO_LIMIT_1_HI 0x3a
171 #define PCI_CB_IO_RANGE_MASK ~0x03
172 /* 0x3c-0x3d are same as for htype 0 */
173 #define PCI_CB_BRIDGE_CONTROL 0x3e
174 #define PCI_CB_BRIDGE_CTL_PARITY 0x01 /* Similar to standard bridge control register */
175 #define PCI_CB_BRIDGE_CTL_SERR 0x02
176 #define PCI_CB_BRIDGE_CTL_ISA 0x04
177 #define PCI_CB_BRIDGE_CTL_VGA 0x08
178 #define PCI_CB_BRIDGE_CTL_MASTER_ABORT 0x20
179 #define PCI_CB_BRIDGE_CTL_CB_RESET 0x40 /* CardBus reset */
180 #define PCI_CB_BRIDGE_CTL_16BIT_INT 0x80 /* Enable interrupt for 16-bit cards */
181 #define PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 0x100 /* Prefetch enable for both memory regions */
182 #define PCI_CB_BRIDGE_CTL_PREFETCH_MEM1 0x200
183 #define PCI_CB_BRIDGE_CTL_POST_WRITES 0x400
184 #define PCI_CB_SUBSYSTEM_VENDOR_ID 0x40
185 #define PCI_CB_SUBSYSTEM_ID 0x42
186 #define PCI_CB_LEGACY_MODE_BASE 0x44 /* 16-bit PC Card legacy mode base address (ExCa) */
187 /* 0x48-0x7f reserved */
188
189 /* Capability lists */
190
191 #define PCI_CAP_LIST_ID 0 /* Capability ID */
192 #define PCI_CAP_ID_PM 0x01 /* Power Management */
193 #define PCI_CAP_ID_AGP 0x02 /* Accelerated Graphics Port */
194 #define PCI_CAP_ID_VPD 0x03 /* Vital Product Data */
195 #define PCI_CAP_ID_SLOTID 0x04 /* Slot Identification */
196 #define PCI_CAP_ID_MSI 0x05 /* Message Signalled Interrupts */
197 #define PCI_CAP_ID_CHSWP 0x06 /* CompactPCI HotSwap */
198 #define PCI_CAP_LIST_NEXT 1 /* Next capability in the list */
199 #define PCI_CAP_FLAGS 2 /* Capability defined flags (16 bits) */
200 #define PCI_CAP_SIZEOF 4
201
202 /* Power Management Registers */
203
204 #define PCI_PM_CAP_VER_MASK 0x0007 /* Version */
205 #define PCI_PM_CAP_PME_CLOCK 0x0008 /* PME clock required */
206 #define PCI_PM_CAP_AUX_POWER 0x0010 /* Auxilliary power support */
207 #define PCI_PM_CAP_DSI 0x0020 /* Device specific initialization */
208 #define PCI_PM_CAP_D1 0x0200 /* D1 power state support */
209 #define PCI_PM_CAP_D2 0x0400 /* D2 power state support */
210 #define PCI_PM_CAP_PME 0x0800 /* PME pin supported */
211 #define PCI_PM_CTRL 4 /* PM control and status register */
212 #define PCI_PM_CTRL_STATE_MASK 0x0003 /* Current power state (D0 to D3) */
213 #define PCI_PM_CTRL_PME_ENABLE 0x0100 /* PME pin enable */
214 #define PCI_PM_CTRL_DATA_SEL_MASK 0x1e00 /* Data select (??) */
215 #define PCI_PM_CTRL_DATA_SCALE_MASK 0x6000 /* Data scale (??) */
216 #define PCI_PM_CTRL_PME_STATUS 0x8000 /* PME pin status */
217 #define PCI_PM_PPB_EXTENSIONS 6 /* PPB support extensions (??) */
218 #define PCI_PM_PPB_B2_B3 0x40 /* Stop clock when in D3hot (??) */
219 #define PCI_PM_BPCC_ENABLE 0x80 /* Bus power/clock control enable (??) */
220 #define PCI_PM_DATA_REGISTER 7 /* (??) */
221 #define PCI_PM_SIZEOF 8
222
223 /* AGP registers */
224
225 #define PCI_AGP_VERSION 2 /* BCD version number */
226 #define PCI_AGP_RFU 3 /* Rest of capability flags */
227 #define PCI_AGP_STATUS 4 /* Status register */
228 #define PCI_AGP_STATUS_RQ_MASK 0xff000000 /* Maximum number of requests - 1 */
229 #define PCI_AGP_STATUS_SBA 0x0200 /* Sideband addressing supported */
230 #define PCI_AGP_STATUS_64BIT 0x0020 /* 64-bit addressing supported */
231 #define PCI_AGP_STATUS_FW 0x0010 /* FW transfers supported */
232 #define PCI_AGP_STATUS_RATE4 0x0004 /* 4x transfer rate supported */
233 #define PCI_AGP_STATUS_RATE2 0x0002 /* 2x transfer rate supported */
234 #define PCI_AGP_STATUS_RATE1 0x0001 /* 1x transfer rate supported */
235 #define PCI_AGP_COMMAND 8 /* Control register */
236 #define PCI_AGP_COMMAND_RQ_MASK 0xff000000 /* Master: Maximum number of requests */
237 #define PCI_AGP_COMMAND_SBA 0x0200 /* Sideband addressing enabled */
238 #define PCI_AGP_COMMAND_AGP 0x0100 /* Allow processing of AGP transactions */
239 #define PCI_AGP_COMMAND_64BIT 0x0020 /* Allow processing of 64-bit addresses */
240 #define PCI_AGP_COMMAND_FW 0x0010 /* Force FW transfers */
241 #define PCI_AGP_COMMAND_RATE4 0x0004 /* Use 4x rate */
242 #define PCI_AGP_COMMAND_RATE2 0x0002 /* Use 4x rate */
243 #define PCI_AGP_COMMAND_RATE1 0x0001 /* Use 4x rate */
244 #define PCI_AGP_SIZEOF 12
245
246 /* Slot Identification */
247
248 #define PCI_SID_ESR 2 /* Expansion Slot Register */
249 #define PCI_SID_ESR_NSLOTS 0x1f /* Number of expansion slots available */
250 #define PCI_SID_ESR_FIC 0x20 /* First In Chassis Flag */
251 #define PCI_SID_CHASSIS_NR 3 /* Chassis Number */
252
253 /* Message Signalled Interrupts registers */
254
255 #define PCI_MSI_FLAGS 2 /* Various flags */
256 #define PCI_MSI_FLAGS_64BIT 0x80 /* 64-bit addresses allowed */
257 #define PCI_MSI_FLAGS_QSIZE 0x70 /* Message queue size configured */
258 #define PCI_MSI_FLAGS_QMASK 0x0e /* Maximum queue size available */
259 #define PCI_MSI_FLAGS_ENABLE 0x01 /* MSI feature enabled */
260 #define PCI_MSI_RFU 3 /* Rest of capability flags */
261 #define PCI_MSI_ADDRESS_LO 4 /* Lower 32 bits */
262 #define PCI_MSI_ADDRESS_HI 8 /* Upper 32 bits (if PCI_MSI_FLAGS_64BIT set) */
263 #define PCI_MSI_DATA_32 8 /* 16 bits of data for 32-bit devices */
264 #define PCI_MSI_DATA_64 12 /* 16 bits of data for 64-bit devices */
265
266 /* Include the ID list */
267
268 #include <linux/pci_ids.h>
269
270 /*
271 * The PCI interface treats multi-function devices as independent
272 * devices. The slot/function address of each device is encoded
273 * in a single byte as follows:
274 *
275 * 7:3 = slot
276 * 2:0 = function
277 */
278 #define PCI_DEVFN(slot,func) ((((slot) & 0x1f) << 3) | ((func) & 0x07))
279 #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f)
280 #define PCI_FUNC(devfn) ((devfn) & 0x07)
281
282 #ifdef __KERNEL__
283
284 #include <linux/types.h>
285 #include <linux/config.h>
286 #include <linux/ioport.h>
287 #include <linux/list.h>
288 #include <linux/errno.h>
289
290 /* This defines the direction arg to the DMA mapping routines. */
291 #define PCI_DMA_BIDIRECTIONAL 0
292 #define PCI_DMA_TODEVICE 1
293 #define PCI_DMA_FROMDEVICE 2
294 #define PCI_DMA_NONE 3
295
296 #define DEVICE_COUNT_COMPATIBLE 4
297 #define DEVICE_COUNT_IRQ 2
298 #define DEVICE_COUNT_DMA 2
299 #define DEVICE_COUNT_RESOURCE 12
300
301 /*
302 * The pci_dev structure is used to describe both PCI and ISAPnP devices.
303 */
304 struct pci_dev {
305 struct list_head global_list; /* node in list of all PCI devices */
306 struct list_head bus_list; /* node in per-bus list */
307 struct pci_bus *bus; /* bus this device is on */
308 struct pci_bus *subordinate; /* bus this device bridges to */
309
310 void *sysdata; /* hook for sys-specific extension */
311 struct proc_dir_entry *procent; /* device entry in /proc/bus/pci */
312
313 unsigned int devfn; /* encoded device & function index */
314 unsigned short vendor;
315 unsigned short device;
316 unsigned short subsystem_vendor;
317 unsigned short subsystem_device;
318 unsigned int class; /* 3 bytes: (base,sub,prog-if) */
319 u8 hdr_type; /* PCI header type (`multi' flag masked out) */
320 u8 rom_base_reg; /* which config register controls the ROM */
321
322 struct pci_driver *driver; /* which driver has allocated this device */
323 void *driver_data; /* data private to the driver */
324 dma_addr_t dma_mask; /* Mask of the bits of bus address this
325 device implements. Normally this is
326 0xffffffff. You only need to change
327 this if your device has broken DMA
328 or supports 64-bit transfers. */
329
330 /* device is compatible with these IDs */
331 unsigned short vendor_compatible[DEVICE_COUNT_COMPATIBLE];
332 unsigned short device_compatible[DEVICE_COUNT_COMPATIBLE];
333
334 /*
335 * Instead of touching interrupt line and base address registers
336 * directly, use the values stored here. They might be different!
337 */
338 unsigned int irq;
339 struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */
340 struct resource dma_resource[DEVICE_COUNT_DMA];
341 struct resource irq_resource[DEVICE_COUNT_IRQ];
342
343 char name[80]; /* device name */
344 char slot_name[8]; /* slot name */
345 int active; /* ISAPnP: device is active */
346 int ro; /* ISAPnP: read only */
347 unsigned short regs; /* ISAPnP: supported registers */
348
349 int (*prepare)(struct pci_dev *dev); /* ISAPnP hooks */
350 int (*activate)(struct pci_dev *dev);
351 int (*deactivate)(struct pci_dev *dev);
352 };
353
354 #define pci_dev_g(n) list_entry(n, struct pci_dev, global_list)
355 #define pci_dev_b(n) list_entry(n, struct pci_dev, bus_list)
356
357 /*
358 * For PCI devices, the region numbers are assigned this way:
359 *
360 * 0-5 standard PCI regions
361 * 6 expansion ROM
362 * 7-10 bridges: address space assigned to buses behind the bridge
363 */
364
365 #define PCI_ROM_RESOURCE 6
366 #define PCI_BRIDGE_RESOURCES 7
367 #define PCI_NUM_RESOURCES 11
368
369 #define PCI_REGION_FLAG_MASK 0x0f /* These bits of resource flags tell us the PCI region flags */
370
371 struct pci_bus {
372 struct list_head node; /* node in list of buses */
373 struct pci_bus *parent; /* parent bus this bridge is on */
374 struct list_head children; /* list of child buses */
375 struct list_head devices; /* list of devices on this bus */
376 struct pci_dev *self; /* bridge device as seen by parent */
377 struct resource *resource[4]; /* address space routed to this bus */
378
379 struct pci_ops *ops; /* configuration access functions */
380 void *sysdata; /* hook for sys-specific extension */
381 struct proc_dir_entry *procdir; /* directory entry in /proc/bus/pci */
382
383 unsigned char number; /* bus number */
384 unsigned char primary; /* number of primary bridge */
385 unsigned char secondary; /* number of secondary bridge */
386 unsigned char subordinate; /* max number of subordinate buses */
387
388 char name[48];
389 unsigned short vendor;
390 unsigned short device;
391 unsigned int serial; /* serial number */
392 unsigned char pnpver; /* Plug & Play version */
393 unsigned char productver; /* product version */
394 unsigned char checksum; /* if zero - checksum passed */
395 unsigned char pad1;
396 };
397
398 #define pci_bus_b(n) list_entry(n, struct pci_bus, node)
399
400 extern struct list_head pci_root_buses; /* list of all known PCI buses */
401 extern struct list_head pci_devices; /* list of all devices */
402
403 /*
404 * Error values that may be returned by PCI functions.
405 */
406 #define PCIBIOS_SUCCESSFUL 0x00
407 #define PCIBIOS_FUNC_NOT_SUPPORTED 0x81
408 #define PCIBIOS_BAD_VENDOR_ID 0x83
409 #define PCIBIOS_DEVICE_NOT_FOUND 0x86
410 #define PCIBIOS_BAD_REGISTER_NUMBER 0x87
411 #define PCIBIOS_SET_FAILED 0x88
412 #define PCIBIOS_BUFFER_TOO_SMALL 0x89
413
414 /* Low-level architecture-dependent routines */
415
416 struct pci_ops {
417 int (*read_byte)(struct pci_dev *, int where, u8 *val);
418 int (*read_word)(struct pci_dev *, int where, u16 *val);
419 int (*read_dword)(struct pci_dev *, int where, u32 *val);
420 int (*write_byte)(struct pci_dev *, int where, u8 val);
421 int (*write_word)(struct pci_dev *, int where, u16 val);
422 int (*write_dword)(struct pci_dev *, int where, u32 val);
423 };
424
425 struct pbus_set_ranges_data
426 {
427 int found_vga;
428 unsigned long io_start, io_end;
429 unsigned long mem_start, mem_end;
430 };
431
432 void pcibios_init(void);
433 void pcibios_fixup_bus(struct pci_bus *);
434 int pcibios_enable_device(struct pci_dev *);
435 char *pcibios_setup (char *str);
436
437 /* Used only when drivers/pci/setup.c is used */
438 void pcibios_align_resource(void *, struct resource *, unsigned long);
439 void pcibios_update_resource(struct pci_dev *, struct resource *,
440 struct resource *, int);
441 void pcibios_update_irq(struct pci_dev *, int irq);
442 void pcibios_fixup_pbus_ranges(struct pci_bus *, struct pbus_set_ranges_data *);
443
444 /* Backward compatibility, don't use in new code! */
445
446 int pcibios_present(void);
447 #define pci_present pcibios_present
448 int pcibios_read_config_byte (unsigned char bus, unsigned char dev_fn,
449 unsigned char where, unsigned char *val);
450 int pcibios_read_config_word (unsigned char bus, unsigned char dev_fn,
451 unsigned char where, unsigned short *val);
452 int pcibios_read_config_dword (unsigned char bus, unsigned char dev_fn,
453 unsigned char where, unsigned int *val);
454 int pcibios_write_config_byte (unsigned char bus, unsigned char dev_fn,
455 unsigned char where, unsigned char val);
456 int pcibios_write_config_word (unsigned char bus, unsigned char dev_fn,
457 unsigned char where, unsigned short val);
458 int pcibios_write_config_dword (unsigned char bus, unsigned char dev_fn,
459 unsigned char where, unsigned int val);
460 int pcibios_find_class (unsigned int class_code, unsigned short index, unsigned char *bus, unsigned char *dev_fn);
461 int pcibios_find_device (unsigned short vendor, unsigned short dev_id,
462 unsigned short index, unsigned char *bus,
463 unsigned char *dev_fn);
464
465 /* Generic PCI functions used internally */
466
467 void pci_init(void);
468 int pci_bus_exists(const struct list_head *list, int nr);
469 struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata);
470 struct pci_bus *pci_alloc_primary_bus(int bus);
471 struct pci_dev *pci_scan_slot(struct pci_dev *temp);
472 int pci_proc_attach_device(struct pci_dev *dev);
473 int pci_proc_detach_device(struct pci_dev *dev);
474 void pci_name_device(struct pci_dev *dev);
475 char *pci_class_name(u32 class);
476 void pci_read_bridge_bases(struct pci_bus *child);
477 struct resource *pci_find_parent_resource(const struct pci_dev *dev, struct resource *res);
478 int pci_setup_device(struct pci_dev *dev);
479 int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge);
480
481 /* Generic PCI functions exported to card drivers */
482
483 struct pci_dev *pci_find_device (unsigned int vendor, unsigned int device, const struct pci_dev *from);
484 struct pci_dev *pci_find_subsys (unsigned int vendor, unsigned int device,
485 unsigned int ss_vendor, unsigned int ss_device,
486 const struct pci_dev *from);
487 struct pci_dev *pci_find_class (unsigned int class, const struct pci_dev *from);
488 struct pci_dev *pci_find_slot (unsigned int bus, unsigned int devfn);
489 int pci_find_capability (struct pci_dev *dev, int cap);
490
491 #define PCI_ANY_ID (~0)
492
493 int pci_read_config_byte(struct pci_dev *dev, int where, u8 *val);
494 int pci_read_config_word(struct pci_dev *dev, int where, u16 *val);
495 int pci_read_config_dword(struct pci_dev *dev, int where, u32 *val);
496 int pci_write_config_byte(struct pci_dev *dev, int where, u8 val);
497 int pci_write_config_word(struct pci_dev *dev, int where, u16 val);
498 int pci_write_config_dword(struct pci_dev *dev, int where, u32 val);
499
500 int pci_enable_device(struct pci_dev *dev);
501 void pci_set_master(struct pci_dev *dev);
502 int pci_set_power_state(struct pci_dev *dev, int state);
503 int pci_assign_resource(struct pci_dev *dev, int i);
504
505 #define pci_for_each_dev(dev) \
506 for(dev = pci_dev_g(pci_devices.next); dev != pci_dev_g(&pci_devices); dev = pci_dev_g(dev->global_list.next))
507
508 #define pci_for_each_dev_reverse(dev) \
509 for(dev = pci_dev_g(pci_devices.prev); dev != pci_dev_g(&pci_devices); dev = pci_dev_g(dev->global_list.prev))
510
511 /* Helper functions for low-level code (drivers/pci/setup.c) */
512
513 int pci_claim_resource(struct pci_dev *, int);
514 void pci_assign_unassigned_resources(void);
515 void pdev_assign_unassigned_resources(struct pci_dev *dev);
516 void pci_set_bus_ranges(void);
517 void pci_fixup_irqs(u8 (*)(struct pci_dev *, u8 *),
518 int (*)(struct pci_dev *, u8, u8));
519
520 /* New-style probing supporting hot-pluggable devices */
521
522 struct pci_device_id {
523 unsigned int vendor, device; /* Vendor and device ID or PCI_ANY_ID */
524 unsigned int subvendor, subdevice; /* Subsystem ID's or PCI_ANY_ID */
525 unsigned int class, class_mask; /* (class,subclass,prog-if) triplet */
526 unsigned long driver_data; /* Data private to the driver */
527 };
528
529 struct pci_driver {
530 struct list_head node;
531 char *name;
532 const struct pci_device_id *id_table; /* NULL if wants all devices */
533 int (*probe)(struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */
534 void (*remove)(struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */
535 void (*suspend)(struct pci_dev *dev); /* Device suspended */
536 void (*resume)(struct pci_dev *dev); /* Device woken up */
537 };
538
539 int pci_register_driver(struct pci_driver *);
540 void pci_unregister_driver(struct pci_driver *);
541 void pci_insert_device(struct pci_dev *, struct pci_bus *);
542 void pci_remove_device(struct pci_dev *);
543 struct pci_driver *pci_dev_driver(const struct pci_dev *);
544 const struct pci_device_id *pci_match_device(const struct pci_device_id *ids, const struct pci_dev *dev);
545
546 /* Include architecture-dependent settings and functions */
547
548 #include <asm/pci.h>
549
550 /*
551 * If the system does not have PCI, clearly these return errors. Define
552 * these as simple inline functions to avoid hair in drivers.
553 */
554
555 #ifndef CONFIG_PCI
556 extern inline int pcibios_present(void) { return 0; }
557 extern inline int pcibios_find_class (unsigned int class_code, unsigned short index, unsigned char *bus, unsigned char *dev_fn)
558 { return PCIBIOS_DEVICE_NOT_FOUND; }
559
560 #define _PCI_NOP(o,s,t) \
561 extern inline int pcibios_##o##_config_##s## (u8 bus, u8 dfn, u8 where, t val) \
562 { return PCIBIOS_FUNC_NOT_SUPPORTED; } \
563 extern inline int pci_##o##_config_##s## (struct pci_dev *dev, int where, t val) \
564 { return PCIBIOS_FUNC_NOT_SUPPORTED; }
565 #define _PCI_NOP_ALL(o,x) _PCI_NOP(o,byte,u8 x) \
566 _PCI_NOP(o,word,u16 x) \
567 _PCI_NOP(o,dword,u32 x)
568 _PCI_NOP_ALL(read, *)
569 _PCI_NOP_ALL(write,)
570
571 extern inline struct pci_dev *pci_find_device(unsigned int vendor, unsigned int device, const struct pci_dev *from)
572 { return NULL; }
573
574 extern inline struct pci_dev *pci_find_class(unsigned int class, const struct pci_dev *from)
575 { return NULL; }
576
577 extern inline struct pci_dev *pci_find_slot(unsigned int bus, unsigned int devfn)
578 { return NULL; }
579
580 extern inline struct pci_dev *pci_find_subsys(unsigned int vendor, unsigned int device,
581 unsigned int ss_vendor, unsigned int ss_device, const struct pci_dev *from)
582 { return NULL; }
583
584 extern inline void pci_set_master(struct pci_dev *dev) { }
585 extern inline int pci_enable_device(struct pci_dev *dev) { return -EIO; }
586 extern inline int pci_module_init(struct pci_driver *drv) { return -ENODEV; }
587 extern inline int pci_assign_resource(struct pci_dev *dev, int i) { return -EBUSY;}
588 extern inline int pci_register_driver(struct pci_driver *drv) { return 0;}
589 extern inline void pci_unregister_driver(struct pci_driver *drv) { }
590 extern inline int scsi_to_pci_dma_dir(unsigned char scsi_dir) { return scsi_dir; }
591 extern inline int pci_find_capability (struct pci_dev *dev, int cap) {return 0; }
592
593 #else
594
595 /*
596 * a helper function which helps ensure correct pci_driver
597 * setup and cleanup for commonly-encountered hotplug/modular cases
598 *
599 * This MUST stay in a header, as it checks for -DMODULE
600 */
601 extern inline int pci_module_init(struct pci_driver *drv)
602 {
603 int rc = pci_register_driver (drv);
604
605 if (rc > 0)
606 return 0;
607
608 /* iff CONFIG_HOTPLUG and built into kernel, we should
609 * leave the driver around for future hotplug events.
610 * For the module case, a hotplug daemon of some sort
611 * should load a module in response to an insert event. */
612 #if defined(CONFIG_HOTPLUG) && !defined(MODULE)
613 if (rc == 0)
614 return 0;
615 #endif
616
617 /* if we get here, we need to clean up pci driver instance
618 * and return some sort of error */
619 pci_unregister_driver (drv);
620
621 return -ENODEV;
622 }
623
624 #endif /* !CONFIG_PCI */
625
626 /* these helpers provide future and backwards compatibility
627 * for accessing popular PCI BAR info */
628 #define pci_resource_start(dev,bar) ((dev)->resource[(bar)].start)
629 #define pci_resource_end(dev,bar) ((dev)->resource[(bar)].end)
630 #define pci_resource_flags(dev,bar) ((dev)->resource[(bar)].flags)
631 #define pci_resource_len(dev,bar) \
632 ((pci_resource_start((dev),(bar)) == 0 && \
633 pci_resource_end((dev),(bar)) == \
634 pci_resource_start((dev),(bar))) ? 0 : \
635 \
636 (pci_resource_end((dev),(bar)) - \
637 pci_resource_start((dev),(bar)) + 1))
638
639 /*
640 * The world is not perfect and supplies us with broken PCI devices.
641 * For at least a part of these bugs we need a work-around, so both
642 * generic (drivers/pci/quirks.c) and per-architecture code can define
643 * fixup hooks to be called for particular buggy devices.
644 */
645
646 struct pci_fixup {
647 int pass;
648 u16 vendor, device; /* You can use PCI_ANY_ID here of course */
649 void (*hook)(struct pci_dev *dev);
650 };
651
652 extern struct pci_fixup pcibios_fixups[];
653
654 #define PCI_FIXUP_HEADER 1 /* Called immediately after reading configuration header */
655 #define PCI_FIXUP_FINAL 2 /* Final phase of device fixups */
656
657 void pci_fixup_device(int pass, struct pci_dev *dev);
658
659 extern int pci_pci_problems;
660 #define PCIPCI_FAIL 1
661 #define PCIPCI_TRITON 2
662 #define PCIPCI_NATOMA 4
663
664 #endif /* __KERNEL__ */
665 #endif /* LINUX_PCI_H */
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