arch/arm/kernel/bios32.c

   1 /*
   2  * arch/arm/kernel/bios32.c
   3  *
   4  * PCI bios-type initialisation for PCI machines
   5  *
   6  * Bits taken from various places.
   7  */
   8 #include <linux/config.h>
   9 #include <linux/kernel.h>
  10 #include <linux/pci.h>
  11 #include <linux/init.h>
  12
  13 #include <asm/page.h> /* for BUG() */
  14 #include <asm/irq.h>
  15 #include <asm/mach-types.h>
  16 #include <asm/mach/pci.h>
  17
  18 static int debug_pci;
  19 int have_isa_bridge;
  20
  21 void pcibios_report_status(u_int status_mask, int warn)
  22 {
  23         struct pci_dev *dev;
  24
  25         pci_for_each_dev(dev) {
  26                 u16 status;
  27
  28                 /*
  29                  * ignore host bridge - we handle
  30                  * that separately
  31                  */
  32                 if (dev->bus->number == 0 && dev->devfn == 0)
  33                         continue;
  34
  35                 pci_read_config_word(dev, PCI_STATUS, &status);
  36
  37                 status &= status_mask;
  38                 if (status == 0)
  39                         continue;
  40
  41                 /* clear the status errors */
  42                 pci_write_config_word(dev, PCI_STATUS, status);
  43
  44                 if (warn)
  45                         printk("(%02x:%02x.%d: %04X) ", dev->bus->number,
  46                                 PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn),
  47                                 status);
  48         }
  49 }
  50
  51 /*
  52  * We don't use this to fix the device, but initialisation of it.
  53  * It's not the correct use for this, but it works.
  54  * Note that the arbiter/ISA bridge appears to be buggy, specifically in
  55  * the following area:
  56  * 1. park on CPU
  57  * 2. ISA bridge ping-pong
  58  * 3. ISA bridge master handling of target RETRY
  59  *
  60  * Bug 3 is responsible for the sound DMA grinding to a halt.  We now
  61  * live with bug 2.
  62  */
  63 static void __init pci_fixup_83c553(struct pci_dev *dev)
  64 {
  65         /*
  66          * Set memory region to start at address 0, and enable IO
  67          */
  68         pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_SPACE_MEMORY);
  69         pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_IO);
  70
  71         dev->resource[0].end -= dev->resource[0].start;
  72         dev->resource[0].start = 0;
  73
  74         /*
  75          * All memory requests from ISA to be channelled to PCI
  76          */
  77         pci_write_config_byte(dev, 0x48, 0xff);
  78
  79         /*
  80          * Enable ping-pong on bus master to ISA bridge transactions.
  81          * This improves the sound DMA substantially.  The fixed
  82          * priority arbiter also helps (see below).
  83          */
  84         pci_write_config_byte(dev, 0x42, 0x01);
  85
  86         /*
  87          * Enable PCI retry
  88          */
  89         pci_write_config_byte(dev, 0x40, 0x22);
  90
  91         /*
  92          * We used to set the arbiter to "park on last master" (bit
  93          * 1 set), but unfortunately the CyberPro does not park the
  94          * bus.  We must therefore park on CPU.  Unfortunately, this
  95          * may trigger yet another bug in the 553.
  96          */
  97         pci_write_config_byte(dev, 0x83, 0x02);
  98
  99         /*
 100          * Make the ISA DMA request lowest priority, and disable
 101          * rotating priorities completely.
 102          */
 103         pci_write_config_byte(dev, 0x80, 0x11);
 104         pci_write_config_byte(dev, 0x81, 0x00);
 105
 106         /*
 107          * Route INTA input to IRQ 11, and set IRQ11 to be level
 108          * sensitive.
 109          */
 110         pci_write_config_word(dev, 0x44, 0xb000);
 111         outb(0x08, 0x4d1);
 112 }
 113
 114 static void __init pci_fixup_unassign(struct pci_dev *dev)
 115 {
 116         dev->resource[0].end -= dev->resource[0].start;
 117         dev->resource[0].start = 0;
 118 }
 119
 120 /*
 121  * Prevent the PCI layer from seeing the resources
 122  * allocated to this device.  These resources are
 123  * of no consequence to the PCI layer (they are
 124  * handled elsewhere).
 125  */
 126 static void __init pci_fixup_disable(struct pci_dev *dev)
 127 {
 128         int i;
 129
 130         for (i = 0; i < PCI_NUM_RESOURCES; i++) {
 131                 dev->resource[i].start = 0;
 132                 dev->resource[i].end   = 0;
 133                 dev->resource[i].flags = 0;
 134         }
 135 }
 136
 137 /*
 138  * PCI IDE controllers use non-standard I/O port
 139  * decoding, respect it.
 140  */
 141 static void __init pci_fixup_ide_bases(struct pci_dev *dev)
 142 {
 143         struct resource *r;
 144         int i;
 145
 146         if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE)
 147                 return;
 148
 149         for (i = 0; i < PCI_NUM_RESOURCES; i++) {
 150                 r = dev->resource + i;
 151                 if ((r->start & ~0x80) == 0x374) {
 152                         r->start |= 2;
 153                         r->end = r->start;
 154                 }
 155         }
 156 }
 157
 158 /*
 159  * Put the DEC21142 to sleep
 160  */
 161 static void __init pci_fixup_dec21142(struct pci_dev *dev)
 162 {
 163         pci_write_config_dword(dev, 0x40, 0x80000000);
 164 }
 165
 166 struct pci_fixup pcibios_fixups[] = {
 167         {
 168                 PCI_FIXUP_HEADER,
 169                 PCI_VENDOR_ID_DEC,      PCI_DEVICE_ID_DEC_21285,
 170                 pci_fixup_disable
 171         }, {
 172                 PCI_FIXUP_HEADER,
 173                 PCI_VENDOR_ID_WINBOND,  PCI_DEVICE_ID_WINBOND_83C553,
 174                 pci_fixup_83c553
 175         }, {
 176                 PCI_FIXUP_HEADER,
 177                 PCI_VENDOR_ID_WINBOND2, PCI_DEVICE_ID_WINBOND2_89C940F,
 178                 pci_fixup_unassign
 179         }, {
 180                 PCI_FIXUP_HEADER,
 181                 PCI_ANY_ID,             PCI_ANY_ID,
 182                 pci_fixup_ide_bases
 183         }, {
 184                 PCI_FIXUP_HEADER,
 185                 PCI_VENDOR_ID_DEC,      PCI_DEVICE_ID_DEC_21142,
 186                 pci_fixup_dec21142
 187         }, { 0 }
 188 };
 189
 190 /*
 191  * Allocate resources for all PCI devices that have been enabled.
 192  * We need to do that before we try to fix up anything.
 193  */
 194 static void __init pcibios_claim_resources(void)
 195 {
 196         struct pci_dev *dev;
 197         int idx;
 198
 199         pci_for_each_dev(dev) {
 200                 for (idx = 0; idx < PCI_NUM_RESOURCES; idx++)
 201                         if (dev->resource[idx].flags &&
 202                             dev->resource[idx].start)
 203                                 pci_claim_resource(dev, idx);
 204         }
 205 }
 206
 207 void __init
 208 pcibios_update_resource(struct pci_dev *dev, struct resource *root,
 209                         struct resource *res, int resource)
 210 {
 211         u32 val, check;
 212         int reg;
 213
 214         if (debug_pci)
 215                 printk("PCI: Assigning %3s %08lx to %s\n",
 216                         res->flags & IORESOURCE_IO ? "IO" : "MEM",
 217                         res->start, dev->name);
 218
 219         val = res->start | (res->flags & PCI_REGION_FLAG_MASK);
 220         if (resource < 6) {
 221                 reg = PCI_BASE_ADDRESS_0 + 4*resource;
 222         } else if (resource == PCI_ROM_RESOURCE) {
 223                 res->flags |= PCI_ROM_ADDRESS_ENABLE;
 224                 val |= PCI_ROM_ADDRESS_ENABLE;
 225                 reg = dev->rom_base_reg;
 226         } else {
 227                 /* Somebody might have asked allocation of a
 228                  * non-standard resource.
 229                  */
 230                 return;
 231         }
 232         pci_write_config_dword(dev, reg, val);
 233         pci_read_config_dword(dev, reg, &check);
 234         if ((val ^ check) & ((val & PCI_BASE_ADDRESS_SPACE_IO) ?
 235             PCI_BASE_ADDRESS_IO_MASK : PCI_BASE_ADDRESS_MEM_MASK)) {
 236                 printk(KERN_ERR "PCI: Error while updating region "
 237                         "%s/%d (%08x != %08x)\n", dev->slot_name,
 238                         resource, val, check);
 239         }
 240 }
 241
 242 void __init pcibios_update_irq(struct pci_dev *dev, int irq)
 243 {
 244         if (debug_pci)
 245                 printk("PCI: Assigning IRQ %02d to %s\n", irq, dev->name);
 246         pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
 247 }
 248
 249 /**
 250  * pcibios_fixup_bus - Called after each bus is probed, but before its children
 251  * are examined.
 252  */
 253 void __init pcibios_fixup_bus(struct pci_bus *bus)
 254 {
 255         struct list_head *walk = &bus->devices;
 256         struct arm_pci_sysdata *sysdata =
 257                         (struct arm_pci_sysdata *)bus->sysdata;
 258         struct arm_bus_sysdata *busdata;
 259
 260         if (bus->number < MAX_NR_BUS)
 261                 busdata = sysdata->bus + bus->number;
 262         else
 263                 BUG();
 264
 265         busdata->max_lat = 255;
 266
 267         /*
 268          * Walk the devices on this bus, working out what we can
 269          * and can't support.
 270          */
 271         for (walk = walk->next; walk != &bus->devices; walk = walk->next) {
 272                 struct pci_dev *dev = pci_dev_b(walk);
 273                 u16 status;
 274                 u8 max_lat, min_gnt;
 275
 276                 pci_read_config_word(dev, PCI_STATUS, &status);
 277
 278                 /*
 279                  * If this device does not support fast back to back
 280                  * transfers, the bus as a whole cannot support them.
 281                  */
 282                 if (!(status & PCI_STATUS_FAST_BACK))
 283                         busdata->features &= ~PCI_COMMAND_FAST_BACK;
 284
 285                 /*
 286                  * If we encounter a CyberPro 2000, then we disable
 287                  * SERR and PERR reporting - this chip doesn't drive the
 288                  * parity line correctly.
 289                  */
 290                 if (dev->vendor == PCI_VENDOR_ID_INTERG &&
 291                     dev->device == PCI_DEVICE_ID_INTERG_2000)
 292                         busdata->features &= ~(PCI_COMMAND_SERR |
 293                                                PCI_COMMAND_PARITY);
 294
 295                 /*
 296                  * Calculate the maximum devsel latency.
 297                  */
 298                 if (busdata->maxdevsel < (status & PCI_STATUS_DEVSEL_MASK))
 299                         busdata->maxdevsel = (status & PCI_STATUS_DEVSEL_MASK);
 300
 301                 /*
 302                  * If this device is an ISA bridge, set the have_isa_bridge
 303                  * flag.  We will then go looking for things like keyboard,
 304                  * etc
 305                  */
 306                 if (dev->class >> 8 == PCI_CLASS_BRIDGE_ISA ||
 307                     dev->class >> 8 == PCI_CLASS_BRIDGE_EISA)
 308                         have_isa_bridge = !0;
 309
 310                 /*
 311                  * Calculate the maximum latency on this bus.  Note
 312                  * that we ignore any device which reports its max
 313                  * latency is the same as its use.
 314                  */
 315                 pci_read_config_byte(dev, PCI_MAX_LAT, &max_lat);
 316                 pci_read_config_byte(dev, PCI_MIN_GNT, &min_gnt);
 317                 if (max_lat && max_lat != min_gnt && max_lat < busdata->max_lat)
 318                         busdata->max_lat = max_lat;
 319         }
 320
 321         /*
 322          * Now walk the devices again, this time setting them up.
 323          */
 324         walk = &bus->devices;
 325         for (walk = walk->next; walk != &bus->devices; walk = walk->next) {
 326                 struct pci_dev *dev = pci_dev_b(walk);
 327                 u16 cmd;
 328                 u8 min_gnt, latency;
 329
 330                 /*
 331                  * Calculate this masters latency timer value.
 332                  * This is rather primitive - it does not take
 333                  * account of the number of masters in a system
 334                  * wanting to use the bus.
 335                  */
 336                 pci_read_config_byte(dev, PCI_MIN_GNT, &min_gnt);
 337                 if (min_gnt) {
 338                         if (min_gnt > busdata->max_lat)
 339                                 min_gnt = busdata->max_lat;
 340
 341                         latency = (int)min_gnt * 25 / 3;
 342                 } else
 343                         latency = 32; /* 1us */
 344
 345                 pci_write_config_byte(dev, PCI_LATENCY_TIMER, latency);
 346
 347                 /*
 348                  * Set the cache line size to 32 bytes.
 349                  * Also, set system error enable, parity error enable.
 350                  * Disable ROM.
 351                  */
 352                 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 8);
 353                 pci_read_config_word(dev, PCI_COMMAND, &cmd);
 354
 355                 cmd |= busdata->features;
 356
 357                 pci_write_config_word(dev, PCI_COMMAND, cmd);
 358                 pci_read_config_word(dev, PCI_COMMAND, &cmd);
 359                 pci_write_config_dword(dev, PCI_ROM_ADDRESS, 0);
 360         }
 361 }
 362
 363 void __init
 364 pcibios_fixup_pbus_ranges(struct pci_bus *bus, struct pbus_set_ranges_data *ranges)
 365 {
 366         ranges->io_start -= bus->resource[0]->start;
 367         ranges->io_end -= bus->resource[0]->start;
 368         ranges->mem_start -= bus->resource[1]->start;
 369         ranges->mem_end -= bus->resource[1]->start;
 370 }
 371
 372 u8 __init no_swizzle(struct pci_dev *dev, u8 *pin)
 373 {
 374         return 0;
 375 }
 376
 377 extern struct hw_pci ebsa285_pci;
 378 extern struct hw_pci cats_pci;
 379 extern struct hw_pci netwinder_pci;
 380 extern struct hw_pci personal_server_pci;
 381 extern struct hw_pci ftv_pci;
 382 extern struct hw_pci integrator_pci;
 383
 384 void __init pcibios_init(void)
 385 {
 386         struct hw_pci *hw_pci = NULL;
 387         struct arm_pci_sysdata sysdata;
 388         int i;
 389
 390         do {
 391 #ifdef CONFIG_ARCH_EBSA285
 392                 if (machine_is_ebsa285()) {
 393                         hw_pci = &ebsa285_pci;
 394                         break;
 395                 }
 396 #endif
 397 #ifdef CONFIG_ARCH_CATS
 398                 if (machine_is_cats()) {
 399                         hw_pci = &cats_pci;
 400                         break;
 401                 }
 402 #endif
 403 #ifdef CONFIG_ARCH_NETWINDER
 404                 if (machine_is_netwinder()) {
 405                         hw_pci = &netwinder_pci;
 406                         break;
 407                 }
 408 #endif
 409 #ifdef CONFIG_ARCH_PERSONAL_SERVER
 410                 if (machine_is_personal_server()) {
 411                         hw_pci = &personal_server_pci;
 412                         break;
 413                 }
 414 #endif
 415 #ifdef CONFIG_ARCH_NEXUSPCI
 416                 if (machine_is_nexuspci()) {
 417                         hw_pci = &ftv_pci;
 418                         break;
 419                 }
 420 #endif
 421 #ifdef CONFIG_ARCH_INTEGRATOR
 422                 if (machine_is_integrator()) {
 423                         hw_pci = &integrator_pci;
 424                         break;
 425                 }
 426 #endif
 427         } while (0);
 428
 429         if (hw_pci == NULL)
 430                 return;
 431
 432         for (i = 0; i < MAX_NR_BUS; i++) {
 433                 sysdata.bus[i].features  = PCI_COMMAND_FAST_BACK |
 434                                            PCI_COMMAND_SERR |
 435                                            PCI_COMMAND_PARITY;
 436                 sysdata.bus[i].maxdevsel = PCI_STATUS_DEVSEL_FAST;
 437         }
 438
 439         /*
 440          * Set up the host bridge, and scan the bus.
 441          */
 442         hw_pci->init(&sysdata);
 443
 444         /*
 445          * Other architectures don't seem to do this... should we?
 446          */
 447         pcibios_claim_resources();
 448
 449         /*
 450          * Assign any unassigned resources.
 451          */
 452         pci_assign_unassigned_resources();
 453         pci_fixup_irqs(hw_pci->swizzle, hw_pci->map_irq);
 454         pci_set_bus_ranges();
 455 }
 456
 457 char * __init pcibios_setup(char *str)
 458 {
 459         if (!strcmp(str, "debug")) {
 460                 debug_pci = 1;
 461                 return NULL;
 462         }
 463         return str;
 464 }
 465
 466 void pcibios_align_resource(void *data, struct resource *res, unsigned long size)
 467 {
 468 }
 469
 470 /**
 471  * pcibios_set_master - Setup device for bus mastering.
 472  * @dev: PCI device to be setup
 473  */
 474 void pcibios_set_master(struct pci_dev *dev)
 475 {
 476 }
 477
 478 /**
 479  * pcibios_enable_device - Enable I/O and memory.
 480  * @dev: PCI device to be enabled
 481  */
 482 int pcibios_enable_device(struct pci_dev *dev)
 483 {
 484         u16 cmd, old_cmd;
 485         int idx;
 486         struct resource *r;
 487
 488         pci_read_config_word(dev, PCI_COMMAND, &cmd);
 489         old_cmd = cmd;
 490         for (idx = 0; idx < 6; idx++) {
 491                 r = dev->resource + idx;
 492                 if (!r->start && r->end) {
 493                         printk(KERN_ERR "PCI: Device %s not available because"
 494                                " of resource collisions\n", dev->slot_name);
 495                         return -EINVAL;
 496                 }
 497                 if (r->flags & IORESOURCE_IO)
 498                         cmd |= PCI_COMMAND_IO;
 499                 if (r->flags & IORESOURCE_MEM)
 500                         cmd |= PCI_COMMAND_MEMORY;
 501         }
 502         if (cmd != old_cmd) {
 503                 printk("PCI: enabling device %s (%04x -> %04x)\n",
 504                        dev->slot_name, old_cmd, cmd);
 505                 pci_write_config_word(dev, PCI_COMMAND, cmd);
 506         }
 507         return 0;
 508 }