arch/alpha/kernel/pci.c

   1 /*
   2  *      linux/arch/alpha/kernel/pci.c
   3  *
   4  * Extruded from code written by
   5  *      Dave Rusling (david.rusling@reo.mts.dec.com)
   6  *      David Mosberger (davidm@cs.arizona.edu)
   7  */
   8
   9 /* 2.3.x PCI/resources, 1999 Andrea Arcangeli <andrea@suse.de> */
  10
  11 #include <linux/string.h>
  12 #include <linux/pci.h>
  13 #include <linux/init.h>
  14 #include <linux/ioport.h>
  15 #include <linux/kernel.h>
  16 #include <linux/bootmem.h>
  17 #include <asm/machvec.h>
  18
  19 #include "proto.h"
  20 #include "pci_impl.h"
  21
  22
  23 /*
  24  * Some string constants used by the various core logics.
  25  */
  26
  27 const char *const pci_io_names[] = {
  28         "PCI IO bus 0", "PCI IO bus 1", "PCI IO bus 2", "PCI IO bus 3"
  29 };
  30
  31 const char *const pci_mem_names[] = {
  32         "PCI mem bus 0", "PCI mem bus 1", "PCI mem bus 2", "PCI mem bus 3"
  33 };
  34
  35 const char pci_hae0_name[] = "HAE0";
  36
  37
  38 /*
  39  * The PCI controler list.
  40  */
  41
  42 struct pci_controler *hose_head, **hose_tail = &hose_head;
  43
  44 /*
  45  * Quirks.
  46  */
  47
  48 static void __init
  49 quirk_eisa_bridge(struct pci_dev *dev)
  50 {
  51         dev->class = PCI_CLASS_BRIDGE_EISA;
  52 }
  53
  54 static void __init
  55 quirk_isa_bridge(struct pci_dev *dev)
  56 {
  57         dev->class = PCI_CLASS_BRIDGE_ISA;
  58 }
  59
  60 static void __init
  61 quirk_ali_ide_ports(struct pci_dev *dev)
  62 {
  63         if (dev->resource[0].end == 0xffff)
  64                 dev->resource[0].end = dev->resource[0].start + 7;
  65         if (dev->resource[2].end == 0xffff)
  66                 dev->resource[2].end = dev->resource[2].start + 7;
  67         if (dev->resource[3].end == 0xffff)
  68                 dev->resource[3].end = dev->resource[3].start + 7;
  69 }
  70
  71 static void __init
  72 quirk_vga_enable_rom(struct pci_dev *dev)
  73 {
  74         /* If it's a VGA, enable its BIOS ROM at C0000.
  75            But if its a Cirrus 543x/544x DISABLE it, since
  76            enabling ROM disables the memory... */
  77         if ((dev->class >> 8) == PCI_CLASS_DISPLAY_VGA &&
  78             /* But if its a Cirrus 543x/544x DISABLE it */
  79             (dev->vendor != PCI_VENDOR_ID_CIRRUS ||
  80              (dev->device < 0x00a0) || (dev->device > 0x00ac)))
  81         {
  82                 u32 reg;
  83
  84                 pci_read_config_dword(dev, dev->rom_base_reg, &reg);
  85                 reg |= PCI_ROM_ADDRESS_ENABLE;
  86                 pci_write_config_dword(dev, dev->rom_base_reg, reg);
  87                 dev->resource[PCI_ROM_RESOURCE].flags |= PCI_ROM_ADDRESS_ENABLE;
  88         }
  89 }
  90
  91 struct pci_fixup pcibios_fixups[] __initdata = {
  92         { PCI_FIXUP_HEADER, PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82375,
  93           quirk_eisa_bridge },
  94         { PCI_FIXUP_HEADER, PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82378,
  95           quirk_isa_bridge },
  96         { PCI_FIXUP_HEADER, PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M5229,
  97           quirk_ali_ide_ports },
  98         { PCI_FIXUP_FINAL, PCI_ANY_ID, PCI_ANY_ID, quirk_vga_enable_rom },
  99         { 0 }
 100 };
 101
 102 #define MAX(val1, val2)         ((val1) > (val2) ? (val1) : (val2))
 103 #define ALIGN(val,align)        (((val) + ((align) - 1)) & ~((align) - 1))
 104 #define KB                      1024
 105 #define MB                      (1024*KB)
 106 #define GB                      (1024*MB)
 107
 108 void
 109 pcibios_align_resource(void *data, struct resource *res, unsigned long size)
 110 {
 111         struct pci_dev * dev = data;
 112         unsigned long alignto;
 113         unsigned long start = res->start;
 114
 115         if (res->flags & IORESOURCE_IO) {
 116                 /*
 117                  * Aligning to 0x800 rather than the minimum base of
 118                  * 0x400 is an attempt to avoid having devices in
 119                  * any 0x?C?? range, which is where the de4x5 driver
 120                  * probes for EISA cards.
 121                  *
 122                  * Adaptecs, especially, resent such intrusions.
 123                  */
 124                 alignto = MAX(0x800, size);
 125                 start = ALIGN(start, alignto);
 126         }
 127         else if (res->flags & IORESOURCE_MEM) {
 128                 /*
 129                  * The following holds at least for the Low Cost
 130                  * Alpha implementation of the PCI interface:
 131                  *
 132                  * In sparse memory address space, the first
 133                  * octant (16MB) of every 128MB segment is
 134                  * aliased to the very first 16 MB of the
 135                  * address space (i.e., it aliases the ISA
 136                  * memory address space).  Thus, we try to
 137                  * avoid allocating PCI devices in that range.
 138                  * Can be allocated in 2nd-7th octant only.
 139                  * Devices that need more than 112MB of
 140                  * address space must be accessed through
 141                  * dense memory space only!
 142                  */
 143
 144                 /* Align to multiple of size of minimum base.  */
 145                 alignto = MAX(0x1000, size);
 146                 start = ALIGN(start, alignto);
 147                 if (size <= 7 * 16*MB) {
 148                         if (((start / (16*MB)) & 0x7) == 0) {
 149                                 start &= ~(128*MB - 1);
 150                                 start += 16*MB;
 151                                 start  = ALIGN(start, alignto);
 152                         }
 153                         if (start/(128*MB) != (start + size)/(128*MB)) {
 154                                 start &= ~(128*MB - 1);
 155                                 start += (128 + 16)*MB;
 156                                 start  = ALIGN(start, alignto);
 157                         }
 158                 }
 159         }
 160
 161         res->start = start;
 162 }
 163 #undef MAX
 164 #undef ALIGN
 165 #undef KB
 166 #undef MB
 167 #undef GB
 168
 169 /*
 170  * Pre-layout host-independant device initialization.
 171  */
 172
 173 static void __init
 174 pcibios_assign_special(struct pci_dev * dev)
 175 {
 176         int i;
 177
 178         /* The first three resources of an IDE controler are often magic,
 179            so leave them unchanged.  This is true, for instance, of the
 180            Contaq 82C693 as seen on SX164 and DP264.  */
 181
 182         if (dev->class >> 8 == PCI_CLASS_STORAGE_IDE) {
 183                 /* Resource 1 of IDE controller is the address of HD_CMD
 184                    register which actually occupies a single byte (0x3f6
 185                    for ide0) in reported 0x3f4-3f7 range. We have to fix
 186                    that to avoid resource conflict with AT-style floppy
 187                    controller. */
 188                 dev->resource[1].start += 2;
 189                 dev->resource[1].end = dev->resource[1].start;
 190                 for (i = 0; i < PCI_NUM_RESOURCES; i++)
 191                         if (dev->resource[i].flags && dev->resource[i].start)
 192                                 pci_claim_resource(dev, i);
 193         }
 194         /*
 195          * We don't have code that will init the CYPRESS bridge correctly
 196          * so we do the next best thing, and depend on the previous
 197          * console code to do the right thing, and ignore it here... :-\
 198          */
 199         else if (dev->vendor == PCI_VENDOR_ID_CONTAQ &&
 200                  dev->device == PCI_DEVICE_ID_CONTAQ_82C693)
 201                 for (i = 0; i < PCI_NUM_RESOURCES; i++)
 202                         if (dev->resource[i].flags && dev->resource[i].start)
 203                                 pci_claim_resource(dev, i);
 204 }
 205
 206
 207 void __init
 208 pcibios_init(void)
 209 {
 210         if (!alpha_mv.init_pci)
 211                 return;
 212         alpha_mv.init_pci();
 213 }
 214
 215 char * __init
 216 pcibios_setup(char *str)
 217 {
 218         return str;
 219 }
 220
 221 void __init
 222 pcibios_fixup_resource(struct resource *res, struct resource *root)
 223 {
 224         res->start += root->start;
 225         res->end += root->start;
 226 }
 227
 228 void __init
 229 pcibios_fixup_device_resources(struct pci_dev *dev, struct pci_bus *bus)
 230 {
 231         /* Update device resources.  */
 232
 233         int i;
 234
 235         for (i = 0; i < PCI_NUM_RESOURCES; i++) {
 236                 if (!dev->resource[i].start)
 237                         continue;
 238                 if (dev->resource[i].flags & IORESOURCE_IO)
 239                         pcibios_fixup_resource(&dev->resource[i],
 240                                                bus->resource[0]);
 241                 else if (dev->resource[i].flags & IORESOURCE_MEM)
 242                         pcibios_fixup_resource(&dev->resource[i],
 243                                                bus->resource[1]);
 244         }
 245         pcibios_assign_special(dev);
 246 }
 247
 248 void __init
 249 pcibios_fixup_bus(struct pci_bus *bus)
 250 {
 251         /* Propogate hose info into the subordinate devices.  */
 252
 253         struct pci_controler *hose = (struct pci_controler *) bus->sysdata;
 254         struct pci_dev *dev;
 255
 256         bus->resource[0] = hose->io_space;
 257         bus->resource[1] = hose->mem_space;
 258         for (dev = bus->devices; dev; dev = dev->sibling) {
 259                 if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI)
 260                         pcibios_fixup_device_resources(dev, bus);
 261         }
 262 }
 263
 264 void __init
 265 pcibios_update_resource(struct pci_dev *dev, struct resource *root,
 266                         struct resource *res, int resource)
 267 {
 268         int where;
 269         u32 reg;
 270
 271         where = PCI_BASE_ADDRESS_0 + (resource * 4);
 272         reg = (res->start - root->start) | (res->flags & 0xf);
 273         pci_write_config_dword(dev, where, reg);
 274         if ((res->flags & (PCI_BASE_ADDRESS_SPACE
 275                            | PCI_BASE_ADDRESS_MEM_TYPE_MASK))
 276             == (PCI_BASE_ADDRESS_SPACE_MEMORY
 277                 | PCI_BASE_ADDRESS_MEM_TYPE_64)) {
 278                 pci_write_config_dword(dev, where+4, 0);
 279                 printk(KERN_WARNING "PCI: dev %s type 64-bit\n", dev->name);
 280         }
 281
 282         /* ??? FIXME -- record old value for shutdown.  */
 283 }
 284
 285 void __init
 286 pcibios_update_irq(struct pci_dev *dev, int irq)
 287 {
 288         pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
 289
 290         /* ??? FIXME -- record old value for shutdown.  */
 291 }
 292
 293 /* Most Alphas have straight-forward swizzling needs.  */
 294
 295 u8 __init
 296 common_swizzle(struct pci_dev *dev, u8 *pinp)
 297 {
 298         struct pci_controler *hose = dev->sysdata;
 299
 300         if (dev->bus->number != hose->first_busno) {
 301                 u8 pin = *pinp;
 302                 do {
 303                         pin = bridge_swizzle(pin, PCI_SLOT(dev->devfn));
 304                         /* Move up the chain of bridges. */
 305                         dev = dev->bus->self;
 306                 } while (dev->bus->self);
 307                 *pinp = pin;
 308
 309                 /* The slot is the slot of the last bridge. */
 310         }
 311
 312         return PCI_SLOT(dev->devfn);
 313 }
 314
 315 void __init
 316 pcibios_fixup_pbus_ranges(struct pci_bus * bus,
 317                           struct pbus_set_ranges_data * ranges)
 318 {
 319         ranges->io_start -= bus->resource[0]->start;
 320         ranges->io_end -= bus->resource[0]->start;
 321         ranges->mem_start -= bus->resource[1]->start;
 322         ranges->mem_end -= bus->resource[1]->start;
 323 }
 324
 325 void __init
 326 common_init_pci(void)
 327 {
 328         struct pci_controler *hose;
 329         struct pci_bus *bus;
 330         int next_busno;
 331
 332         /* Scan all of the recorded PCI controlers.  */
 333         for (next_busno = 0, hose = hose_head; hose; hose = hose->next) {
 334                 hose->first_busno = next_busno;
 335                 hose->last_busno = 0xff;
 336                 bus = pci_scan_bus(next_busno, alpha_mv.pci_ops, hose);
 337                 hose->bus = bus;
 338                 next_busno = hose->last_busno = bus->subordinate;
 339                 next_busno += 1;
 340         }
 341
 342         pci_assign_unassigned_resources(alpha_mv.min_io_address,
 343                                         alpha_mv.min_mem_address);
 344         pci_fixup_irqs(alpha_mv.pci_swizzle, alpha_mv.pci_map_irq);
 345         pci_set_bus_ranges();
 346 }
 347
 348
 349 struct pci_controler * __init
 350 alloc_pci_controler(void)
 351 {
 352         struct pci_controler *hose;
 353
 354         hose = alloc_bootmem(sizeof(*hose));
 355
 356         *hose_tail = hose;
 357         hose_tail = &hose->next;
 358
 359         return hose;
 360 }
 361
 362 struct resource * __init
 363 alloc_resource(void)
 364 {
 365         struct resource *res;
 366
 367         res = alloc_bootmem(sizeof(*res));
 368
 369         return res;
 370 }