include/linux/mc146818rtc.h

   1 /* mc146818rtc.h - register definitions for the Real-Time-Clock / CMOS RAM
   2  * Copyright Torsten Duwe <duwe@informatik.uni-erlangen.de> 1993
   3  * derived from Data Sheet, Copyright Motorola 1984 (!).
   4  * It was written to be part of the Linux operating system.
   5  */
   6 /* permission is hereby granted to copy, modify and redistribute this code
   7  * in terms of the GNU Library General Public License, Version 2 or later,
   8  * at your option.
   9  */
  10
  11 #ifndef _MC146818RTC_H
  12 #define _MC146818RTC_H
  13 #include <asm/io.h>
  14
  15 #ifndef RTC_PORT
  16 #define RTC_PORT(x)     (0x70 + (x))
  17 #define RTC_ALWAYS_BCD  1
  18 #endif
  19
  20 #define CMOS_READ(addr) ({ \
  21 outb_p((addr),RTC_PORT(0)); \
  22 inb_p(RTC_PORT(1)); \
  23 })
  24 #define CMOS_WRITE(val, addr) ({ \
  25 outb_p((addr),RTC_PORT(0)); \
  26 outb_p((val),RTC_PORT(1)); \
  27 })
  28
  29 /**********************************************************************
  30  * register summary
  31  **********************************************************************/
  32 #define RTC_SECONDS             0
  33 #define RTC_SECONDS_ALARM       1
  34 #define RTC_MINUTES             2
  35 #define RTC_MINUTES_ALARM       3
  36 #define RTC_HOURS               4
  37 #define RTC_HOURS_ALARM         5
  38 /* RTC_*_alarm is always true if 2 MSBs are set */
  39 # define RTC_ALARM_DONT_CARE    0xC0
  40
  41 #define RTC_DAY_OF_WEEK         6
  42 #define RTC_DAY_OF_MONTH        7
  43 #define RTC_MONTH               8
  44 #define RTC_YEAR                9
  45
  46 /* control registers - Moto names
  47  */
  48 #define RTC_REG_A               10
  49 #define RTC_REG_B               11
  50 #define RTC_REG_C               12
  51 #define RTC_REG_D               13
  52
  53 /**********************************************************************
  54  * register details
  55  **********************************************************************/
  56 #define RTC_FREQ_SELECT RTC_REG_A
  57
  58 /* update-in-progress  - set to "1" 244 microsecs before RTC goes off the bus,
  59  * reset after update (may take 1.984ms @ 32768Hz RefClock) is complete,
  60  * totalling to a max high interval of 2.228 ms.
  61  */
  62 # define RTC_UIP                0x80
  63 # define RTC_DIV_CTL            0x70
  64    /* divider control: refclock values 4.194 / 1.049 MHz / 32.768 kHz */
  65 #  define RTC_REF_CLCK_4MHZ     0x00
  66 #  define RTC_REF_CLCK_1MHZ     0x10
  67 #  define RTC_REF_CLCK_32KHZ    0x20
  68    /* 2 values for divider stage reset, others for "testing purposes only" */
  69 #  define RTC_DIV_RESET1        0x60
  70 #  define RTC_DIV_RESET2        0x70
  71   /* Periodic intr. / Square wave rate select. 0=none, 1=32.8kHz,... 15=2Hz */
  72 # define RTC_RATE_SELECT        0x0F
  73
  74 /**********************************************************************/
  75 #define RTC_CONTROL     RTC_REG_B
  76 # define RTC_SET 0x80           /* disable updates for clock setting */
  77 # define RTC_PIE 0x40           /* periodic interrupt enable */
  78 # define RTC_AIE 0x20           /* alarm interrupt enable */
  79 # define RTC_UIE 0x10           /* update-finished interrupt enable */
  80 # define RTC_SQWE 0x08          /* enable square-wave output */
  81 # define RTC_DM_BINARY 0x04     /* all time/date values are BCD if clear */
  82 # define RTC_24H 0x02           /* 24 hour mode - else hours bit 7 means pm */
  83 # define RTC_DST_EN 0x01        /* auto switch DST - works f. USA only */
  84
  85 /**********************************************************************/
  86 #define RTC_INTR_FLAGS  RTC_REG_C
  87 /* caution - cleared by read */
  88 # define RTC_IRQF 0x80          /* any of the following 3 is active */
  89 # define RTC_PF 0x40
  90 # define RTC_AF 0x20
  91 # define RTC_UF 0x10
  92
  93 /**********************************************************************/
  94 #define RTC_VALID       RTC_REG_D
  95 # define RTC_VRT 0x80           /* valid RAM and time */
  96 /**********************************************************************/
  97
  98 /* example: !(CMOS_READ(RTC_CONTROL) & RTC_DM_BINARY)
  99  * determines if the following two #defines are needed
 100  */
 101 #ifndef BCD_TO_BIN
 102 #define BCD_TO_BIN(val) ((val)=((val)&15) + ((val)>>4)*10)
 103 #endif
 104
 105 #ifndef BIN_TO_BCD
 106 #define BIN_TO_BCD(val) ((val)=(((val)/10)<<4) + (val)%10)
 107 #endif
 108
 109 /*
 110  * The struct used to pass data via the following ioctl. Similar to the
 111  * struct tm in <time.h>, but it needs to be here so that the kernel
 112  * source is self contained, allowing cross-compiles, etc. etc.
 113  */
 114
 115 struct rtc_time {
 116         int tm_sec;
 117         int tm_min;
 118         int tm_hour;
 119         int tm_mday;
 120         int tm_mon;
 121         int tm_year;
 122         int tm_wday;
 123         int tm_yday;
 124         int tm_isdst;
 125 };
 126
 127 /*
 128  * ioctl calls that are permitted to the /dev/rtc interface, if
 129  * CONFIG_RTC was enabled.
 130  */
 131
 132 #define RTC_AIE_ON      _IO('p', 0x01)  /* Alarm int. enable on         */
 133 #define RTC_AIE_OFF     _IO('p', 0x02)  /* ... off                      */
 134 #define RTC_UIE_ON      _IO('p', 0x03)  /* Update int. enable on        */
 135 #define RTC_UIE_OFF     _IO('p', 0x04)  /* ... off                      */
 136 #define RTC_PIE_ON      _IO('p', 0x05)  /* Periodic int. enable on      */
 137 #define RTC_PIE_OFF     _IO('p', 0x06)  /* ... off                      */
 138
 139 #define RTC_ALM_SET     _IOW('p', 0x07, struct rtc_time) /* Set alarm time  */
 140 #define RTC_ALM_READ    _IOR('p', 0x08, struct rtc_time) /* Read alarm time */
 141 #define RTC_RD_TIME     _IOR('p', 0x09, struct rtc_time) /* Read RTC time   */
 142 #define RTC_SET_TIME    _IOW('p', 0x0a, struct rtc_time) /* Set RTC time    */
 143 #define RTC_IRQP_READ   _IOR('p', 0x0b, unsigned long)   /* Read IRQ rate   */
 144 #define RTC_IRQP_SET    _IOW('p', 0x0c, unsigned long)   /* Set IRQ rate    */
 145 #define RTC_EPOCH_READ  _IOR('p', 0x0d, unsigned long)   /* Read epoch      */
 146 #define RTC_EPOCH_SET   _IOW('p', 0x0e, unsigned long)   /* Set epoch       */
 147
 148
 149 #endif /* _MC146818RTC_H */