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Import 2.3.49pre2
[davej-history.git] / drivers / pci / pci.c
blob1837c2467d0a0489e071862ceea90102680125a3
1 /*
2 * $Id: pci.c,v 1.91 1999/01/21 13:34:01 davem Exp $
3 *
4 * PCI Bus Services, see include/linux/pci.h for further explanation.
5 *
6 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
7 * David Mosberger-Tang
8 *
9 * Copyright 1997 -- 2000 Martin Mares <mj@suse.cz>
10 */
11
12 #include <linux/config.h>
13 #include <linux/module.h>
14 #include <linux/types.h>
15 #include <linux/kernel.h>
16 #include <linux/pci.h>
17 #include <linux/string.h>
18 #include <linux/init.h>
19 #include <linux/malloc.h>
20 #include <linux/ioport.h>
21
22 #include <asm/page.h>
23 #include <asm/dma.h> /* isa_dma_bridge_buggy */
24
25 #undef DEBUG
26
27 #ifdef DEBUG
28 #define DBG(x...) printk(x)
29 #else
30 #define DBG(x...)
31 #endif
32
33 LIST_HEAD(pci_root_buses);
34 LIST_HEAD(pci_devices);
35
36 struct pci_dev *
37 pci_find_slot(unsigned int bus, unsigned int devfn)
38 {
39 struct pci_dev *dev;
40
41 pci_for_each_dev(dev) {
42 if (dev->bus->number == bus && dev->devfn == devfn)
43 return dev;
44 }
45 return NULL;
46 }
47
48
49 struct pci_dev *
50 pci_find_subsys(unsigned int vendor, unsigned int device,
51 unsigned int ss_vendor, unsigned int ss_device,
52 const struct pci_dev *from)
53 {
54 struct list_head *n = from ? from->global_list.next : pci_devices.next;
55
56 while (n != &pci_devices) {
57 struct pci_dev *dev = pci_dev_g(n);
58 if ((vendor == PCI_ANY_ID || dev->vendor == vendor) &&
59 (device == PCI_ANY_ID || dev->device == device) &&
60 (ss_vendor == PCI_ANY_ID || dev->subsystem_vendor == ss_vendor) &&
61 (ss_device == PCI_ANY_ID || dev->subsystem_device == ss_device))
62 return dev;
63 n = n->next;
64 }
65 return NULL;
66 }
67
68
69 struct pci_dev *
70 pci_find_device(unsigned int vendor, unsigned int device, const struct pci_dev *from)
71 {
72 return pci_find_subsys(vendor, device, PCI_ANY_ID, PCI_ANY_ID, from);
73 }
74
75
76 struct pci_dev *
77 pci_find_class(unsigned int class, const struct pci_dev *from)
78 {
79 struct list_head *n = from ? from->global_list.next : pci_devices.next;
80
81 while (n != &pci_devices) {
82 struct pci_dev *dev = pci_dev_g(n);
83 if (dev->class == class)
84 return dev;
85 n = n->next;
86 }
87 return NULL;
88 }
89
90
91 int
92 pci_find_capability(struct pci_dev *dev, int cap)
93 {
94 u16 status;
95 u8 pos, id;
96 int ttl = 48;
97
98 pci_read_config_word(dev, PCI_STATUS, &status);
99 if (!(status & PCI_STATUS_CAP_LIST))
100 return 0;
101 switch (dev->hdr_type) {
102 case PCI_HEADER_TYPE_NORMAL:
103 case PCI_HEADER_TYPE_BRIDGE:
104 pci_read_config_byte(dev, PCI_CAPABILITY_LIST, &pos);
105 break;
106 case PCI_HEADER_TYPE_CARDBUS:
107 pci_read_config_byte(dev, PCI_CB_CAPABILITY_LIST, &pos);
108 break;
109 default:
110 return 0;
111 }
112 while (ttl-- && pos >= 0x40) {
113 pos &= ~3;
114 pci_read_config_byte(dev, pos + PCI_CAP_LIST_ID, &id);
115 if (id == 0xff)
116 break;
117 if (id == cap)
118 return pos;
119 pci_read_config_byte(dev, pos + PCI_CAP_LIST_NEXT, &pos);
120 }
121 return 0;
122 }
123
124
125 /*
126 * For given resource region of given device, return the resource
127 * region of parent bus the given region is contained in or where
128 * it should be allocated from.
129 */
130 struct resource *
131 pci_find_parent_resource(const struct pci_dev *dev, struct resource *res)
132 {
133 const struct pci_bus *bus = dev->bus;
134 int i;
135 struct resource *best = NULL;
136
137 for(i=0; i<4; i++) {
138 struct resource *r = bus->resource[i];
139 if (!r)
140 continue;
141 if (res->start && !(res->start >= r->start && res->end <= r->end))
142 continue; /* Not contained */
143 if ((res->flags ^ r->flags) & (IORESOURCE_IO | IORESOURCE_MEM))
144 continue; /* Wrong type */
145 if (!((res->flags ^ r->flags) & IORESOURCE_PREFETCH))
146 return r; /* Exact match */
147 if ((res->flags & IORESOURCE_PREFETCH) && !(r->flags & IORESOURCE_PREFETCH))
148 best = r; /* Approximating prefetchable by non-prefetchable */
149 }
150 return best;
151 }
152
153 /*
154 * Set power management state of a device. For transitions from state D3
155 * it isn't as straightforward as one could assume since many devices forget
156 * their configuration space during wakeup. Returns old power state.
157 */
158 int
159 pci_set_power_state(struct pci_dev *dev, int new_state)
160 {
161 u32 base[5], romaddr;
162 u16 pci_command, pwr_command;
163 u8 pci_latency, pci_cacheline;
164 int i, old_state;
165 int pm = pci_find_capability(dev, PCI_CAP_ID_PM);
166
167 if (!pm)
168 return 0;
169 pci_read_config_word(dev, pm + PCI_PM_CTRL, &pwr_command);
170 old_state = pwr_command & PCI_PM_CTRL_STATE_MASK;
171 if (old_state == new_state)
172 return old_state;
173 DBG("PCI: %s goes from D%d to D%d\n", dev->slot_name, old_state, new_state);
174 if (old_state == 3) {
175 pci_read_config_word(dev, PCI_COMMAND, &pci_command);
176 pci_write_config_word(dev, PCI_COMMAND, pci_command & ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY));
177 for (i = 0; i < 5; i++)
178 pci_read_config_dword(dev, PCI_BASE_ADDRESS_0 + i*4, &base[i]);
179 pci_read_config_dword(dev, PCI_ROM_ADDRESS, &romaddr);
180 pci_read_config_byte(dev, PCI_LATENCY_TIMER, &pci_latency);
181 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &pci_cacheline);
182 pci_write_config_word(dev, pm + PCI_PM_CTRL, new_state);
183 for (i = 0; i < 5; i++)
184 pci_write_config_dword(dev, PCI_BASE_ADDRESS_0 + i*4, base[i]);
185 pci_write_config_dword(dev, PCI_ROM_ADDRESS, romaddr);
186 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
187 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cacheline);
188 pci_write_config_byte(dev, PCI_LATENCY_TIMER, pci_latency);
189 pci_write_config_word(dev, PCI_COMMAND, pci_command);
190 } else
191 pci_write_config_word(dev, pm + PCI_PM_CTRL, (pwr_command & ~PCI_PM_CTRL_STATE_MASK) | new_state);
192 return old_state;
193 }
194
195 /*
196 * Initialize device before it's used by a driver. Ask low-level code
197 * to enable I/O and memory. Wake up the device if it was suspended.
198 * Beware, this function can fail.
199 */
200 int
201 pci_enable_device(struct pci_dev *dev)
202 {
203 int err;
204
205 if ((err = pcibios_enable_device(dev)) < 0)
206 return err;
207 pci_set_power_state(dev, 0);
208 return 0;
209 }
210
211 /*
212 * Registration of PCI drivers and handling of hot-pluggable devices.
213 */
214
215 static LIST_HEAD(pci_drivers);
216
217 const struct pci_device_id *
218 pci_match_device(const struct pci_device_id *ids, const struct pci_dev *dev)
219 {
220 while (ids->vendor || ids->subvendor || ids->class_mask) {
221 if ((ids->vendor == PCI_ANY_ID || ids->vendor == dev->vendor) &&
222 (ids->device == PCI_ANY_ID || ids->device == dev->device) &&
223 (ids->subvendor == PCI_ANY_ID || ids->subvendor == dev->subsystem_vendor) &&
224 (ids->subdevice == PCI_ANY_ID || ids->subdevice == dev->subsystem_device) &&
225 !((ids->class ^ dev->class) & ids->class_mask))
226 return ids;
227 ids++;
228 }
229 return NULL;
230 }
231
232 static int
233 pci_announce_device(struct pci_driver *drv, struct pci_dev *dev)
234 {
235 const struct pci_device_id *id;
236
237 if (drv->id_table) {
238 id = pci_match_device(drv->id_table, dev);
239 if (!id)
240 return 0;
241 } else
242 id = NULL;
243 if (drv->probe(dev, id) >= 0) {
244 dev->driver = drv;
245 return 1;
246 }
247 return 0;
248 }
249
250 int
251 pci_register_driver(struct pci_driver *drv)
252 {
253 struct pci_dev *dev;
254 int count = 0;
255
256 list_add_tail(&drv->node, &pci_drivers);
257 pci_for_each_dev(dev) {
258 if (!pci_dev_driver(dev))
259 count += pci_announce_device(drv, dev);
260 }
261 return count;
262 }
263
264 void
265 pci_unregister_driver(struct pci_driver *drv)
266 {
267 struct pci_dev *dev;
268
269 list_del(&drv->node);
270 pci_for_each_dev(dev) {
271 if (dev->driver == drv) {
272 if (drv->remove)
273 drv->remove(dev);
274 dev->driver = NULL;
275 }
276 }
277 }
278
279 #ifdef CONFIG_HOTPLUG
280
281 void
282 pci_insert_device(struct pci_dev *dev, struct pci_bus *bus)
283 {
284 struct list_head *ln;
285
286 list_add_tail(&dev->bus_list, &bus->devices);
287 list_add_tail(&dev->global_list, &pci_devices);
288 #ifdef CONFIG_PROC_FS
289 pci_proc_attach_device(dev);
290 #endif
291 for(ln=pci_drivers.next; ln != &pci_drivers; ln=ln->next) {
292 struct pci_driver *drv = list_entry(ln, struct pci_driver, node);
293 if (drv->remove && pci_announce_device(drv, dev))
294 break;
295 }
296 }
297
298 static void pci_free_resources(struct pci_dev *dev)
299 {
300 int i;
301
302 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
303 struct resource *res = dev->resource + i;
304 if (res->parent)
305 release_resource(res);
306 }
307 }
308
309 void
310 pci_remove_device(struct pci_dev *dev)
311 {
312 if (dev->driver) {
313 if (dev->driver->remove)
314 dev->driver->remove(dev);
315 dev->driver = NULL;
316 }
317 list_del(&dev->bus_list);
318 list_del(&dev->global_list);
319 pci_free_resources(dev);
320 #ifdef CONFIG_PROC_FS
321 pci_proc_detach_device(dev);
322 #endif
323 }
324
325 #endif
326
327 static struct pci_driver pci_compat_driver = {
328 name: "compat"
329 };
330
331 struct pci_driver *
332 pci_dev_driver(const struct pci_dev *dev)
333 {
334 if (dev->driver)
335 return dev->driver;
336 else {
337 int i;
338 for(i=0; i<=PCI_ROM_RESOURCE; i++)
339 if (dev->resource[i].flags & IORESOURCE_BUSY)
340 return &pci_compat_driver;
341 }
342 return NULL;
343 }
344
345
346 /*
347 * This interrupt-safe spinlock protects all accesses to PCI
348 * configuration space.
349 */
350
351 static spinlock_t pci_lock = SPIN_LOCK_UNLOCKED;
352
353 /*
354 * Wrappers for all PCI configuration access functions. They just check
355 * alignment, do locking and call the low-level functions pointed to
356 * by pci_dev->ops.
357 */
358
359 #define PCI_byte_BAD 0
360 #define PCI_word_BAD (pos & 1)
361 #define PCI_dword_BAD (pos & 3)
362
363 #define PCI_OP(rw,size,type) \
364 int pci_##rw##_config_##size (struct pci_dev *dev, int pos, type value) \
365 { \
366 int res; \
367 unsigned long flags; \
368 if (PCI_##size##_BAD) return PCIBIOS_BAD_REGISTER_NUMBER; \
369 spin_lock_irqsave(&pci_lock, flags); \
370 res = dev->bus->ops->rw##_##size(dev, pos, value); \
371 spin_unlock_irqrestore(&pci_lock, flags); \
372 return res; \
373 }
374
375 PCI_OP(read, byte, u8 *)
376 PCI_OP(read, word, u16 *)
377 PCI_OP(read, dword, u32 *)
378 PCI_OP(write, byte, u8)
379 PCI_OP(write, word, u16)
380 PCI_OP(write, dword, u32)
381
382
383 void
384 pci_set_master(struct pci_dev *dev)
385 {
386 u16 cmd;
387 u8 lat;
388
389 pci_read_config_word(dev, PCI_COMMAND, &cmd);
390 if (! (cmd & PCI_COMMAND_MASTER)) {
391 printk("PCI: Enabling bus mastering for device %s\n", dev->slot_name);
392 cmd |= PCI_COMMAND_MASTER;
393 pci_write_config_word(dev, PCI_COMMAND, cmd);
394 }
395 pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
396 if (lat < 16) {
397 printk("PCI: Increasing latency timer of device %s to 64\n", dev->slot_name);
398 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64);
399 }
400 }
401
402 /*
403 * Translate the low bits of the PCI base
404 * to the resource type
405 */
406 static inline unsigned int pci_calc_resource_flags(unsigned int flags)
407 {
408 if (flags & PCI_BASE_ADDRESS_SPACE_IO)
409 return IORESOURCE_IO;
410
411 if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH)
412 return IORESOURCE_MEM | IORESOURCE_PREFETCH;
413
414 return IORESOURCE_MEM;
415 }
416
417 static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
418 {
419 unsigned int pos, reg, next;
420 u32 l, sz, tmp;
421 u16 cmd;
422 struct resource *res;
423
424 /* Disable IO and memory while we fiddle */
425 pci_read_config_word(dev, PCI_COMMAND, &cmd);
426 tmp = cmd & ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY);
427 pci_write_config_word(dev, PCI_COMMAND, tmp);
428
429 for(pos=0; pos<howmany; pos = next) {
430 next = pos+1;
431 res = &dev->resource[pos];
432 res->name = dev->name;
433 reg = PCI_BASE_ADDRESS_0 + (pos << 2);
434 pci_read_config_dword(dev, reg, &l);
435 pci_write_config_dword(dev, reg, ~0);
436 pci_read_config_dword(dev, reg, &sz);
437 pci_write_config_dword(dev, reg, l);
438 if (!sz || sz == 0xffffffff)
439 continue;
440 if (l == 0xffffffff)
441 l = 0;
442 if ((l & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_MEMORY) {
443 res->start = l & PCI_BASE_ADDRESS_MEM_MASK;
444 sz = ~(sz & PCI_BASE_ADDRESS_MEM_MASK);
445 } else {
446 res->start = l & PCI_BASE_ADDRESS_IO_MASK;
447 sz = ~(sz & PCI_BASE_ADDRESS_IO_MASK) & 0xffff;
448 }
449 res->end = res->start + (unsigned long) sz;
450 res->flags |= (l & 0xf) | pci_calc_resource_flags(l);
451 if ((l & (PCI_BASE_ADDRESS_SPACE | PCI_BASE_ADDRESS_MEM_TYPE_MASK))
452 == (PCI_BASE_ADDRESS_SPACE_MEMORY | PCI_BASE_ADDRESS_MEM_TYPE_64)) {
453 pci_read_config_dword(dev, reg+4, &l);
454 next++;
455 #if BITS_PER_LONG == 64
456 res->start |= ((unsigned long) l) << 32;
457 res->end = res->start + sz;
458 pci_write_config_dword(dev, reg+4, ~0);
459 pci_read_config_dword(dev, reg+4, &tmp);
460 pci_write_config_dword(dev, reg+4, l);
461 if (l)
462 res->end = res->start + (((unsigned long) ~l) << 32);
463 #else
464 if (l) {
465 printk(KERN_ERR "PCI: Unable to handle 64-bit address for device %s\n", dev->slot_name);
466 res->start = 0;
467 res->flags = 0;
468 continue;
469 }
470 #endif
471 }
472 }
473 if (rom) {
474 dev->rom_base_reg = rom;
475 res = &dev->resource[PCI_ROM_RESOURCE];
476 pci_read_config_dword(dev, rom, &l);
477 pci_write_config_dword(dev, rom, ~PCI_ROM_ADDRESS_ENABLE);
478 pci_read_config_dword(dev, rom, &sz);
479 pci_write_config_dword(dev, rom, l);
480 if (l == 0xffffffff)
481 l = 0;
482 if (sz && sz != 0xffffffff) {
483 res->flags = (l & PCI_ROM_ADDRESS_ENABLE) |
484 IORESOURCE_MEM | IORESOURCE_PREFETCH | IORESOURCE_READONLY | IORESOURCE_CACHEABLE;
485 res->start = l & PCI_ROM_ADDRESS_MASK;
486 sz = ~(sz & PCI_ROM_ADDRESS_MASK);
487 res->end = res->start + (unsigned long) sz;
488 }
489 res->name = dev->name;
490 }
491 pci_write_config_word(dev, PCI_COMMAND, cmd);
492 }
493
494 void __init pci_read_bridge_bases(struct pci_bus *child)
495 {
496 struct pci_dev *dev = child->self;
497 u8 io_base_lo, io_limit_lo;
498 u16 mem_base_lo, mem_limit_lo, io_base_hi, io_limit_hi;
499 u32 mem_base_hi, mem_limit_hi;
500 unsigned long base, limit;
501 struct resource *res;
502 int i;
503
504 if (!dev) /* It's a host bus, nothing to read */
505 return;
506
507 for(i=0; i<3; i++)
508 child->resource[i] = &dev->resource[PCI_BRIDGE_RESOURCES+i];
509
510 res = child->resource[0];
511 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
512 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
513 pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi);
514 pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi);
515 base = ((io_base_lo & PCI_IO_RANGE_MASK) << 8) | (io_base_hi << 16);
516 limit = ((io_limit_lo & PCI_IO_RANGE_MASK) << 8) | (io_limit_hi << 16);
517 if (base && base <= limit) {
518 res->flags |= (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO;
519 res->start = base;
520 res->end = limit + 0xfff;
521 res->name = child->name;
522 }
523
524 res = child->resource[1];
525 pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo);
526 pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo);
527 base = (mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16;
528 limit = (mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16;
529 if (base && base <= limit) {
530 res->flags |= (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM;
531 res->start = base;
532 res->end = limit + 0xfffff;
533 res->name = child->name;
534 }
535
536 res = child->resource[2];
537 pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo);
538 pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo);
539 pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi);
540 pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi);
541 base = (mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16;
542 limit = (mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16;
543 #if BITS_PER_LONG == 64
544 base |= ((long) mem_base_hi) << 32;
545 limit |= ((long) mem_limit_hi) << 32;
546 #else
547 if (mem_base_hi || mem_limit_hi) {
548 printk(KERN_ERR "PCI: Unable to handle 64-bit address space for %s\n", child->name);
549 return;
550 }
551 #endif
552 if (base && base <= limit) {
553 res->flags |= (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM | IORESOURCE_PREFETCH;
554 res->start = base;
555 res->end = limit + 0xfffff;
556 res->name = child->name;
557 }
558 }
559
560 static struct pci_bus * __init pci_alloc_bus(void)
561 {
562 struct pci_bus *b;
563
564 b = kmalloc(sizeof(*b), GFP_KERNEL);
565 if (b) {
566 memset(b, 0, sizeof(*b));
567 INIT_LIST_HEAD(&b->children);
568 INIT_LIST_HEAD(&b->devices);
569 }
570 return b;
571 }
572
573 static struct pci_bus * __init pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, int busnr)
574 {
575 struct pci_bus *child;
576
577 /*
578 * Allocate a new bus, and inherit stuff from the parent..
579 */
580 child = pci_alloc_bus();
581
582 list_add_tail(&child->node, &parent->children);
583 child->self = dev;
584 dev->subordinate = child;
585 child->parent = parent;
586 child->ops = parent->ops;
587 child->sysdata = parent->sysdata;
588
589 /*
590 * Set up the primary, secondary and subordinate
591 * bus numbers.
592 */
593 child->number = child->secondary = busnr;
594 child->primary = parent->secondary;
595 child->subordinate = 0xff;
596
597 return child;
598 }
599
600 /*
601 * A CardBus bridge is basically the same as a regular PCI bridge,
602 * except we don't scan behind it because it will be changing.
603 */
604 static int __init pci_scan_cardbus(struct pci_bus *bus, struct pci_dev *dev, int busnr)
605 {
606 int i;
607 unsigned short cr;
608 unsigned int buses;
609 struct pci_bus *child;
610
611 /*
612 * Insert it into the tree of buses.
613 */
614 DBG("Scanning CardBus bridge %s\n", dev->slot_name);
615 child = pci_add_new_bus(bus, dev, ++busnr);
616
617 for (i = 0; i < 4; i++)
618 child->resource[i] = &dev->resource[PCI_BRIDGE_RESOURCES+i];
619
620 /*
621 * Maybe we'll have another bus behind this one?
622 */
623 child->subordinate = ++busnr;
624 sprintf(child->name, "PCI CardBus #%02x", child->number);
625
626 /*
627 * Clear all status bits and turn off memory,
628 * I/O and master enables.
629 */
630 pci_read_config_word(dev, PCI_COMMAND, &cr);
631 pci_write_config_word(dev, PCI_COMMAND, 0x0000);
632 pci_write_config_word(dev, PCI_STATUS, 0xffff);
633
634 /*
635 * Read the existing primary/secondary/subordinate bus
636 * number configuration to determine if the bridge
637 * has already been configured by the system. If so,
638 * do not modify the configuration, merely note it.
639 */
640 pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses);
641 if ((buses & 0xFFFFFF) != 0 && ! pcibios_assign_all_busses()) {
642 child->primary = buses & 0xFF;
643 child->secondary = (buses >> 8) & 0xFF;
644 child->subordinate = (buses >> 16) & 0xFF;
645 child->number = child->secondary;
646 if (child->subordinate > busnr)
647 busnr = child->subordinate;
648 } else {
649 /*
650 * Configure the bus numbers for this bridge:
651 */
652 buses &= 0xff000000;
653 buses |=
654 (((unsigned int)(child->primary) << 0) |
655 ((unsigned int)(child->secondary) << 8) |
656 ((unsigned int)(child->subordinate) << 16));
657 pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses);
658 }
659 pci_write_config_word(dev, PCI_COMMAND, cr);
660 return busnr;
661 }
662
663 static unsigned int __init pci_do_scan_bus(struct pci_bus *bus);
664
665 /*
666 * If it's a bridge, scan the bus behind it.
667 */
668 static int __init pci_scan_bridge(struct pci_bus *bus, struct pci_dev * dev, int max)
669 {
670 unsigned int buses;
671 unsigned short cr;
672 struct pci_bus *child;
673
674 /*
675 * Insert it into the tree of buses.
676 */
677 DBG("Scanning behind PCI bridge %s\n", dev->slot_name);
678 child = pci_add_new_bus(bus, dev, ++max);
679 sprintf(child->name, "PCI Bus #%02x", child->number);
680
681 /*
682 * Clear all status bits and turn off memory,
683 * I/O and master enables.
684 */
685 pci_read_config_word(dev, PCI_COMMAND, &cr);
686 pci_write_config_word(dev, PCI_COMMAND, 0x0000);
687 pci_write_config_word(dev, PCI_STATUS, 0xffff);
688
689 /*
690 * Read the existing primary/secondary/subordinate bus
691 * number configuration to determine if the PCI bridge
692 * has already been configured by the system. If so,
693 * do not modify the configuration, merely note it.
694 */
695 pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses);
696 if ((buses & 0xFFFFFF) != 0 && ! pcibios_assign_all_busses()) {
697 unsigned int cmax;
698 child->primary = buses & 0xFF;
699 child->secondary = (buses >> 8) & 0xFF;
700 child->subordinate = (buses >> 16) & 0xFF;
701 child->number = child->secondary;
702 cmax = pci_do_scan_bus(child);
703 if (cmax > max) max = cmax;
704 } else {
705 /*
706 * Configure the bus numbers for this bridge:
707 */
708 buses &= 0xff000000;
709 buses |=
710 (((unsigned int)(child->primary) << 0) |
711 ((unsigned int)(child->secondary) << 8) |
712 ((unsigned int)(child->subordinate) << 16));
713 pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses);
714 /*
715 * Now we can scan all subordinate buses:
716 */
717 max = pci_do_scan_bus(child);
718 /*
719 * Set the subordinate bus number to its real
720 * value:
721 */
722 child->subordinate = max;
723 buses = (buses & 0xff00ffff)
724 | ((unsigned int)(child->subordinate) << 16);
725 pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses);
726 }
727 pci_write_config_word(dev, PCI_COMMAND, cr);
728 return max;
729 }
730
731 /*
732 * Read interrupt line and base address registers.
733 * The architecture-dependent code can tweak these, of course.
734 */
735 static void pci_read_irq(struct pci_dev *dev)
736 {
737 unsigned char irq;
738
739 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq);
740 if (irq)
741 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
742 dev->irq = irq;
743 }
744
745 /*
746 * Fill in class and map information of a device
747 */
748 int pci_setup_device(struct pci_dev * dev)
749 {
750 u32 class;
751
752 sprintf(dev->slot_name, "%02x:%02x.%d", dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn));
753 sprintf(dev->name, "PCI device %04x:%04x", dev->vendor, dev->device);
754
755 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class);
756 class >>= 8; /* upper 3 bytes */
757 dev->class = class;
758 class >>= 8;
759
760 DBG("Found %02x:%02x [%04x/%04x] %06x %02x\n", dev->bus->number, dev->devfn, dev->vendor, dev->device, class, dev->hdr_type);
761
762 switch (dev->hdr_type) { /* header type */
763 case PCI_HEADER_TYPE_NORMAL: /* standard header */
764 if (class == PCI_CLASS_BRIDGE_PCI)
765 goto bad;
766 pci_read_irq(dev);
767 pci_read_bases(dev, 6, PCI_ROM_ADDRESS);
768 pci_read_config_word(dev, PCI_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
769 pci_read_config_word(dev, PCI_SUBSYSTEM_ID, &dev->subsystem_device);
770 break;
771
772 case PCI_HEADER_TYPE_BRIDGE: /* bridge header */
773 if (class != PCI_CLASS_BRIDGE_PCI)
774 goto bad;
775 pci_read_bases(dev, 2, PCI_ROM_ADDRESS1);
776 break;
777
778 case PCI_HEADER_TYPE_CARDBUS: /* CardBus bridge header */
779 if (class != PCI_CLASS_BRIDGE_CARDBUS)
780 goto bad;
781 pci_read_irq(dev);
782 pci_read_bases(dev, 1, 0);
783 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
784 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_ID, &dev->subsystem_device);
785 break;
786
787 default: /* unknown header */
788 printk(KERN_ERR "PCI: device %s has unknown header type %02x, ignoring.\n",
789 dev->slot_name, dev->hdr_type);
790 return -1;
791
792 bad:
793 printk(KERN_ERR "PCI: %s: class %x doesn't match header type %02x. Ignoring class.\n",
794 dev->slot_name, class, dev->hdr_type);
795 dev->class = PCI_CLASS_NOT_DEFINED;
796 }
797
798 /* We found a fine healthy device, go go go... */
799 return 0;
800 }
801
802 /*
803 * Read the config data for a PCI device, sanity-check it
804 * and fill in the dev structure...
805 */
806 static struct pci_dev * __init pci_scan_device(struct pci_dev *temp)
807 {
808 struct pci_dev *dev;
809 u32 l;
810
811 if (pci_read_config_dword(temp, PCI_VENDOR_ID, &l))
812 return NULL;
813
814 /* some broken boards return 0 or ~0 if a slot is empty: */
815 if (l == 0xffffffff || l == 0x00000000 || l == 0x0000ffff || l == 0xffff0000)
816 return NULL;
817
818 dev = kmalloc(sizeof(*dev), GFP_KERNEL);
819 if (!dev)
820 return NULL;
821
822 memcpy(dev, temp, sizeof(*dev));
823 dev->vendor = l & 0xffff;
824 dev->device = (l >> 16) & 0xffff;
825
826 /* Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer)
827 set this higher, assuming the system even supports it. */
828 dev->dma_mask = 0xffffffff;
829 if (pci_setup_device(dev) < 0) {
830 kfree(dev);
831 dev = NULL;
832 }
833 return dev;
834 }
835
836 struct pci_dev * __init pci_scan_slot(struct pci_dev *temp)
837 {
838 struct pci_bus *bus = temp->bus;
839 struct pci_dev *dev;
840 struct pci_dev *first_dev = NULL;
841 int func = 0;
842 int is_multi = 0;
843 u8 hdr_type;
844
845 for (func = 0; func < 8; func++, temp->devfn++) {
846 if (func && !is_multi) /* not a multi-function device */
847 continue;
848 if (pci_read_config_byte(temp, PCI_HEADER_TYPE, &hdr_type))
849 continue;
850 temp->hdr_type = hdr_type & 0x7f;
851
852 dev = pci_scan_device(temp);
853 if (!dev)
854 continue;
855 pci_name_device(dev);
856 if (!func) {
857 is_multi = hdr_type & 0x80;
858 first_dev = dev;
859 }
860
861 /*
862 * Link the device to both the global PCI device chain and
863 * the per-bus list of devices.
864 */
865 list_add_tail(&dev->global_list, &pci_devices);
866 list_add_tail(&dev->bus_list, &bus->devices);
867
868 /* Fix up broken headers */
869 pci_fixup_device(PCI_FIXUP_HEADER, dev);
870 }
871 return first_dev;
872 }
873
874 static unsigned int __init pci_do_scan_bus(struct pci_bus *bus)
875 {
876 unsigned int devfn, max;
877 struct list_head *ln;
878 struct pci_dev *dev, dev0;
879
880 DBG("Scanning bus %02x\n", bus->number);
881 max = bus->secondary;
882
883 /* Create a device template */
884 memset(&dev0, 0, sizeof(dev0));
885 dev0.bus = bus;
886 dev0.sysdata = bus->sysdata;
887
888 /* Go find them, Rover! */
889 for (devfn = 0; devfn < 0x100; devfn += 8) {
890 dev0.devfn = devfn;
891 pci_scan_slot(&dev0);
892 }
893
894 /*
895 * After performing arch-dependent fixup of the bus, look behind
896 * all PCI-to-PCI bridges on this bus.
897 */
898 DBG("Fixups for bus %02x\n", bus->number);
899 pcibios_fixup_bus(bus);
900 for (ln=bus->devices.next; ln != &bus->devices; ln=ln->next) {
901 dev = pci_dev_b(ln);
902 switch (dev->class >> 8) {
903 case PCI_CLASS_BRIDGE_PCI:
904 max = pci_scan_bridge(bus, dev, max);
905 break;
906 case PCI_CLASS_BRIDGE_CARDBUS:
907 max = pci_scan_cardbus(bus, dev, max);
908 break;
909 }
910 }
911
912 /*
913 * We've scanned the bus and so we know all about what's on
914 * the other side of any bridges that may be on this bus plus
915 * any devices.
916 *
917 * Return how far we've got finding sub-buses.
918 */
919 DBG("Bus scan for %02x returning with max=%02x\n", bus->number, max);
920 return max;
921 }
922
923 static int __init pci_bus_exists(const struct list_head *list, int nr)
924 {
925 const struct list_head *l;
926
927 for(l=list->next; l != list; l = l->next) {
928 const struct pci_bus *b = pci_bus_b(l);
929 if (b->number == nr || pci_bus_exists(&b->children, nr))
930 return 1;
931 }
932 return 0;
933 }
934
935 struct pci_bus * __init pci_alloc_primary_bus(int bus)
936 {
937 struct pci_bus *b;
938
939 if (pci_bus_exists(&pci_root_buses, bus)) {
940 /* If we already got to this bus through a different bridge, ignore it */
941 DBG("PCI: Bus %02x already known\n", bus);
942 return NULL;
943 }
944
945 b = pci_alloc_bus();
946 list_add_tail(&b->node, &pci_root_buses);
947
948 b->number = b->secondary = bus;
949 b->resource[0] = &ioport_resource;
950 b->resource[1] = &iomem_resource;
951 return b;
952 }
953
954 struct pci_bus * __init pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata)
955 {
956 struct pci_bus *b = pci_alloc_primary_bus(bus);
957 if (b) {
958 b->sysdata = sysdata;
959 b->ops = ops;
960 b->subordinate = pci_do_scan_bus(b);
961 }
962 return b;
963 }
964
965 void __init pci_init(void)
966 {
967 struct pci_dev *dev;
968
969 pcibios_init();
970
971 pci_for_each_dev(dev) {
972 pci_fixup_device(PCI_FIXUP_FINAL, dev);
973 }
974 }
975
976 static int __init pci_setup(char *str)
977 {
978 while (str) {
979 char *k = strchr(str, ',');
980 if (k)
981 *k++ = 0;
982 if (*str && (str = pcibios_setup(str)) && *str) {
983 /* PCI layer options should be handled here */
984 printk(KERN_ERR "PCI: Unknown option `%s'\n", str);
985 }
986 str = k;
987 }
988 return 1;
989 }
990
991 __setup("pci=", pci_setup);
992
993
994 EXPORT_SYMBOL(pci_read_config_byte);
995 EXPORT_SYMBOL(pci_read_config_word);
996 EXPORT_SYMBOL(pci_read_config_dword);
997 EXPORT_SYMBOL(pci_write_config_byte);
998 EXPORT_SYMBOL(pci_write_config_word);
999 EXPORT_SYMBOL(pci_write_config_dword);
1000 EXPORT_SYMBOL(pci_devices);
1001 EXPORT_SYMBOL(pci_root_buses);
1002 EXPORT_SYMBOL(pci_enable_device);
1003 EXPORT_SYMBOL(pci_find_capability);
1004 EXPORT_SYMBOL(pci_find_class);
1005 EXPORT_SYMBOL(pci_find_device);
1006 EXPORT_SYMBOL(pci_find_slot);
1007 EXPORT_SYMBOL(pci_find_subsys);
1008 EXPORT_SYMBOL(pci_set_master);
1009 EXPORT_SYMBOL(pci_set_power_state);
1010 EXPORT_SYMBOL(pci_assign_resource);
1011 EXPORT_SYMBOL(pci_register_driver);
1012 EXPORT_SYMBOL(pci_unregister_driver);
1013 EXPORT_SYMBOL(pci_match_device);
1014 EXPORT_SYMBOL(pci_find_parent_resource);
1015
1016 #ifdef CONFIG_HOTPLUG
1017 EXPORT_SYMBOL(pci_setup_device);
1018 EXPORT_SYMBOL(pci_insert_device);
1019 EXPORT_SYMBOL(pci_remove_device);
1020 #endif
1021
1022 /* Obsolete functions */
1023
1024 EXPORT_SYMBOL(pcibios_present);
1025 EXPORT_SYMBOL(pcibios_read_config_byte);
1026 EXPORT_SYMBOL(pcibios_read_config_word);
1027 EXPORT_SYMBOL(pcibios_read_config_dword);
1028 EXPORT_SYMBOL(pcibios_write_config_byte);
1029 EXPORT_SYMBOL(pcibios_write_config_word);
1030 EXPORT_SYMBOL(pcibios_write_config_dword);
1031 EXPORT_SYMBOL(pcibios_find_class);
1032 EXPORT_SYMBOL(pcibios_find_device);
1033
1034 /* Quirk info */
1035
1036 EXPORT_SYMBOL(isa_dma_bridge_buggy);
1037 EXPORT_SYMBOL(pci_pci_problems);
1038
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