arch/mips/ddb5074/pci.c

   1 /*
   2  *  arch/mips/ddb5074/pci.c -- NEC DDB Vrc-5074 PCI access routines
   3  *
   4  *  Copyright (C) 2000 Geert Uytterhoeven <geert@sonycom.com>
   5  *                     Albert Dorofeev <albert@sonycom.com>
   6  *                     Sony Suprastructure Center Europe (SUPC-E), Brussels
   7  *
   8  *  $Id: pci.c,v 1.4 2000/02/18 00:02:17 ralf Exp $
   9  */
  10
  11 #include <linux/init.h>
  12 #include <linux/kernel.h>
  13 #include <linux/pci.h>
  14 #include <linux/types.h>
  15 #include <linux/sched.h>
  16 #include <linux/ioport.h>
  17 #include <asm-mips/nile4.h>
  18
  19
  20 static u32 nile4_pre_pci_access0(int slot_num)
  21 {
  22     u32 pci_addr = 0;
  23     u32 virt_addr = NILE4_PCI_CFG_BASE;
  24
  25     /* Set window 1 address 8000000 - 64 bit - 2 MB (PCI config space) */
  26     nile4_set_pdar(NILE4_PCIW1, PHYSADDR(virt_addr), 0x00200000, 64, 0, 0);
  27     if (slot_num > 2)
  28         pci_addr = 0x00040000 << slot_num;
  29     else
  30         virt_addr += 0x00040000 << slot_num;
  31     nile4_set_pmr(NILE4_PCIINIT1, NILE4_PCICMD_CFG, pci_addr);
  32     return virt_addr;
  33 }
  34
  35 static void nile4_post_pci_access0(void)
  36 {
  37     /* Set window 1 back to address 8000000 - 64 bit - 128 MB (PCI IO space) */
  38     nile4_set_pdar(NILE4_PCIW1, PHYSADDR(NILE4_PCI_MEM_BASE), 0x08000000, 64,
  39                    1, 1);
  40     nile4_set_pmr(NILE4_PCIINIT1, NILE4_PCICMD_MEM, 0);
  41 }
  42
  43
  44 static int nile4_pci_read_config_dword( struct pci_dev *dev,
  45                                 int where, u32 *val)
  46 {
  47     int slot_num, func_num;
  48     u32 base;
  49
  50     /*
  51      *  For starters let's do configuration cycle 0 only (one bus only)
  52      */
  53     if (dev->bus->number)
  54         return PCIBIOS_FUNC_NOT_SUPPORTED;
  55
  56     slot_num = PCI_SLOT(dev->devfn);
  57     func_num = PCI_FUNC(dev->devfn);
  58     if (slot_num == 5) {
  59         /*
  60          *  This is Nile 4 and it will crash if we access it like other
  61          *   devices
  62          */
  63         *val = nile4_in32(NILE4_PCI_BASE + where);
  64         return PCIBIOS_SUCCESSFUL;
  65     }
  66     base = nile4_pre_pci_access0(slot_num);
  67     *val = *((volatile u32 *)(base + (func_num << 8) + (where & 0xfc)));
  68     nile4_post_pci_access0();
  69     return PCIBIOS_SUCCESSFUL;
  70 }
  71
  72 static int nile4_pci_write_config_dword(struct pci_dev *dev, int where,
  73                                         u32 val)
  74 {
  75     int slot_num, func_num;
  76     u32 base;
  77
  78     /*
  79      *  For starters let's do configuration cycle 0 only (one bus only)
  80      */
  81     if (dev->bus->number)
  82         return PCIBIOS_FUNC_NOT_SUPPORTED;
  83
  84     slot_num = PCI_SLOT(dev->devfn);
  85     func_num = PCI_FUNC(dev->devfn);
  86     if (slot_num == 5) {
  87         /*
  88          *  This is Nile 4 and it will crash if we access it like other
  89          *   devices
  90          */
  91         nile4_out32(NILE4_PCI_BASE + where, val);
  92         return PCIBIOS_SUCCESSFUL;
  93     }
  94     base = nile4_pre_pci_access0(slot_num);
  95     *((volatile u32 *)(base + (func_num << 8) + (where & 0xfc))) = val;
  96     nile4_post_pci_access0();
  97     return PCIBIOS_SUCCESSFUL;
  98 }
  99
 100 static int nile4_pci_read_config_word(struct pci_dev *dev, int where, u16 *val)
 101 {
 102     int status;
 103     u32 result;
 104
 105     status = nile4_pci_read_config_dword(dev, where, &result);
 106     if (status != PCIBIOS_SUCCESSFUL)
 107         return status;
 108     if (where & 2)
 109         result >>= 16;
 110     *val = result & 0xffff;
 111     return PCIBIOS_SUCCESSFUL;
 112 }
 113
 114 static int nile4_pci_read_config_byte(struct pci_dev *dev, int where, u8 *val)
 115 {
 116     int status;
 117     u32 result;
 118
 119     status = nile4_pci_read_config_dword(dev, where, &result);
 120     if (status != PCIBIOS_SUCCESSFUL)
 121         return status;
 122     if (where & 1)
 123         result >>= 8;
 124     if (where & 2)
 125         result >>= 16;
 126     *val = result & 0xff;
 127     return PCIBIOS_SUCCESSFUL;
 128 }
 129
 130 static int nile4_pci_write_config_word(struct pci_dev *dev, int where, u16 val)
 131 {
 132     int status, shift = 0;
 133     u32 result;
 134
 135     status = nile4_pci_read_config_dword(dev, where, &result);
 136     if (status != PCIBIOS_SUCCESSFUL)
 137         return status;
 138     if (where & 2)
 139         shift += 16;
 140     result &= ~(0xffff << shift);
 141     result |= val << shift;
 142     return nile4_pci_write_config_dword(dev, where, result);
 143 }
 144
 145 static int nile4_pci_write_config_byte( struct pci_dev *dev, int where, u8 val)
 146 {
 147     int status, shift = 0;
 148     u32 result;
 149
 150     status = nile4_pci_read_config_dword(dev, where, &result);
 151     if (status != PCIBIOS_SUCCESSFUL)
 152         return status;
 153     if (where & 2)
 154         shift += 16;
 155     if (where & 1)
 156         shift += 8;
 157     result &= ~(0xff << shift);
 158     result |= val << shift;
 159     return nile4_pci_write_config_dword(dev, where, result);
 160 }
 161
 162 struct pci_ops nile4_pci_ops = {
 163     nile4_pci_read_config_byte,
 164     nile4_pci_read_config_word,
 165     nile4_pci_read_config_dword,
 166     nile4_pci_write_config_byte,
 167     nile4_pci_write_config_word,
 168     nile4_pci_write_config_dword
 169 };
 170
 171
 172 static void __init pcibios_claim_resources(struct list_head *bus_list)
 173 {
 174     struct list_head *ln, *dn;
 175     struct pci_bus *bus;
 176     struct pci_dev *dev;
 177     int idx;
 178
 179     for (ln = bus_list->next; ln != bus_list; ln = ln->next) {
 180         bus = pci_bus_b(ln);
 181         for (dn = bus->devices.next; dn != &bus->devices; dn = dn->next) {
 182             dev = pci_dev_b(dn);
 183             for (idx = 0; idx < PCI_NUM_RESOURCES; idx++) {
 184                 struct resource *r = &dev->resource[idx];
 185                 struct resource *pr;
 186                 if (!r->start)
 187                     continue;
 188                 pr = pci_find_parent_resource(dev, r);
 189                 if (!pr || request_resource(pr, r) < 0) {
 190                     printk(KERN_ERR "PCI: Address space collision on region %d of device %s\n", idx, dev->name);
 191                     /* We probably should disable the region, shouldn't we? */
 192                 }
 193             }
 194         }
 195         pcibios_claim_resources(&bus->children);
 196     }
 197 }
 198
 199
 200 void pcibios_init(void)
 201 {
 202     printk("PCI: Probing PCI hardware\n");
 203     ioport_resource.end = 0x1ffffff;
 204     pci_scan_bus(0, &nile4_pci_ops, NULL);
 205     pcibios_claim_resources(&pci_root_buses);
 206 }
 207
 208 void pcibios_fixup_bus(struct pci_bus *bus)
 209 {
 210     struct list_head *dn;
 211     struct pci_dev *dev;
 212     extern struct pci_dev *pci_pmu;     /* for LEDs D2 and D3 */
 213     int slot_num, func_num;
 214     u8 t8;
 215
 216     /*
 217      *  FIXME: PMON doesn't autoconfigure the PCI devices
 218      *         For now we just hardcode them for our configuration
 219      */
 220     printk("PCI: Configuring PCI devices (hardcoded)\n");
 221     for (dn = bus->devices.next; dn != &bus->devices; dn = dn->next) {
 222         dev = pci_dev_b(dn);
 223
 224         slot_num = PCI_SLOT(dev->devfn);
 225         func_num = PCI_FUNC(dev->devfn);
 226         printk("  Device %2d: ", slot_num);
 227         switch (slot_num) {
 228             case 0:
 229                 printk("[onboard] Acer Labs M1533 Aladdin IV\n");
 230                 dev->irq = nile4_to_irq(NILE4_INT_INTE);
 231                 break;
 232             case 1:
 233                 printk("[onboard] DEC DC21140\n");
 234                 dev->irq = nile4_to_irq(NILE4_INT_INTA);
 235                 dev->resource[0].start = 0x100000;
 236                 dev->resource[0].end = dev->resource[0].start+0x7f;
 237                 nile4_pci_write_config_dword(dev, PCI_BASE_ADDRESS_0,
 238                                              dev->resource[0].start);
 239                 dev->resource[1].start = 0x1000000;
 240                 dev->resource[1].end = dev->resource[1].start+0x7f;
 241                 nile4_pci_write_config_dword(dev, PCI_BASE_ADDRESS_0,
 242                                              dev->resource[1].start);
 243                 break;
 244             case 2:
 245                 printk("[slot 1]  Realtek 8029\n");
 246                 dev->irq = nile4_to_irq(NILE4_INT_INTA);
 247                 dev->resource[0].start = 0x800000;
 248                 dev->resource[0].end = dev->resource[0].start+0x1f;
 249                 nile4_pci_write_config_dword(dev, PCI_BASE_ADDRESS_0,
 250                                              dev->resource[0].start);
 251                 break;
 252             case 3:
 253                 printk("[slot 2]  DEC DC21140 (#2)\n");
 254                 dev->irq = nile4_to_irq(NILE4_INT_INTB);
 255                 dev->resource[0].start = 0x1000000;
 256                 dev->resource[0].end = dev->resource[0].start+0x7f;
 257                 nile4_pci_write_config_dword(dev, PCI_BASE_ADDRESS_0,
 258                                              dev->resource[0].start);
 259                 dev->resource[1].start = 0x4000000;
 260                 dev->resource[1].end = dev->resource[1].start+0x7f;
 261                 nile4_pci_write_config_dword(dev, PCI_BASE_ADDRESS_0,
 262                                              dev->resource[1].start);
 263                 break;
 264             case 4:
 265                 printk("[slot 3]  Promise Technology IDE UltraDMA/33");
 266                 printk(" or 3Com 3c905 :-)\n");
 267                 dev->irq = nile4_to_irq(NILE4_INT_INTC);
 268                 dev->resource[0].start = 0x1800000;
 269                 dev->resource[0].end = dev->resource[0].start+0x7fffff;
 270                 nile4_pci_write_config_dword(dev, PCI_BASE_ADDRESS_0,
 271                                              dev->resource[0].start);
 272                 break;
 273             case 5:
 274                 printk("[onboard] NEC Vrc-5074 Nile 4 Host Bridge\n");
 275                 /*
 276                  * Fixup so the serial driver can use the UART
 277                  */
 278                 dev->irq = nile4_to_irq(NILE4_INT_UART);
 279                 dev->resource[0].start = PHYSADDR(NILE4_BASE);
 280                 dev->resource[0].end = dev->resource[0].start+NILE4_SIZE-1;
 281                 dev->resource[0].flags = IORESOURCE_MEM |
 282                                          PCI_BASE_ADDRESS_MEM_TYPE_64;
 283
 284                 break;
 285             case 10:
 286                 printk("[onboard] Acer Labs M7101 PMU\n");
 287                 pci_pmu = dev;
 288                 /* Program the lines for LEDs D2 and D3 to output */
 289                 nile4_pci_read_config_byte(dev, 0x7d, &t8);
 290                 t8 |= 0xc0;
 291                 nile4_pci_write_config_byte(dev, 0x7d, t8);
 292                 /* Turn LEDs D2 and D3 off */
 293                 nile4_pci_read_config_byte(dev, 0x7e, &t8);
 294                 t8 |= 0xc0;
 295                 nile4_pci_write_config_byte(dev, 0x7e, t8);
 296                 break;
 297             case 13:
 298                 printk("[onboard] Acer Labs M5237 USB\n");
 299                 dev->irq = nile4_to_irq(NILE4_INT_INTE);
 300                 dev->resource[0].start = 0x1001000;
 301                 dev->resource[0].end = dev->resource[0].start+0xfff;
 302                 nile4_pci_write_config_dword(dev, PCI_BASE_ADDRESS_0,
 303                                              dev->resource[0].start);
 304                 break;
 305             default:
 306                 printk("\n");
 307                 break;
 308         }
 309     }
 310 }
 311
 312 char *pcibios_setup (char *str)
 313 {
 314     return str;
 315 }
 316
 317 void __init pcibios_update_resource(struct pci_dev *dev, struct resource *root,
 318                                     struct resource *res, int resource)
 319 {
 320     unsigned long where, size;
 321     u32 reg;
 322
 323     where = PCI_BASE_ADDRESS_0 + (resource * 4);
 324     size = res->end - res->start;
 325     pci_read_config_dword(dev, where, &reg);
 326     reg = (reg & size) | (((u32)(res->start - root->start)) & ~size);
 327     pci_write_config_dword(dev, where, reg);
 328 }
 329
 330 void __init pcibios_update_irq(struct pci_dev *dev, int irq)
 331 {
 332     pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
 333 }
 334
 335 void __init pcibios_fixup_pbus_ranges(struct pci_bus *bus,
 336                                       struct pbus_set_ranges_data *ranges)
 337 {
 338     ranges->io_start -= bus->resource[0]->start;
 339     ranges->io_end -= bus->resource[0]->start;
 340     ranges->mem_start -= bus->resource[1]->start;
 341     ranges->mem_end -= bus->resource[1]->start;
 342 }
 343
 344 int __init pcibios_enable_device(struct pci_dev *dev)
 345 {
 346     printk("pcibios_enable_device for %04x:%04x\n", dev->vendor, dev->device);
 347     panic("pcibios_enable_device: not yet implemented\n");
 348 }
 349
 350 void __init pcibios_align_resource(void *data, struct resource *res,
 351                                    unsigned long size)
 352 {}
 353
 354 struct pci_fixup pcibios_fixups[] = {};
 355