arch/mips/arc/console.c

   1 /*
   2  * console.c: SGI arcs console code.
   3  *
   4  * Copyright (C) 1996 David S. Miller (dm@sgi.com)
   5  * Compability with board caches, Ulf Carlsson
   6  *
   7  * $Id: console.c,v 1.3 1999/10/09 00:00:57 ralf Exp $
   8  */
   9 #include <linux/config.h>
  10 #include <linux/init.h>
  11 #include <asm/sgialib.h>
  12 #include <asm/bcache.h>
  13
  14 /* The romvec is not compatible with board caches.  Thus we disable it during
  15  * romvec action.  Since r4xx0.c is always compiled and linked with your kernel,
  16  * this shouldn't cause any harm regardless what MIPS processor you have.
  17  *
  18  * The romvec write and read functions seem to interfere with the serial lines
  19  * in some way. You should be careful with them.
  20  */
  21 extern struct bcache_ops *bcops;
  22
  23 #ifdef CONFIG_SGI_PROM_CONSOLE
  24 void prom_putchar(char c)
  25 #else
  26 void __init prom_putchar(char c)
  27 #endif
  28 {
  29         long cnt;
  30         char it = c;
  31
  32         bcops->bc_disable();
  33         romvec->write(1, &it, 1, &cnt);
  34         bcops->bc_enable();
  35 }
  36
  37 #ifdef CONFIG_SGI_PROM_CONSOLE
  38 char prom_getchar(void)
  39 #else
  40 char __init prom_getchar(void)
  41 #endif
  42 {
  43         long cnt;
  44         char c;
  45
  46         bcops->bc_disable();
  47         romvec->read(0, &c, 1, &cnt);
  48         bcops->bc_enable();
  49         return c;
  50 }