2 * Intel IO-APIC support for multi-Pentium hosts.
4 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs
20 #include <linux/irq.h>
21 #include <linux/interrupt.h>
22 #include <linux/init.h>
23 #include <linux/delay.h>
24 #include <linux/sched.h>
25 #include <linux/config.h>
26 #include <linux/smp_lock.h>
32 static spinlock_t ioapic_lock
= SPIN_LOCK_UNLOCKED
;
35 * # of IO-APICs and # of IRQ routing registers
38 int nr_ioapic_registers
[MAX_IO_APICS
];
40 /* I/O APIC entries */
41 struct mpc_config_ioapic mp_ioapics
[MAX_IO_APICS
];
43 /* # of MP IRQ source entries */
44 struct mpc_config_intsrc mp_irqs
[MAX_IRQ_SOURCES
];
46 /* MP IRQ source entries */
47 int mp_irq_entries
= 0;
49 /* non-0 if default (table-less) MP configuration */
50 int mpc_default_type
= 0;
53 * Rough estimation of how many shared IRQs there are, can
56 #define MAX_PLUS_SHARED_IRQS NR_IRQS
57 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
60 * This is performance-critical, we want to do it O(1)
62 * the indexing order of this array favors 1:1 mappings
63 * between pins and IRQs.
66 static struct irq_pin_list
{
68 } irq_2_pin
[PIN_MAP_SIZE
];
71 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
72 * shared ISA-space IRQs, so we have to support them. We are super
73 * fast in the common case, and fast for shared ISA-space IRQs.
75 static void add_pin_to_irq(unsigned int irq
, int apic
, int pin
)
77 static int first_free_entry
= NR_IRQS
;
78 struct irq_pin_list
*entry
= irq_2_pin
+ irq
;
81 entry
= irq_2_pin
+ entry
->next
;
83 if (entry
->pin
!= -1) {
84 entry
->next
= first_free_entry
;
85 entry
= irq_2_pin
+ entry
->next
;
86 if (++first_free_entry
>= PIN_MAP_SIZE
)
87 panic("io_apic.c: whoops");
93 #define __DO_ACTION(name,R,ACTION, FINAL) \
97 struct irq_pin_list *entry = irq_2_pin + irq; \
104 reg = io_apic_read(entry->apic, 0x10 + R + pin*2); \
106 io_apic_modify(entry->apic, reg); \
109 entry = irq_2_pin + entry->next; \
114 #define DO_ACTION(name,R,ACTION, FINAL) \
116 static void name##_IO_APIC_irq(unsigned int irq) \
117 __DO_ACTION(name,R,ACTION, FINAL)
119 DO_ACTION( __mask
, 0, |= 0x00010000, io_apic_sync(entry
->apic
))/* mask = 1 */
120 DO_ACTION( __unmask
, 0, &= 0xfffeffff, ) /* mask = 0 */
122 static void mask_IO_APIC_irq (unsigned int irq
)
126 spin_lock_irqsave(&ioapic_lock
, flags
);
127 __mask_IO_APIC_irq(irq
);
128 spin_unlock_irqrestore(&ioapic_lock
, flags
);
131 static void unmask_IO_APIC_irq (unsigned int irq
)
135 spin_lock_irqsave(&ioapic_lock
, flags
);
136 __unmask_IO_APIC_irq(irq
);
137 spin_unlock_irqrestore(&ioapic_lock
, flags
);
140 void clear_IO_APIC_pin(unsigned int apic
, unsigned int pin
)
142 struct IO_APIC_route_entry entry
;
145 * Disable it in the IO-APIC irq-routing table:
147 memset(&entry
, 0, sizeof(entry
));
149 io_apic_write(apic
, 0x10 + 2 * pin
, *(((int *)&entry
) + 0));
150 io_apic_write(apic
, 0x11 + 2 * pin
, *(((int *)&entry
) + 1));
153 static void clear_IO_APIC (void)
157 for (apic
= 0; apic
< nr_ioapics
; apic
++)
158 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++)
159 clear_IO_APIC_pin(apic
, pin
);
163 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
164 * specific CPU-side IRQs.
168 int pirq_entries
[MAX_PIRQS
];
170 int skip_ioapic_setup
= 0;
172 static int __init
ioapic_setup(char *str
)
174 extern int skip_ioapic_setup
; /* defined in arch/i386/kernel/smp.c */
176 skip_ioapic_setup
= 1;
180 __setup("noapic", ioapic_setup
);
182 static int __init
ioapic_pirq_setup(char *str
)
185 int ints
[MAX_PIRQS
+1];
187 get_options(str
, ARRAY_SIZE(ints
), ints
);
189 for (i
= 0; i
< MAX_PIRQS
; i
++)
190 pirq_entries
[i
] = -1;
193 printk("PIRQ redirection, working around broken MP-BIOS.\n");
195 if (ints
[0] < MAX_PIRQS
)
198 for (i
= 0; i
< max
; i
++) {
199 printk("... PIRQ%d -> IRQ %d\n", i
, ints
[i
+1]);
201 * PIRQs are mapped upside down, usually.
203 pirq_entries
[MAX_PIRQS
-i
-1] = ints
[i
+1];
208 __setup("pirq=", ioapic_pirq_setup
);
211 * Find the IRQ entry number of a certain pin.
213 static int __init
find_irq_entry(int apic
, int pin
, int type
)
217 for (i
= 0; i
< mp_irq_entries
; i
++)
218 if ( (mp_irqs
[i
].mpc_irqtype
== type
) &&
219 (mp_irqs
[i
].mpc_dstapic
== mp_ioapics
[apic
].mpc_apicid
) &&
220 (mp_irqs
[i
].mpc_dstirq
== pin
))
228 * Find the pin to which IRQ0 (ISA) is connected
230 static int __init
find_timer_pin(int type
)
234 for (i
= 0; i
< mp_irq_entries
; i
++) {
235 int lbus
= mp_irqs
[i
].mpc_srcbus
;
237 if ((mp_bus_id_to_type
[lbus
] == MP_BUS_ISA
||
238 mp_bus_id_to_type
[lbus
] == MP_BUS_EISA
) &&
239 (mp_irqs
[i
].mpc_irqtype
== type
) &&
240 (mp_irqs
[i
].mpc_srcbusirq
== 0x00))
242 return mp_irqs
[i
].mpc_dstirq
;
248 * Find a specific PCI IRQ entry.
249 * Not an __init, possibly needed by modules
251 static int __init
pin_2_irq(int idx
, int apic
, int pin
);
252 int IO_APIC_get_PCI_irq_vector(int bus
, int slot
, int pci_pin
)
254 int apic
, i
, best_guess
= -1;
256 for (i
= 0; i
< mp_irq_entries
; i
++) {
257 int lbus
= mp_irqs
[i
].mpc_srcbus
;
259 for (apic
= 0; apic
< nr_ioapics
; apic
++)
260 if (mp_ioapics
[apic
].mpc_apicid
== mp_irqs
[i
].mpc_dstapic
)
263 if ((apic
|| IO_APIC_IRQ(mp_irqs
[i
].mpc_dstirq
)) &&
264 (mp_bus_id_to_type
[lbus
] == MP_BUS_PCI
) &&
265 !mp_irqs
[i
].mpc_irqtype
&&
266 (bus
== mp_bus_id_to_pci_bus
[mp_irqs
[i
].mpc_srcbus
]) &&
267 (slot
== ((mp_irqs
[i
].mpc_srcbusirq
>> 2) & 0x1f))) {
268 int irq
= pin_2_irq(i
,apic
,mp_irqs
[i
].mpc_dstirq
);
270 if (pci_pin
== (mp_irqs
[i
].mpc_srcbusirq
& 3))
273 * Use the first all-but-pin matching entry as a
274 * best-guess fuzzy result for broken mptables.
284 * EISA Edge/Level control register, ELCR
286 static int __init
EISA_ELCR(unsigned int irq
)
289 unsigned int port
= 0x4d0 + (irq
>> 3);
290 return (inb(port
) >> (irq
& 7)) & 1;
292 printk("Broken MPtable reports ISA irq %d\n", irq
);
296 /* EISA interrupts are always polarity zero and can be edge or level
297 * trigger depending on the ELCR value. If an interrupt is listed as
298 * EISA conforming in the MP table, that means its trigger type must
299 * be read in from the ELCR */
301 #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].mpc_dstirq))
302 #define default_EISA_polarity(idx) (0)
304 /* ISA interrupts are always polarity zero edge triggered, even when
305 * listed as conforming in the MP table. */
307 #define default_ISA_trigger(idx) (0)
308 #define default_ISA_polarity(idx) (0)
310 static int __init
MPBIOS_polarity(int idx
)
312 int bus
= mp_irqs
[idx
].mpc_srcbus
;
316 * Determine IRQ line polarity (high active or low active):
318 switch (mp_irqs
[idx
].mpc_irqflag
& 3)
320 case 0: /* conforms, ie. bus-type dependent polarity */
322 switch (mp_bus_id_to_type
[bus
])
324 case MP_BUS_ISA
: /* ISA pin */
326 polarity
= default_ISA_polarity(idx
);
331 polarity
= default_EISA_polarity(idx
);
334 case MP_BUS_PCI
: /* PCI pin */
341 printk("broken BIOS!!\n");
348 case 1: /* high active */
353 case 2: /* reserved */
355 printk("broken BIOS!!\n");
359 case 3: /* low active */
364 default: /* invalid */
366 printk("broken BIOS!!\n");
374 static int __init
MPBIOS_trigger(int idx
)
376 int bus
= mp_irqs
[idx
].mpc_srcbus
;
380 * Determine IRQ trigger mode (edge or level sensitive):
382 switch ((mp_irqs
[idx
].mpc_irqflag
>>2) & 3)
384 case 0: /* conforms, ie. bus-type dependent */
386 switch (mp_bus_id_to_type
[bus
])
390 trigger
= default_ISA_trigger(idx
);
395 trigger
= default_EISA_trigger(idx
);
398 case MP_BUS_PCI
: /* PCI pin, level */
405 printk("broken BIOS!!\n");
417 case 2: /* reserved */
419 printk("broken BIOS!!\n");
428 default: /* invalid */
430 printk("broken BIOS!!\n");
438 static inline int irq_polarity(int idx
)
440 return MPBIOS_polarity(idx
);
443 static inline int irq_trigger(int idx
)
445 return MPBIOS_trigger(idx
);
448 static int __init
pin_2_irq(int idx
, int apic
, int pin
)
451 int bus
= mp_irqs
[idx
].mpc_srcbus
;
454 * Debugging check, we are in big trouble if this message pops up!
456 if (mp_irqs
[idx
].mpc_dstirq
!= pin
)
457 printk("broken BIOS or MPTABLE parser, ayiee!!\n");
459 switch (mp_bus_id_to_type
[bus
])
461 case MP_BUS_ISA
: /* ISA pin */
464 irq
= mp_irqs
[idx
].mpc_srcbusirq
;
467 case MP_BUS_PCI
: /* PCI pin */
470 * PCI IRQs are mapped in order
474 irq
+= nr_ioapic_registers
[i
++];
480 printk("unknown bus type %d.\n",bus
);
487 * PCI IRQ command line redirection. Yes, limits are hardcoded.
489 if ((pin
>= 16) && (pin
<= 23)) {
490 if (pirq_entries
[pin
-16] != -1) {
491 if (!pirq_entries
[pin
-16]) {
492 printk("disabling PIRQ%d\n", pin
-16);
494 irq
= pirq_entries
[pin
-16];
495 printk("using PIRQ%d -> IRQ %d\n",
503 static inline int IO_APIC_irq_trigger(int irq
)
507 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
508 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
509 idx
= find_irq_entry(apic
,pin
,mp_INT
);
510 if ((idx
!= -1) && (irq
== pin_2_irq(idx
,apic
,pin
)))
511 return irq_trigger(idx
);
515 * nonexistent IRQs are edge default
520 int irq_vector
[NR_IRQS
] = { IRQ0_TRAP_VECTOR
, 0 };
522 static int __init
assign_irq_vector(int irq
)
524 static int current_vector
= IRQ0_TRAP_VECTOR
, offset
= 0;
525 if (IO_APIC_VECTOR(irq
) > 0)
526 return IO_APIC_VECTOR(irq
);
527 if (current_vector
== 0xFF)
528 panic("ran out of interrupt sources!");
531 if (current_vector
== SYSCALL_VECTOR
)
534 if (current_vector
> 0xFF) {
536 current_vector
= IRQ0_TRAP_VECTOR
+ offset
;
539 IO_APIC_VECTOR(irq
) = current_vector
;
540 return current_vector
;
543 extern void (*interrupt
[NR_IRQS
])(void);
544 static struct hw_interrupt_type ioapic_level_irq_type
;
545 static struct hw_interrupt_type ioapic_edge_irq_type
;
547 void __init
setup_IO_APIC_irqs(void)
549 struct IO_APIC_route_entry entry
;
550 int apic
, pin
, idx
, irq
, first_notcon
= 1, vector
;
552 printk("init IO_APIC IRQs\n");
554 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
555 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
558 * add it to the IO-APIC irq-routing table:
560 memset(&entry
,0,sizeof(entry
));
562 entry
.delivery_mode
= dest_LowestPrio
;
563 entry
.dest_mode
= 1; /* logical delivery */
564 entry
.mask
= 0; /* enable IRQ */
565 entry
.dest
.logical
.logical_dest
= APIC_ALL_CPUS
;
567 idx
= find_irq_entry(apic
,pin
,mp_INT
);
570 printk(" IO-APIC (apicid-pin) %d-%d", mp_ioapics
[apic
].mpc_apicid
, pin
);
573 printk(", %d-%d", mp_ioapics
[apic
].mpc_apicid
, pin
);
577 entry
.trigger
= irq_trigger(idx
);
578 entry
.polarity
= irq_polarity(idx
);
580 if (irq_trigger(idx
)) {
583 entry
.dest
.logical
.logical_dest
= APIC_ALL_CPUS
;
586 irq
= pin_2_irq(idx
, apic
, pin
);
587 add_pin_to_irq(irq
, apic
, pin
);
589 if (!apic
&& !IO_APIC_IRQ(irq
))
592 if (IO_APIC_IRQ(irq
)) {
593 vector
= assign_irq_vector(irq
);
594 entry
.vector
= vector
;
596 if (IO_APIC_irq_trigger(irq
))
597 irq_desc
[irq
].handler
= &ioapic_level_irq_type
;
599 irq_desc
[irq
].handler
= &ioapic_edge_irq_type
;
601 set_intr_gate(vector
, interrupt
[irq
]);
603 if (!apic
&& (irq
< 16))
604 disable_8259A_irq(irq
);
606 io_apic_write(apic
, 0x11+2*pin
, *(((int *)&entry
)+1));
607 io_apic_write(apic
, 0x10+2*pin
, *(((int *)&entry
)+0));
612 printk(" not connected.\n");
616 * Set up the 8259A-master output pin as broadcast to all
619 void __init
setup_ExtINT_IRQ0_pin(unsigned int pin
, int vector
)
621 struct IO_APIC_route_entry entry
;
623 memset(&entry
,0,sizeof(entry
));
625 disable_8259A_irq(0);
627 apic_readaround(APIC_LVT0
);
628 apic_write(APIC_LVT0
, 0x00010700); // mask LVT0
633 * We use logical delivery to get the timer IRQ
636 entry
.dest_mode
= 1; /* logical delivery */
637 entry
.mask
= 0; /* unmask IRQ now */
638 entry
.dest
.logical
.logical_dest
= APIC_ALL_CPUS
;
639 entry
.delivery_mode
= dest_LowestPrio
;
642 entry
.vector
= vector
;
645 * The timer IRQ doesnt have to know that behind the
646 * scene we have a 8259A-master in AEOI mode ...
648 irq_desc
[0].handler
= &ioapic_edge_irq_type
;
651 * Add it to the IO-APIC irq-routing table:
653 io_apic_write(0, 0x10+2*pin
, *(((int *)&entry
)+0));
654 io_apic_write(0, 0x11+2*pin
, *(((int *)&entry
)+1));
659 void __init
UNEXPECTED_IO_APIC(void)
661 printk(" WARNING: unexpected IO-APIC, please mail\n");
662 printk(" to linux-smp@vger.rutgers.edu\n");
665 void __init
print_IO_APIC(void)
668 struct IO_APIC_reg_00 reg_00
;
669 struct IO_APIC_reg_01 reg_01
;
670 struct IO_APIC_reg_02 reg_02
;
672 printk("number of MP IRQ sources: %d.\n", mp_irq_entries
);
673 for (i
= 0; i
< nr_ioapics
; i
++)
674 printk("number of IO-APIC #%d registers: %d.\n", mp_ioapics
[i
].mpc_apicid
, nr_ioapic_registers
[i
]);
677 * We are a bit conservative about what we expect. We have to
678 * know about every hardware change ASAP.
680 printk("testing the IO APIC.......................\n");
682 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
684 *(int *)®_00
= io_apic_read(apic
, 0);
685 *(int *)®_01
= io_apic_read(apic
, 1);
686 if (reg_01
.version
>= 0x10)
687 *(int *)®_02
= io_apic_read(apic
, 2);
689 printk("\nIO APIC #%d......\n", mp_ioapics
[apic
].mpc_apicid
);
690 printk(".... register #00: %08X\n", *(int *)®_00
);
691 printk("....... : physical APIC id: %02X\n", reg_00
.ID
);
692 if (reg_00
.__reserved_1
|| reg_00
.__reserved_2
)
693 UNEXPECTED_IO_APIC();
695 printk(".... register #01: %08X\n", *(int *)®_01
);
696 printk("....... : max redirection entries: %04X\n", reg_01
.entries
);
697 if ( (reg_01
.entries
!= 0x0f) && /* older (Neptune) boards */
698 (reg_01
.entries
!= 0x17) && /* typical ISA+PCI boards */
699 (reg_01
.entries
!= 0x1b) && /* Compaq Proliant boards */
700 (reg_01
.entries
!= 0x1f) && /* dual Xeon boards */
701 (reg_01
.entries
!= 0x22) && /* bigger Xeon boards */
702 (reg_01
.entries
!= 0x2E) &&
703 (reg_01
.entries
!= 0x3F)
705 UNEXPECTED_IO_APIC();
707 printk("....... : IO APIC version: %04X\n", reg_01
.version
);
708 if ( (reg_01
.version
!= 0x01) && /* 82489DX IO-APICs */
709 (reg_01
.version
!= 0x10) && /* oldest IO-APICs */
710 (reg_01
.version
!= 0x11) && /* Pentium/Pro IO-APICs */
711 (reg_01
.version
!= 0x13) /* Xeon IO-APICs */
713 UNEXPECTED_IO_APIC();
714 if (reg_01
.__reserved_1
|| reg_01
.__reserved_2
)
715 UNEXPECTED_IO_APIC();
717 if (reg_01
.version
>= 0x10) {
718 printk(".... register #02: %08X\n", *(int *)®_02
);
719 printk("....... : arbitration: %02X\n", reg_02
.arbitration
);
720 if (reg_02
.__reserved_1
|| reg_02
.__reserved_2
)
721 UNEXPECTED_IO_APIC();
724 printk(".... IRQ redirection table:\n");
726 printk(" NR Log Phy ");
727 printk("Mask Trig IRR Pol Stat Dest Deli Vect: \n");
729 for (i
= 0; i
<= reg_01
.entries
; i
++) {
730 struct IO_APIC_route_entry entry
;
732 *(((int *)&entry
)+0) = io_apic_read(apic
, 0x10+i
*2);
733 *(((int *)&entry
)+1) = io_apic_read(apic
, 0x11+i
*2);
735 printk(" %02x %03X %02X ",
737 entry
.dest
.logical
.logical_dest
,
738 entry
.dest
.physical
.physical_dest
741 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
746 entry
.delivery_status
,
753 printk(KERN_DEBUG
"IRQ to pin mappings:\n");
754 for (i
= 0; i
< NR_IRQS
; i
++) {
755 struct irq_pin_list
*entry
= irq_2_pin
+ i
;
758 printk(KERN_DEBUG
"IRQ%d ", i
);
760 printk("-> %d", entry
->pin
);
763 entry
= irq_2_pin
+ entry
->next
;
768 printk(".................................... done.\n");
773 static void print_APIC_bitfield (int base
)
778 printk("0123456789abcdef0123456789abcdef\n");
779 for (i
= 0; i
< 8; i
++) {
780 v
= apic_read(base
+ i
*0x10);
781 for (j
= 0; j
< 32; j
++) {
791 void /*__init*/ print_local_APIC(void * dummy
)
793 unsigned int v
, ver
, maxlvt
;
795 printk("\nprinting local APIC contents on CPU#%d/%d:\n",
796 smp_processor_id(), hard_smp_processor_id());
797 v
= apic_read(APIC_ID
);
798 printk("... APIC ID: %08x (%01x)\n", v
, GET_APIC_ID(v
));
799 v
= apic_read(APIC_LVR
);
800 printk("... APIC VERSION: %08x\n", v
);
801 ver
= GET_APIC_VERSION(v
);
802 maxlvt
= get_maxlvt();
804 v
= apic_read(APIC_TASKPRI
);
805 printk("... APIC TASKPRI: %08x (%02x)\n", v
, v
& APIC_TPRI_MASK
);
807 if (APIC_INTEGRATED(ver
)) { /* !82489DX */
808 v
= apic_read(APIC_ARBPRI
);
809 printk("... APIC ARBPRI: %08x (%02x)\n", v
,
810 v
& APIC_ARBPRI_MASK
);
811 v
= apic_read(APIC_PROCPRI
);
812 printk("... APIC PROCPRI: %08x\n", v
);
815 v
= apic_read(APIC_EOI
);
816 printk("... APIC EOI: %08x\n", v
);
817 v
= apic_read(APIC_LDR
);
818 printk("... APIC LDR: %08x\n", v
);
819 v
= apic_read(APIC_DFR
);
820 printk("... APIC DFR: %08x\n", v
);
821 v
= apic_read(APIC_SPIV
);
822 printk("... APIC SPIV: %08x\n", v
);
824 printk("... APIC ISR field:\n");
825 print_APIC_bitfield(APIC_ISR
);
826 printk("... APIC TMR field:\n");
827 print_APIC_bitfield(APIC_TMR
);
828 printk("... APIC IRR field:\n");
829 print_APIC_bitfield(APIC_IRR
);
831 if (APIC_INTEGRATED(ver
)) { /* !82489DX */
833 * Due to the Pentium erratum 3AP.
836 apic_readaround(APIC_SPIV
); // not strictly necessery
837 apic_write(APIC_ESR
, 0);
839 v
= apic_read(APIC_ESR
);
840 printk("... APIC ESR: %08x\n", v
);
843 v
= apic_read(APIC_ICR
);
844 printk("... APIC ICR: %08x\n", v
);
845 v
= apic_read(APIC_ICR2
);
846 printk("... APIC ICR2: %08x\n", v
);
848 v
= apic_read(APIC_LVTT
);
849 printk("... APIC LVTT: %08x\n", v
);
851 if (maxlvt
> 3) { /* PC is LVT#4. */
852 v
= apic_read(APIC_LVTPC
);
853 printk("... APIC LVTPC: %08x\n", v
);
855 v
= apic_read(APIC_LVT0
);
856 printk("... APIC LVT0: %08x\n", v
);
857 v
= apic_read(APIC_LVT1
);
858 printk("... APIC LVT1: %08x\n", v
);
860 if (maxlvt
> 2) { /* ERR is LVT#3. */
861 v
= apic_read(APIC_LVTERR
);
862 printk("... APIC LVTERR: %08x\n", v
);
865 v
= apic_read(APIC_TMICT
);
866 printk("... APIC TMICT: %08x\n", v
);
867 v
= apic_read(APIC_TMCCT
);
868 printk("... APIC TMCCT: %08x\n", v
);
869 v
= apic_read(APIC_TDCR
);
870 printk("... APIC TDCR: %08x\n", v
);
874 void print_all_local_APICs (void)
876 smp_call_function(print_local_APIC
, NULL
, 1, 1);
877 print_local_APIC(NULL
);
880 static void __init
enable_IO_APIC(void)
882 struct IO_APIC_reg_01 reg_01
;
885 for (i
= 0; i
< PIN_MAP_SIZE
; i
++) {
886 irq_2_pin
[i
].pin
= -1;
887 irq_2_pin
[i
].next
= 0;
890 for (i
= 0; i
< MAX_PIRQS
; i
++)
891 pirq_entries
[i
] =- 1;
895 * PIC mode, enable symmetric IO mode in the IMCR.
897 printk("leaving PIC mode, enabling symmetric IO mode.\n");
903 * The number of IO-APIC IRQ registers (== #pins):
905 for (i
= 0; i
< nr_ioapics
; i
++) {
906 *(int *)®_01
= io_apic_read(i
, 1);
907 nr_ioapic_registers
[i
] = reg_01
.entries
+1;
911 * Do not trust the IO-APIC being empty at bootup
917 * Not an __init, needed by the reboot code
919 void disable_IO_APIC(void)
922 * Clear the IO-APIC before rebooting:
927 * Put it back into PIC mode (has an effect only on
928 * certain older boards)
931 printk("disabling symmetric IO mode, entering PIC mode.\n");
938 * function to set the IO-APIC physical IDs based on the
939 * values stored in the MPC table.
941 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
944 static void __init
setup_ioapic_ids_from_mpc (void)
946 struct IO_APIC_reg_00 reg_00
;
950 * Set the IOAPIC ID to the value stored in the MPC table.
952 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
954 /* Read the register 0 value */
955 *(int *)®_00
= io_apic_read(apic
, 0);
958 * Read the right value from the MPC table and
959 * write it into the ID register.
961 printk("...changing IO-APIC physical APIC ID to %d ...",
962 mp_ioapics
[apic
].mpc_apicid
);
965 * Sanity check, is the ID really free? Every APIC in the
966 * system must have a unique ID or we get lots of nice
967 * 'stuck on smp_invalidate_needed IPI wait' messages.
969 if (phys_cpu_present_map
& (1<<mp_ioapics
[apic
].mpc_apicid
))
970 panic("APIC ID %d already used",
971 mp_ioapics
[apic
].mpc_apicid
);
973 reg_00
.ID
= mp_ioapics
[apic
].mpc_apicid
;
974 io_apic_write(apic
, 0, *(int *)®_00
);
979 *(int *)®_00
= io_apic_read(apic
, 0);
980 if (reg_00
.ID
!= mp_ioapics
[apic
].mpc_apicid
)
981 panic("could not set ID!\n");
987 static void __init
construct_default_ISA_mptable(void)
990 const int bus_type
= (mpc_default_type
== 2 || mpc_default_type
== 3 ||
991 mpc_default_type
== 6) ? MP_BUS_EISA
: MP_BUS_ISA
;
993 for (i
= 0; i
< 16; i
++) {
997 mp_irqs
[pos
].mpc_irqtype
= mp_INT
;
998 mp_irqs
[pos
].mpc_irqflag
= 0; /* default */
999 mp_irqs
[pos
].mpc_srcbus
= 0;
1000 mp_irqs
[pos
].mpc_srcbusirq
= i
;
1001 mp_irqs
[pos
].mpc_dstapic
= 0;
1002 mp_irqs
[pos
].mpc_dstirq
= i
;
1005 mp_irq_entries
= pos
;
1006 mp_bus_id_to_type
[0] = bus_type
;
1009 * MP specification 1.4 defines some extra rules for default
1010 * configurations, fix them up here:
1012 switch (mpc_default_type
)
1016 * IRQ0 is not connected:
1018 mp_irqs
[0].mpc_irqtype
= mp_ExtINT
;
1024 mp_irqs
[0].mpc_dstirq
= 2;
1030 * There is a nasty bug in some older SMP boards, their mptable lies
1031 * about the timer IRQ. We do the following to work around the situation:
1033 * - timer IRQ defaults to IO-APIC IRQ
1034 * - if this function detects that timer IRQs are defunct, then we fall
1035 * back to ISA timer IRQs
1037 static int __init
timer_irq_works(void)
1039 unsigned int t1
= jiffies
;
1050 extern atomic_t nmi_counter
[NR_CPUS
];
1052 static int __init
nmi_irq_works(void)
1054 irq_cpustat_t tmp
[NR_CPUS
];
1057 memcpy(tmp
, irq_stat
, sizeof(tmp
));
1061 for (j
= 0; j
< smp_num_cpus
; j
++) {
1062 cpu
= cpu_logical_map(j
);
1063 if (atomic_read(&nmi_counter(cpu
)) - atomic_read(&tmp
[cpu
].__nmi_counter
) <= 3) {
1064 printk("CPU#%d NMI appears to be stuck.\n", cpu
);
1072 * In the SMP+IOAPIC case it might happen that there are an unspecified
1073 * number of pending IRQ events unhandled. These cases are very rare,
1074 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1075 * better to do it this way as thus we do not have to be aware of
1076 * 'pending' interrupts in the IRQ path, except at this point.
1079 * Edge triggered needs to resend any interrupt
1080 * that was delayed but this is now handled in the device
1083 #define enable_edge_ioapic_irq unmask_IO_APIC_irq
1085 static void disable_edge_ioapic_irq (unsigned int irq
) { /* nothing */ }
1088 * Starting up a edge-triggered IO-APIC interrupt is
1089 * nasty - we need to make sure that we get the edge.
1090 * If it is already asserted for some reason, we need
1091 * return 1 to indicate that is was pending.
1093 * This is not complete - we should be able to fake
1094 * an edge even if it isn't on the 8259A...
1097 static unsigned int startup_edge_ioapic_irq(unsigned int irq
)
1099 int was_pending
= 0;
1100 unsigned long flags
;
1102 spin_lock_irqsave(&ioapic_lock
, flags
);
1104 disable_8259A_irq(irq
);
1105 if (i8259A_irq_pending(irq
))
1108 __unmask_IO_APIC_irq(irq
);
1109 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1114 #define shutdown_edge_ioapic_irq disable_edge_ioapic_irq
1117 * Once we have recorded IRQ_PENDING already, we can mask the
1118 * interrupt for real. This prevents IRQ storms from unhandled
1121 static void ack_edge_ioapic_irq(unsigned int irq
)
1123 if ((irq_desc
[irq
].status
& (IRQ_PENDING
| IRQ_DISABLED
))
1124 == (IRQ_PENDING
| IRQ_DISABLED
))
1125 mask_IO_APIC_irq(irq
);
1129 static void end_edge_ioapic_irq (unsigned int i
) { /* nothing */ }
1133 * Level triggered interrupts can just be masked,
1134 * and shutting down and starting up the interrupt
1135 * is the same as enabling and disabling them -- except
1136 * with a startup need to return a "was pending" value.
1138 * Level triggered interrupts are special because we
1139 * do not touch any IO-APIC register while handling
1140 * them. We ack the APIC in the end-IRQ handler, not
1141 * in the start-IRQ-handler. Protection against reentrance
1142 * from the same interrupt is still provided, both by the
1143 * generic IRQ layer and by the fact that an unacked local
1144 * APIC does not accept IRQs.
1146 static unsigned int startup_level_ioapic_irq (unsigned int irq
)
1148 unmask_IO_APIC_irq(irq
);
1150 return 0; /* don't check for pending */
1153 #define shutdown_level_ioapic_irq mask_IO_APIC_irq
1154 #define enable_level_ioapic_irq unmask_IO_APIC_irq
1155 #define disable_level_ioapic_irq mask_IO_APIC_irq
1157 static void end_level_ioapic_irq (unsigned int i
)
1162 static void mask_and_ack_level_ioapic_irq (unsigned int i
) { /* nothing */ }
1164 static void set_ioapic_affinity (unsigned int irq
, unsigned long mask
)
1166 unsigned long flags
;
1168 * Only the first 8 bits are valid.
1172 spin_lock_irqsave(&ioapic_lock
, flags
);
1173 __DO_ACTION( target
, 1, = mask
, )
1174 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1178 * Level and edge triggered IO-APIC interrupts need different handling,
1179 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
1180 * handled with the level-triggered descriptor, but that one has slightly
1181 * more overhead. Level-triggered interrupts cannot be handled with the
1182 * edge-triggered handler, without risking IRQ storms and other ugly
1186 static struct hw_interrupt_type ioapic_edge_irq_type
= {
1188 startup_edge_ioapic_irq
,
1189 shutdown_edge_ioapic_irq
,
1190 enable_edge_ioapic_irq
,
1191 disable_edge_ioapic_irq
,
1192 ack_edge_ioapic_irq
,
1193 end_edge_ioapic_irq
,
1194 set_ioapic_affinity
,
1197 static struct hw_interrupt_type ioapic_level_irq_type
= {
1199 startup_level_ioapic_irq
,
1200 shutdown_level_ioapic_irq
,
1201 enable_level_ioapic_irq
,
1202 disable_level_ioapic_irq
,
1203 mask_and_ack_level_ioapic_irq
,
1204 end_level_ioapic_irq
,
1205 set_ioapic_affinity
,
1208 static inline void init_IO_APIC_traps(void)
1213 * NOTE! The local APIC isn't very good at handling
1214 * multiple interrupts at the same interrupt level.
1215 * As the interrupt level is determined by taking the
1216 * vector number and shifting that right by 4, we
1217 * want to spread these out a bit so that they don't
1218 * all fall in the same interrupt level.
1220 * Also, we've got to be careful not to trash gate
1221 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1223 for (irq
= 0; irq
< NR_IRQS
; irq
++) {
1224 if (IO_APIC_IRQ(irq
) && !IO_APIC_VECTOR(irq
)) {
1226 * Hmm.. We don't have an entry for this,
1227 * so default to an old-fashioned 8259
1228 * interrupt if we can..
1231 make_8259A_irq(irq
);
1233 /* Strange. Oh, well.. */
1234 irq_desc
[irq
].handler
= &no_irq_type
;
1239 static void ack_lapic_irq (unsigned int irq
)
1244 static void end_lapic_irq (unsigned int i
) { /* nothing */ }
1246 static struct hw_interrupt_type lapic_irq_type
= {
1248 NULL
, /* startup_irq() not used for IRQ0 */
1249 NULL
, /* shutdown_irq() not used for IRQ0 */
1250 NULL
, /* enable_irq() not used for IRQ0 */
1251 NULL
, /* disable_irq() not used for IRQ0 */
1256 static void enable_NMI_through_LVT0 (void * dummy
)
1258 apic_readaround(APIC_LVT0
);
1259 apic_write(APIC_LVT0
, 0x00000400); // unmask and set to NMI
1262 static void setup_nmi (void)
1265 * Dirty trick to enable the NMI watchdog ...
1266 * We put the 8259A master into AEOI mode and
1267 * unmask on all local APICs LVT0 as NMI.
1269 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
1270 * is from Maciej W. Rozycki - so we do not have to EOI from
1271 * the NMI handler or the timer interrupt.
1273 printk("activating NMI Watchdog ...");
1275 smp_call_function(enable_NMI_through_LVT0
, NULL
, 1, 1);
1276 enable_NMI_through_LVT0(NULL
);
1282 * This code may look a bit paranoid, but it's supposed to cooperate with
1283 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
1284 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
1285 * fanatically on his truly buggy board.
1287 static inline void check_timer(void)
1293 * get/set the timer IRQ vector:
1295 disable_8259A_irq(0);
1296 vector
= assign_irq_vector(0);
1297 set_intr_gate(vector
, interrupt
[0]);
1299 pin1
= find_timer_pin(mp_INT
);
1300 pin2
= find_timer_pin(mp_ExtINT
);
1302 printk("..TIMER: vector=%d pin1=%d pin2=%d\n", vector
, pin1
, pin2
);
1305 * Ok, does IRQ0 through the IOAPIC work?
1307 if (timer_irq_works()) {
1309 disable_8259A_irq(0);
1312 enable_8259A_irq(0);
1313 if (nmi_irq_works())
1320 printk("..MP-BIOS bug: 8254 timer not connected to IO-APIC\n");
1321 clear_IO_APIC_pin(0, pin1
);
1324 printk("...trying to set up timer (IRQ0) through the 8259A ... ");
1326 printk("\n..... (found pin %d) ...", pin2
);
1328 * legacy devices should be connected to IO APIC #0
1330 setup_ExtINT_IRQ0_pin(pin2
, vector
);
1331 if (timer_irq_works()) {
1335 if (nmi_irq_works())
1341 * Cleanup, just in case ...
1343 clear_IO_APIC_pin(0, pin2
);
1345 printk(" failed.\n");
1348 printk("timer doesnt work through the IO-APIC - disabling NMI Watchdog!\n");
1352 printk("...trying to set up timer as Virtual Wire IRQ...");
1354 disable_8259A_irq(0);
1355 irq_desc
[0].handler
= &lapic_irq_type
;
1356 init_8259A(1); // AEOI mode
1357 apic_readaround(APIC_LVT0
);
1358 apic_write(APIC_LVT0
, 0x00000000 | vector
); // Fixed mode
1359 enable_8259A_irq(0);
1361 if (timer_irq_works()) {
1362 printk(" works.\n");
1365 printk(" failed :(.\n");
1366 panic("IO-APIC + timer doesn't work! pester mingo@redhat.com");
1371 * IRQ's that are handled by the old PIC in all cases:
1372 * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
1373 * Linux doesn't really care, as it's not actually used
1374 * for any interrupt handling anyway.
1375 * - IRQ13 is the FPU error IRQ, and may be connected
1376 * directly from the FPU to the old PIC. Linux doesn't
1377 * really care, because Linux doesn't want to use IRQ13
1378 * anyway (exception 16 is the proper FPU error signal)
1380 * Additionally, something is definitely wrong with irq9
1383 #define PIC_IRQS ((1<<2)|(1<<13))
1385 void __init
setup_IO_APIC(void)
1389 io_apic_irqs
= ~PIC_IRQS
;
1390 printk("ENABLING IO-APIC IRQs\n");
1393 * If there are no explicit MP IRQ entries, it's either one of the
1394 * default configuration types or we are broken. In both cases it's
1395 * fine to set up most of the low 16 IO-APIC pins to ISA defaults.
1397 if (!mp_irq_entries
) {
1398 printk("no explicit IRQ entries, using default mptable\n");
1399 construct_default_ISA_mptable();
1403 * Set up the IO-APIC IRQ routing table by parsing the MP-BIOS
1406 setup_ioapic_ids_from_mpc();
1407 setup_IO_APIC_irqs();
1408 init_IO_APIC_traps();
1415 * This initializes the IO-APIC and APIC hardware if this is
1418 void IO_APIC_init_uniprocessor (void)
1420 if (!smp_found_config
)
1424 setup_APIC_clocks();