arch/alpha/kernel/sys_noritake.c

   1 /*
   2  *      linux/arch/alpha/kernel/sys_noritake.c
   3  *
   4  *      Copyright (C) 1995 David A Rusling
   5  *      Copyright (C) 1996 Jay A Estabrook
   6  *      Copyright (C) 1998, 1999 Richard Henderson
   7  *
   8  * Code supporting the NORITAKE (AlphaServer 1000A),
   9  * CORELLE (AlphaServer 800), and ALCOR Primo (AlphaStation 600A).
  10  */
  11
  12 #include <linux/config.h>
  13 #include <linux/kernel.h>
  14 #include <linux/types.h>
  15 #include <linux/mm.h>
  16 #include <linux/sched.h>
  17 #include <linux/pci.h>
  18 #include <linux/init.h>
  19
  20 #include <asm/ptrace.h>
  21 #include <asm/system.h>
  22 #include <asm/dma.h>
  23 #include <asm/irq.h>
  24 #include <asm/bitops.h>
  25 #include <asm/mmu_context.h>
  26 #include <asm/io.h>
  27 #include <asm/pgtable.h>
  28 #include <asm/core_apecs.h>
  29 #include <asm/core_cia.h>
  30
  31 #include "proto.h"
  32 #include "irq_impl.h"
  33 #include "pci_impl.h"
  34 #include "machvec_impl.h"
  35
  36 /* Note mask bit is true for ENABLED irqs.  */
  37 static int cached_irq_mask;
  38
  39 static inline void
  40 noritake_update_irq_hw(int irq, int mask)
  41 {
  42         int port = 0x54a;
  43         if (irq >= 16) mask >>= 16;
  44         if (irq >= 16) port = 0x54c;
  45         outw(mask, port);
  46 }
  47
  48 static void
  49 noritake_enable_irq(unsigned int irq)
  50 {
  51         noritake_update_irq_hw(irq, cached_irq_mask |= 1 << (irq - 16));
  52 }
  53
  54 static void
  55 noritake_disable_irq(unsigned int irq)
  56 {
  57         noritake_update_irq_hw(irq, cached_irq_mask &= ~(1 << (irq - 16)));
  58 }
  59
  60 static unsigned int
  61 noritake_startup_irq(unsigned int irq)
  62 {
  63         noritake_enable_irq(irq);
  64         return 0;
  65 }
  66
  67 static struct hw_interrupt_type noritake_irq_type = {
  68         typename:       "NORITAKE",
  69         startup:        noritake_startup_irq,
  70         shutdown:       noritake_disable_irq,
  71         enable:         noritake_enable_irq,
  72         disable:        noritake_disable_irq,
  73         ack:            noritake_disable_irq,
  74         end:            noritake_enable_irq,
  75 };
  76
  77 static void
  78 noritake_device_interrupt(unsigned long vector, struct pt_regs *regs)
  79 {
  80         unsigned long pld;
  81         unsigned int i;
  82
  83         /* Read the interrupt summary registers of NORITAKE */
  84         pld = (((unsigned long) inw(0x54c) << 32)
  85                | ((unsigned long) inw(0x54a) << 16)
  86                | ((unsigned long) inb(0xa0) << 8)
  87                | inb(0x20));
  88
  89         /*
  90          * Now for every possible bit set, work through them and call
  91          * the appropriate interrupt handler.
  92          */
  93         while (pld) {
  94                 i = ffz(~pld);
  95                 pld &= pld - 1; /* clear least bit set */
  96                 if (i < 16) {
  97                         isa_device_interrupt(vector, regs);
  98                 } else {
  99                         handle_irq(i, regs);
 100                 }
 101         }
 102 }
 103
 104 static void
 105 noritake_srm_device_interrupt(unsigned long vector, struct pt_regs * regs)
 106 {
 107         int irq;
 108
 109         irq = (vector - 0x800) >> 4;
 110
 111         /*
 112          * I really hate to do this, too, but the NORITAKE SRM console also
 113          * reports PCI vectors *lower* than I expected from the bit numbers
 114          * in the documentation.
 115          * But I really don't want to change the fixup code for allocation
 116          * of IRQs, nor the alpha_irq_mask maintenance stuff, both of which
 117          * look nice and clean now.
 118          * So, here's this additional grotty hack... :-(
 119          */
 120         if (irq >= 16)
 121                 irq = irq + 1;
 122
 123         handle_irq(irq, regs);
 124 }
 125
 126 static void __init
 127 noritake_init_irq(void)
 128 {
 129         long i;
 130
 131         if (alpha_using_srm)
 132                 alpha_mv.device_interrupt = noritake_srm_device_interrupt;
 133
 134         outw(0, 0x54a);
 135         outw(0, 0x54c);
 136
 137         for (i = 16; i < 48; ++i) {
 138                 irq_desc[i].status = IRQ_DISABLED | IRQ_LEVEL;
 139                 irq_desc[i].handler = &noritake_irq_type;
 140         }
 141
 142         init_i8259a_irqs();
 143         common_init_isa_dma();
 144 }
 145
 146
 147 /*
 148  * PCI Fixup configuration.
 149  *
 150  * Summary @ 0x542, summary register #1:
 151  * Bit      Meaning
 152  * 0        All valid ints from summary regs 2 & 3
 153  * 1        QLOGIC ISP1020A SCSI
 154  * 2        Interrupt Line A from slot 0
 155  * 3        Interrupt Line B from slot 0
 156  * 4        Interrupt Line A from slot 1
 157  * 5        Interrupt line B from slot 1
 158  * 6        Interrupt Line A from slot 2
 159  * 7        Interrupt Line B from slot 2
 160  * 8        Interrupt Line A from slot 3
 161  * 9        Interrupt Line B from slot 3
 162  *10        Interrupt Line A from slot 4
 163  *11        Interrupt Line B from slot 4
 164  *12        Interrupt Line A from slot 5
 165  *13        Interrupt Line B from slot 5
 166  *14        Interrupt Line A from slot 6
 167  *15        Interrupt Line B from slot 6
 168  *
 169  * Summary @ 0x544, summary register #2:
 170  * Bit      Meaning
 171  * 0        OR of all unmasked ints in SR #2
 172  * 1        OR of secondary bus ints
 173  * 2        Interrupt Line C from slot 0
 174  * 3        Interrupt Line D from slot 0
 175  * 4        Interrupt Line C from slot 1
 176  * 5        Interrupt line D from slot 1
 177  * 6        Interrupt Line C from slot 2
 178  * 7        Interrupt Line D from slot 2
 179  * 8        Interrupt Line C from slot 3
 180  * 9        Interrupt Line D from slot 3
 181  *10        Interrupt Line C from slot 4
 182  *11        Interrupt Line D from slot 4
 183  *12        Interrupt Line C from slot 5
 184  *13        Interrupt Line D from slot 5
 185  *14        Interrupt Line C from slot 6
 186  *15        Interrupt Line D from slot 6
 187  *
 188  * The device to slot mapping looks like:
 189  *
 190  * Slot     Device
 191  *  7       Intel PCI-EISA bridge chip
 192  *  8       DEC PCI-PCI bridge chip
 193  * 11       PCI on board slot 0
 194  * 12       PCI on board slot 1
 195  * 13       PCI on board slot 2
 196  *
 197  *
 198  * This two layered interrupt approach means that we allocate IRQ 16 and
 199  * above for PCI interrupts.  The IRQ relates to which bit the interrupt
 200  * comes in on.  This makes interrupt processing much easier.
 201  */
 202
 203 static int __init
 204 noritake_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
 205 {
 206         static char irq_tab[15][5] __initlocaldata = {
 207                 /*INT    INTA   INTB   INTC   INTD */
 208                 /* note: IDSELs 16, 17, and 25 are CORELLE only */
 209                 { 16+1,  16+1,  16+1,  16+1,  16+1},  /* IdSel 16,  QLOGIC */
 210                 {   -1,    -1,    -1,    -1,    -1},  /* IdSel 17, S3 Trio64 */
 211                 {   -1,    -1,    -1,    -1,    -1},  /* IdSel 18,  PCEB */
 212                 {   -1,    -1,    -1,    -1,    -1},  /* IdSel 19,  PPB  */
 213                 {   -1,    -1,    -1,    -1,    -1},  /* IdSel 20,  ???? */
 214                 {   -1,    -1,    -1,    -1,    -1},  /* IdSel 21,  ???? */
 215                 { 16+2,  16+2,  16+3,  32+2,  32+3},  /* IdSel 22,  slot 0 */
 216                 { 16+4,  16+4,  16+5,  32+4,  32+5},  /* IdSel 23,  slot 1 */
 217                 { 16+6,  16+6,  16+7,  32+6,  32+7},  /* IdSel 24,  slot 2 */
 218                 { 16+8,  16+8,  16+9,  32+8,  32+9},    /* IdSel 25,  slot 3 */
 219                 /* The following 5 are actually on PCI bus 1, which is
 220                    across the built-in bridge of the NORITAKE only.  */
 221                 { 16+1,  16+1,  16+1,  16+1,  16+1},  /* IdSel 16,  QLOGIC */
 222                 { 16+8,  16+8,  16+9,  32+8,  32+9},  /* IdSel 17,  slot 3 */
 223                 {16+10, 16+10, 16+11, 32+10, 32+11},  /* IdSel 18,  slot 4 */
 224                 {16+12, 16+12, 16+13, 32+12, 32+13},  /* IdSel 19,  slot 5 */
 225                 {16+14, 16+14, 16+15, 32+14, 32+15},  /* IdSel 20,  slot 6 */
 226         };
 227         const long min_idsel = 5, max_idsel = 19, irqs_per_slot = 5;
 228         return COMMON_TABLE_LOOKUP;
 229 }
 230
 231 static u8 __init
 232 noritake_swizzle(struct pci_dev *dev, u8 *pinp)
 233 {
 234         int slot, pin = *pinp;
 235
 236         if (dev->bus->number == 0) {
 237                 slot = PCI_SLOT(dev->devfn);
 238         }
 239         /* Check for the built-in bridge */
 240         else if (PCI_SLOT(dev->bus->self->devfn) == 8) {
 241                 slot = PCI_SLOT(dev->devfn) + 15; /* WAG! */
 242         }
 243         else
 244         {
 245                 /* Must be a card-based bridge.  */
 246                 do {
 247                         if (PCI_SLOT(dev->bus->self->devfn) == 8) {
 248                                 slot = PCI_SLOT(dev->devfn) + 15;
 249                                 break;
 250                         }
 251                         pin = bridge_swizzle(pin, PCI_SLOT(dev->devfn)) ;
 252
 253                         /* Move up the chain of bridges.  */
 254                         dev = dev->bus->self;
 255                         /* Slot of the next bridge.  */
 256                         slot = PCI_SLOT(dev->devfn);
 257                 } while (dev->bus->self);
 258         }
 259         *pinp = pin;
 260         return slot;
 261 }
 262
 263
 264 /*
 265  * The System Vectors
 266  */
 267
 268 #if defined(CONFIG_ALPHA_GENERIC) || !defined(CONFIG_ALPHA_PRIMO)
 269 struct alpha_machine_vector noritake_mv __initmv = {
 270         vector_name:            "Noritake",
 271         DO_EV4_MMU,
 272         DO_DEFAULT_RTC,
 273         DO_APECS_IO,
 274         DO_APECS_BUS,
 275         machine_check:          apecs_machine_check,
 276         max_dma_address:        ALPHA_MAX_DMA_ADDRESS,
 277         min_io_address:         EISA_DEFAULT_IO_BASE,
 278         min_mem_address:        APECS_AND_LCA_DEFAULT_MEM_BASE,
 279
 280         nr_irqs:                48,
 281         device_interrupt:       noritake_device_interrupt,
 282
 283         init_arch:              apecs_init_arch,
 284         init_irq:               noritake_init_irq,
 285         init_rtc:               common_init_rtc,
 286         init_pci:               common_init_pci,
 287         kill_arch:              NULL,
 288         pci_map_irq:            noritake_map_irq,
 289         pci_swizzle:            noritake_swizzle,
 290 };
 291 ALIAS_MV(noritake)
 292 #endif
 293
 294 #if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_PRIMO)
 295 struct alpha_machine_vector noritake_primo_mv __initmv = {
 296         vector_name:            "Noritake-Primo",
 297         DO_EV5_MMU,
 298         DO_DEFAULT_RTC,
 299         DO_CIA_IO,
 300         DO_CIA_BUS,
 301         machine_check:          cia_machine_check,
 302         max_dma_address:        ALPHA_MAX_DMA_ADDRESS,
 303         min_io_address:         EISA_DEFAULT_IO_BASE,
 304         min_mem_address:        CIA_DEFAULT_MEM_BASE,
 305
 306         nr_irqs:                48,
 307         device_interrupt:       noritake_device_interrupt,
 308
 309         init_arch:              cia_init_arch,
 310         init_irq:               noritake_init_irq,
 311         init_rtc:               common_init_rtc,
 312         init_pci:               common_init_pci,
 313         pci_map_irq:            noritake_map_irq,
 314         pci_swizzle:            noritake_swizzle,
 315 };
 316 ALIAS_MV(noritake_primo)
 317 #endif