drivers/usb/ohci.h

   1 #ifndef __LINUX_OHCI_H
   2 #define __LINUX_OHCI_H
   3
   4 /*
   5  * Open Host Controller Interface data structures and defines.
   6  *
   7  * (C) Copyright 1999 Gregory P. Smith <greg@electricrain.com>
   8  *
   9  * $Id: ohci.h,v 1.24 1999/05/16 10:18:26 greg Exp $
  10  */
  11
  12 #include <linux/list.h>
  13 #include <asm/io.h>
  14
  15 #include "usb.h"
  16
  17 struct ohci_ed;
  18
  19 /*
  20  * Each TD must be aligned on a 16-byte boundary.  From the OHCI v1.0 spec
  21  * it does not state that TDs must be contiguious in memory (due to the
  22  * use of the next_td field).  This gives us extra room at the end of a
  23  * TD for our own driver specific data.
  24  *
  25  * This structure's size must be a multiple of 16 bytes. ?? no way, I
  26  * don't see why.  Alignment should be all that matters.
  27  */
  28 struct ohci_td {
  29         /* OHCI Hardware fields */
  30         __u32 info;             /* TD status & type flags */
  31         __u32 cur_buf;          /* Current Buffer Pointer (bus address) */
  32         __u32 next_td;          /* Next TD Pointer (bus address) */
  33         __u32 buf_end;          /* Memory Buffer End Pointer (bus address) */
  34
  35         /* Driver specific fields */
  36         struct ohci_ed *ed;             /* address of the ED this TD is on */
  37         struct ohci_td *next_dl_td;     /* used during donelist processing */
  38         void *data;                     /* virt. address of the the buffer */
  39         usb_device_irq completed;       /* Completion handler routine */
  40         int hcd_flags;                  /* Flags for the HCD: */
  41                 /* bit0 = boolean: Is this TD allocated? */
  42                 /* bit1 = boolean: Is this a dummy (end of list) TD? */
  43
  44         /* User or Device class driver specific fields */
  45         void *dev_id;   /* user defined pointer passed to irq handler */
  46 } __attribute((aligned(16)));
  47
  48 #define OHCI_TD_ROUND   (1 << 18)       /* buffer rounding bit */
  49 #define OHCI_TD_D       (3 << 19)       /* direction of xfer: */
  50 #define OHCI_TD_D_IN    (2 << 19)
  51 #define OHCI_TD_D_OUT   (1 << 19)
  52 #define OHCI_TD_D_SETUP (0 << 19)
  53 #define td_set_dir_in(d)        ((d) ? OHCI_TD_D_IN : OHCI_TD_D_OUT )
  54 #define td_set_dir_out(d)       ((d) ? OHCI_TD_D_OUT : OHCI_TD_D_IN )
  55 #define OHCI_TD_IOC_DELAY (7 << 21)     /* frame delay allowed before int. */
  56 #define OHCI_TD_IOC_OFF (OHCI_TD_IOC_DELAY)     /* no interrupt on complete */
  57 #define OHCI_TD_DT      (3 << 24)       /* data toggle bits */
  58 #define TOGGLE_AUTO     (0 << 24)       /* automatic (from the ED) */
  59 #define TOGGLE_DATA0    (2 << 24)       /* force Data0 */
  60 #define TOGGLE_DATA1    (3 << 24)       /* force Data1 */
  61 #define td_force_toggle(b)      (((b) | 2) << 24)
  62 #define OHCI_TD_ERRCNT  (3 << 26)       /* error count */
  63 #define td_errorcount(td)       (((td).info >> 26) & 3)
  64 #define clear_td_errorcount(td) ((td)->info &= ~(__u32)OHCI_TD_ERRCNT)
  65 #define OHCI_TD_CC      (0xf << 28)     /* condition code */
  66 #define OHCI_TD_CC_GET(td_i) (((td_i) >> 28) & 0xf)
  67 #define OHCI_TD_CC_NEW  (OHCI_TD_CC)    /* set this on all unaccessed TDs! */
  68 #define td_cc_notaccessed(td)   (((td).info >> 29) == 7)
  69 #define td_cc_accessed(td)      (((td).info >> 29) != 7)
  70 #define td_cc_noerror(td)       ((((td).info) & OHCI_TD_CC) == 0)
  71 #define td_active(td)   (!td_cc_noerror((td)) && (td_errorcount((td)) < 3))
  72 #define td_done(td)     (td_cc_noerror((td)) || (td_errorcount((td)) == 3))
  73
  74 /*
  75  * Macros to use the td->hcd_flags field.
  76  */
  77 #define td_allocated(td)        ((td).hcd_flags & 1)
  78 #define allocate_td(td)         ((td)->hcd_flags |= 1)
  79 #define ohci_free_td(td)        ((td)->hcd_flags &= ~(__u32)1)
  80
  81 #define td_dummy(td)            ((td).hcd_flags & 2)
  82 #define make_dumb_td(td)        ((td)->hcd_flags |= 2)
  83 #define clear_dumb_td(td)       ((td)->hcd_flags &= ~(__u32)2)
  84
  85
  86 /*
  87  * The endpoint descriptors also requires 16-byte alignment
  88  */
  89 struct ohci_ed {
  90         /* OHCI hardware fields */
  91         __u32 status;
  92         __u32 tail_td;  /* TD Queue tail pointer */
  93         __u32 _head_td; /* TD Queue head pointer, toggle carry & halted bits */
  94         __u32 next_ed;  /* Next ED */
  95 } __attribute((aligned(16)));
  96
  97 /* get the head_td */
  98 #define ed_head_td(ed)  ((ed)->_head_td & 0xfffffff0)
  99
 100 /* save the carry & halted flag while setting the head_td */
 101 #define set_ed_head_td(ed, td)  ((ed)->_head_td = (td) | ((ed)->_head_td & 3))
 102
 103 /* Control the ED's halted flag */
 104 #define ohci_halt_ed(ed)        ((ed)->_head_td |= 1)
 105 #define ohci_unhalt_ed(ed)      ((ed)->_head_td &= ~(__u32)1)
 106 #define ohci_ed_halted(ed)      ((ed)->_head_td & 1)
 107
 108 #define OHCI_ED_SKIP    (1 << 14)
 109 #define OHCI_ED_MPS     (0x7ff << 16)
 110 /* FIXME: should cap at the USB max packet size [0x4ff] */
 111 #define ed_set_maxpacket(s)     (((s) << 16) & OHCI_ED_MPS)
 112 #define OHCI_ED_F_NORM  (0)
 113 #define OHCI_ED_F_ISOC  (1 << 15)
 114 #define ed_set_type_isoc(i)     ((i) ? OHCI_ED_F_ISOC : OHCI_ED_F_NORM)
 115 #define OHCI_ED_S_LOW   (1 << 13)
 116 #define OHCI_ED_S_HIGH  (0)
 117 #define ed_set_speed(s)         ((s) ? OHCI_ED_S_LOW : OHCI_ED_S_HIGH)
 118 #define OHCI_ED_D       (3 << 11)
 119 #define OHCI_ED_D_IN    (2 << 11)
 120 #define OHCI_ED_D_OUT   (1 << 11)
 121 #define ed_set_dir_in(d)        ((d) ? OHCI_ED_D_IN : OHCI_ED_D_OUT)
 122 #define ed_set_dir_out(d)       ((d) ? OHCI_ED_D_OUT : OHCI_ED_D_IN)
 123 #define OHCI_ED_EN      (0xf << 7)
 124 #define OHCI_ED_FA      (0x7f)
 125
 126
 127 /* NOTE: bits 27-31 of the status dword are reserved for the HCD */
 128 /*
 129  * We'll use this status flag for to mark if an ED is in use by the
 130  * driver or not.  If the bit is set, it is being used.
 131  */
 132 #define ED_ALLOCATED    (1 << 31)
 133 #define ed_allocated(ed)        ((ed).status & ED_ALLOCATED)
 134 #define allocate_ed(ed)         ((ed)->status |= ED_ALLOCATED)
 135
 136 /*
 137  * The HCCA (Host Controller Communications Area) is a 256 byte
 138  * structure defined in the OHCI spec. that the host controller is
 139  * told the base address of.  It must be 256-byte aligned.
 140  */
 141 #define NUM_INTS 32     /* part of the OHCI standard */
 142 struct ohci_hcca {
 143         __u32   int_table[NUM_INTS];    /* Interrupt ED table */
 144         __u16   frame_no;               /* current frame number */
 145         __u16   pad1;                   /* set to 0 on each frame_no change */
 146         __u32   donehead;               /* info returned for an interrupt */
 147         u8      reserved_for_hc[116];
 148 } __attribute((aligned(256)));
 149
 150 /*
 151  * The TD entries here are pre-allocated as Linus did with his simple
 152  * UHCI implementation.  With the current state of this driver that
 153  * shouldn't be a problem.  However if someone ever connects 127
 154  * supported devices to this driver and tries to use them all at once:
 155  *      a)  They're insane!
 156  *      b)  They should code in dynamic allocation
 157  */
 158 struct ohci;
 159
 160 /*
 161  *  Warning: These constants must not be so large as to cause the
 162  *  ohci_device structure to exceed one 4096 byte page.  Or "weird
 163  *  things will happen" as the alloc_ohci() function assumes that
 164  *  its less than one page.  (FIXME)
 165  */
 166 #define NUM_TDS 32              /* num of preallocated transfer descriptors */
 167 #define DATA_BUF_LEN 16         /* num of unsigned long's for the data buf */
 168
 169 /*
 170  * For this "simple" driver we only support a single ED for each
 171  * polling rate.
 172  *
 173  * Later on this driver should be extended to use a full tree of EDs
 174  * so that there can be 32 different 32ms polling frames, etc.
 175  * Individual devices shouldn't need as many as the root hub in that
 176  * case; complicating how things are done at the moment.
 177  *
 178  * Bulk and Control transfers hang off of their own ED lists.
 179  */
 180 #define NUM_EDS 16              /* num of preallocated endpoint descriptors */
 181
 182 #define ohci_to_usb(ohci)       ((ohci)->usb)
 183 #define usb_to_ohci(usb)        ((struct ohci_device *)(usb)->hcpriv)
 184
 185 /* The usb_device must be first! */
 186 struct ohci_device {
 187         struct usb_device       *usb;
 188
 189         struct ohci             *ohci;
 190         struct ohci_hcca        *hcca;          /* OHCI mem. mapped IO area */
 191
 192         struct ohci_ed          ed[NUM_EDS];    /* Endpoint Descriptors */
 193         struct ohci_td          td[NUM_TDS];    /* Transfer Descriptors */
 194
 195         unsigned long           data[DATA_BUF_LEN];
 196 };
 197
 198 /* .... */
 199
 200 /*
 201  * These are the index of the placeholder EDs for the root hub to
 202  * build the interrupt transfer ED tree out of.
 203  */
 204 #define ED_INT_1        0
 205 #define ED_INT_2        1
 206 #define ED_INT_4        2
 207 #define ED_INT_8        3
 208 #define ED_INT_16       4
 209 #define ED_INT_32       5
 210 #define ED_ISO          ED_INT_1        /* same as 1ms interrupt queue */
 211
 212 /*
 213  * Given a period p in ms, convert it to the closest endpoint
 214  * interrupt frequency; rounding down.  This is a gross macro.
 215  * Feel free to toss it for actual code. (gasp!)
 216  */
 217 #define ms_to_ed_int(p) \
 218         ((p >= 32) ? ED_INT_32 : \
 219          ((p & 16) ? ED_INT_16 : \
 220           ((p & 8) ? ED_INT_8 : \
 221            ((p & 4) ? ED_INT_4 : \
 222             ((p & 2) ? ED_INT_2 : \
 223              ED_INT_1)))))  /* hmm.. scheme or lisp anyone? */
 224
 225 /*
 226  * This is the maximum number of root hub ports.  I don't think we'll
 227  * ever see more than two as that's the space available on an ATX
 228  * motherboard's case, but it could happen.  The OHCI spec allows for
 229  * up to 15... (which is insane given that they each need to supply up
 230  * to 500ma; that would be 7.5 amps!).  I have seen a PCI card with 4
 231  * downstream ports on it.
 232  *
 233  * Although I suppose several "ports" could be connected directly to
 234  * internal laptop devices such as a keyboard, mouse, camera and
 235  * serial/parallel ports.  hmm...  That'd be neat.
 236  */
 237 #define MAX_ROOT_PORTS  15      /* maximum OHCI root hub ports */
 238
 239 /*
 240  * This is the structure of the OHCI controller's memory mapped I/O
 241  * region.  This is Memory Mapped I/O.  You must use the readl() and
 242  * writel() macros defined in asm/io.h to access these!!
 243  */
 244 struct ohci_regs {
 245         /* control and status registers */
 246         __u32   revision;
 247         __u32   control;
 248         __u32   cmdstatus;
 249         __u32   intrstatus;
 250         __u32   intrenable;
 251         __u32   intrdisable;
 252         /* memory pointers */
 253         __u32   hcca;
 254         __u32   ed_periodcurrent;
 255         __u32   ed_controlhead;
 256         __u32   ed_controlcurrent;
 257         __u32   ed_bulkhead;
 258         __u32   ed_bulkcurrent;
 259         __u32   current_donehead; /* The driver should get this from the HCCA */
 260         /* frame counters */
 261         __u32   fminterval;
 262         __u32   fmremaining;
 263         __u32   fmnumber;
 264         __u32   periodicstart;
 265         __u32   lsthresh;
 266         /* Root hub ports */
 267         struct  ohci_roothub_regs {
 268                 __u32   a;
 269                 __u32   b;
 270                 __u32   status;
 271                 __u32   portstatus[MAX_ROOT_PORTS];
 272         } roothub;
 273 } __attribute((aligned(32)));
 274
 275 /*
 276  * These are used by internal ED managing functions as a
 277  * parameter to state the type of ED to deal with (when it matters).
 278  */
 279 #define HCD_ED_ISOC     (0)
 280 #define HCD_ED_INT      (1)
 281 #define HCD_ED_CONTROL  (2)
 282 #define HCD_ED_BULK     (3)
 283
 284 /*
 285  * Read a MMIO register and re-write it after ANDing with (m)
 286  */
 287 #define writel_mask(m, a) writel( (readl((unsigned long)(a))) & (__u32)(m), (unsigned long)(a) )
 288
 289 /*
 290  * Read a MMIO register and re-write it after ORing with (b)
 291  */
 292 #define writel_set(b, a) writel( (readl((unsigned long)(a))) | (__u32)(b), (unsigned long)(a) )
 293
 294
 295 #define PORT_CCS        (1)             /* port current connect status */
 296 #define PORT_PES        (1 << 1)        /* port enable status */
 297 #define PORT_PSS        (1 << 2)        /* port suspend status */
 298 #define PORT_POCI       (1 << 3)        /* port overcurrent indicator */
 299 #define PORT_PRS        (1 << 4)        /* port reset status */
 300 #define PORT_PPS        (1 << 8)        /* port power status */
 301 #define PORT_LSDA       (1 << 9)        /* port low speed dev. attached */
 302 #define PORT_CSC        (1 << 16)       /* port connect status change */
 303 #define PORT_PESC       (1 << 17)       /* port enable status change */
 304 #define PORT_PSSC       (1 << 18)       /* port suspend status change */
 305 #define PORT_OCIC       (1 << 19)       /* port over current indicator chg */
 306 #define PORT_PRSC       (1 << 20)       /* port reset status change */
 307
 308 /*
 309  * Root Hub status register masks
 310  */
 311 #define OHCI_ROOT_LPS   (1)             /* turn off root hub ports power */
 312 #define OHCI_ROOT_OCI   (1 << 1)        /* Overcurrent Indicator */
 313 #define OHCI_ROOT_DRWE  (1 << 15)       /* Device remote wakeup enable */
 314 #define OHCI_ROOT_LPSC  (1 << 16)       /* turn on root hub ports power */
 315 #define OHCI_ROOT_OCIC  (1 << 17)       /* Overcurrent indicator change */
 316 #define OHCI_ROOT_CRWE  (1 << 31)       /* Clear RemoteWakeupEnable */
 317
 318 /*
 319  * Root hub A register masks
 320  */
 321 #define OHCI_ROOT_A_NPS (1 << 9)
 322 #define OHCI_ROOT_A_PSM (1 << 8)
 323
 324 /*
 325  * Root hub B register masks
 326  */
 327
 328 /*
 329  * Interrupt register masks
 330  */
 331 #define OHCI_INTR_SO    (1)
 332 #define OHCI_INTR_WDH   (1 << 1)
 333 #define OHCI_INTR_SF    (1 << 2)
 334 #define OHCI_INTR_RD    (1 << 3)
 335 #define OHCI_INTR_UE    (1 << 4)
 336 #define OHCI_INTR_FNO   (1 << 5)
 337 #define OHCI_INTR_RHSC  (1 << 6)
 338 #define OHCI_INTR_OC    (1 << 30)
 339 #define OHCI_INTR_MIE   (1 << 31)
 340
 341 /*
 342  * Control register masks
 343  */
 344 #define OHCI_USB_OPER           (2 << 6)
 345 #define OHCI_USB_SUSPEND        (3 << 6)
 346 #define OHCI_USB_PLE            (1 << 2)  /* Periodic (interrupt) list enable */
 347 #define OHCI_USB_IE             (1 << 3)  /* Isochronous list enable */
 348 #define OHCI_USB_CLE            (1 << 4)  /* Control list enable */
 349 #define OHCI_USB_BLE            (1 << 5)  /* Bulk list enable */
 350
 351 /*
 352  * Command status register masks
 353  */
 354 #define OHCI_CMDSTAT_HCR        (1)
 355 #define OHCI_CMDSTAT_CLF        (1 << 1)
 356 #define OHCI_CMDSTAT_BLF        (1 << 2)
 357 #define OHCI_CMDSTAT_OCR        (1 << 3)
 358 #define OHCI_CMDSTAT_SOC        (3 << 16)
 359
 360 /*
 361  * This is the full ohci controller description
 362  *
 363  * Note how the "proper" USB information is just
 364  * a subset of what the full implementation needs. (Linus)
 365  */
 366 struct ohci {
 367         int irq;
 368         struct ohci_regs *regs;                 /* OHCI controller's memory */
 369         struct usb_bus *bus;
 370         struct list_head interrupt_list;        /* List of interrupt active TDs for this OHCI */
 371 };
 372
 373 #define OHCI_TIMER              /* enable the OHCI timer */
 374 #define OHCI_TIMER_FREQ (234)   /* ms between each root hub status check */
 375
 376 #undef OHCI_RHSC_INT            /* Don't use root hub status interrupts! */
 377
 378 /* Debugging code [ohci-debug.c] */
 379 void show_ohci_ed(struct ohci_ed *ed);
 380 void show_ohci_td(struct ohci_td *td);
 381 void show_ohci_status(struct ohci *ohci);
 382 void show_ohci_device(struct ohci_device *dev);
 383 void show_ohci_hcca(struct ohci_hcca *hcca);
 384
 385 #endif
 386 /* vim:sw=8
 387  */