arch/sparc/math-emu/math.c

   1 /*
   2  * arch/sparc/math-emu/math.c
   3  *
   4  * Copyright (C) 1998 Peter Maydell (pmaydell@chiark.greenend.org.uk)
   5  * Copyright (C) 1997, 1999 Jakub Jelinek (jj@ultra.linux.cz)
   6  * Copyright (C) 1999 David S. Miller (davem@redhat.com)
   7  *
   8  * This is a good place to start if you're trying to understand the
   9  * emulation code, because it's pretty simple. What we do is
  10  * essentially analyse the instruction to work out what the operation
  11  * is and which registers are involved. We then execute the appropriate
  12  * FXXXX function. [The floating point queue introduces a minor wrinkle;
  13  * see below...]
  14  * The fxxxxx.c files each emulate a single insn. They look relatively
  15  * simple because the complexity is hidden away in an unholy tangle
  16  * of preprocessor macros.
  17  *
  18  * The first layer of macros is single.h, double.h, quad.h. Generally
  19  * these files define macros for working with floating point numbers
  20  * of the three IEEE formats. FP_ADD_D(R,A,B) is for adding doubles,
  21  * for instance. These macros are usually defined as calls to more
  22  * generic macros (in this case _FP_ADD(D,2,R,X,Y) where the number
  23  * of machine words required to store the given IEEE format is passed
  24  * as a parameter. [double.h and co check the number of bits in a word
  25  * and define FP_ADD_D & co appropriately].
  26  * The generic macros are defined in op-common.h. This is where all
  27  * the grotty stuff like handling NaNs is coded. To handle the possible
  28  * word sizes macros in op-common.h use macros like _FP_FRAC_SLL_##wc()
  29  * where wc is the 'number of machine words' parameter (here 2).
  30  * These are defined in the third layer of macros: op-1.h, op-2.h
  31  * and op-4.h. These handle operations on floating point numbers composed
  32  * of 1,2 and 4 machine words respectively. [For example, on sparc64
  33  * doubles are one machine word so macros in double.h eventually use
  34  * constructs in op-1.h, but on sparc32 they use op-2.h definitions.]
  35  * soft-fp.h is on the same level as op-common.h, and defines some
  36  * macros which are independent of both word size and FP format.
  37  * Finally, sfp-machine.h is the machine dependent part of the
  38  * code: it defines the word size and what type a word is. It also
  39  * defines how _FP_MUL_MEAT_t() maps to _FP_MUL_MEAT_n_* : op-n.h
  40  * provide several possible flavours of multiply algorithm, most
  41  * of which require that you supply some form of asm or C primitive to
  42  * do the actual multiply. (such asm primitives should be defined
  43  * in sfp-machine.h too). udivmodti4.c is the same sort of thing.
  44  *
  45  * There may be some errors here because I'm working from a
  46  * SPARC architecture manual V9, and what I really want is V8...
  47  * Also, the insns which can generate exceptions seem to be a
  48  * greater subset of the FPops than for V9 (for example, FCMPED
  49  * has to be emulated on V8). So I think I'm going to have
  50  * to emulate them all just to be on the safe side...
  51  *
  52  * Emulation routines originate from soft-fp package, which is
  53  * part of glibc and has appropriate copyrights in it (allegedly).
  54  *
  55  * NB: on sparc int == long == 4 bytes, long long == 8 bytes.
  56  * Most bits of the kernel seem to go for long rather than int,
  57  * so we follow that practice...
  58  */
  59
  60 /* TODO:
  61  * fpsave() saves the FP queue but fpload() doesn't reload it.
  62  * Therefore when we context switch or change FPU ownership
  63  * we have to check to see if the queue had anything in it and
  64  * emulate it if it did. This is going to be a pain.
  65  */
  66
  67 #include <linux/types.h>
  68 #include <linux/sched.h>
  69 #include <linux/mm.h>
  70 #include <asm/uaccess.h>
  71
  72 #include "sfp-util.h"
  73 #include "soft-fp.h"
  74
  75 #define FLOATFUNC(x) extern int x(void *,void *,void *)
  76
  77 /* The Vn labels indicate what version of the SPARC architecture gas thinks
  78  * each insn is. This is from the binutils source :->
  79  */
  80 /* quadword instructions */
  81 FLOATFUNC(FSQRTQ);                                /* v8 */
  82 FLOATFUNC(FADDQ);                                 /* v8 */
  83 FLOATFUNC(FSUBQ);                                 /* v8 */
  84 FLOATFUNC(FMULQ);                                 /* v8 */
  85 FLOATFUNC(FDIVQ);                                 /* v8 */
  86 FLOATFUNC(FDMULQ);                                /* v8 */
  87 FLOATFUNC(FQTOS);                                 /* v8 */
  88 FLOATFUNC(FQTOD);                                 /* v8 */
  89 FLOATFUNC(FITOQ);                                 /* v8 */
  90 FLOATFUNC(FSTOQ);                                 /* v8 */
  91 FLOATFUNC(FDTOQ);                                 /* v8 */
  92 FLOATFUNC(FQTOI);                                 /* v8 */
  93 FLOATFUNC(FCMPQ);                                 /* v8 */
  94 FLOATFUNC(FCMPEQ);                                /* v8 */
  95 /* single/double instructions (subnormal): should all work */
  96 FLOATFUNC(FSQRTS);                                /* v7 */
  97 FLOATFUNC(FSQRTD);                                /* v7 */
  98 FLOATFUNC(FADDS);                                 /* v6 */
  99 FLOATFUNC(FADDD);                                 /* v6 */
 100 FLOATFUNC(FSUBS);                                 /* v6 */
 101 FLOATFUNC(FSUBD);                                 /* v6 */
 102 FLOATFUNC(FMULS);                                 /* v6 */
 103 FLOATFUNC(FMULD);                                 /* v6 */
 104 FLOATFUNC(FDIVS);                                 /* v6 */
 105 FLOATFUNC(FDIVD);                                 /* v6 */
 106 FLOATFUNC(FSMULD);                                /* v8 */
 107 FLOATFUNC(FDTOS);                                 /* v6 */
 108 FLOATFUNC(FSTOD);                                 /* v6 */
 109 FLOATFUNC(FSTOI);                                 /* v6 */
 110 FLOATFUNC(FDTOI);                                 /* v6 */
 111 FLOATFUNC(FABSS);                                 /* v6 */
 112 FLOATFUNC(FCMPS);                                 /* v6 */
 113 FLOATFUNC(FCMPES);                                /* v6 */
 114 FLOATFUNC(FCMPD);                                 /* v6 */
 115 FLOATFUNC(FCMPED);                                /* v6 */
 116 FLOATFUNC(FMOVS);                                 /* v6 */
 117 FLOATFUNC(FNEGS);                                 /* v6 */
 118 FLOATFUNC(FITOS);                                 /* v6 */
 119 FLOATFUNC(FITOD);                                 /* v6 */
 120
 121 #define FSR_TEM_SHIFT   23UL
 122 #define FSR_TEM_MASK    (0x1fUL << FSR_TEM_SHIFT)
 123 #define FSR_AEXC_SHIFT  5UL
 124 #define FSR_AEXC_MASK   (0x1fUL << FSR_AEXC_SHIFT)
 125 #define FSR_CEXC_SHIFT  0UL
 126 #define FSR_CEXC_MASK   (0x1fUL << FSR_CEXC_SHIFT)
 127
 128 static int do_one_mathemu(u32 insn, unsigned long *fsr, unsigned long *fregs);
 129
 130 /* Unlike the Sparc64 version (which has a struct fpustate), we
 131  * pass the taskstruct corresponding to the task which currently owns the
 132  * FPU. This is partly because we don't have the fpustate struct and
 133  * partly because the task owning the FPU isn't always current (as is
 134  * the case for the Sparc64 port). This is probably SMP-related...
 135  * This function returns 1 if all queued insns were emulated successfully.
 136  * The test for unimplemented FPop in kernel mode has been moved into
 137  * kernel/traps.c for simplicity.
 138  */
 139 int do_mathemu(struct pt_regs *regs, struct task_struct *fpt)
 140 {
 141         /* regs->pc isn't necessarily the PC at which the offending insn is sitting.
 142          * The FPU maintains a queue of FPops which cause traps.
 143          * When it hits an instruction that requires that the trapped op succeeded
 144          * (usually because it reads a reg. that the trapped op wrote) then it
 145          * causes this exception. We need to emulate all the insns on the queue
 146          * and then allow the op to proceed.
 147          * This code should also handle the case where the trap was precise,
 148          * in which case the queue length is zero and regs->pc points at the
 149          * single FPop to be emulated. (this case is untested, though :->)
 150          * You'll need this case if you want to be able to emulate all FPops
 151          * because the FPU either doesn't exist or has been software-disabled.
 152          * [The UltraSPARC makes FP a precise trap; this isn't as stupid as it
 153          * might sound because the Ultra does funky things with a superscalar
 154          * architecture.]
 155          */
 156
 157         /* You wouldn't believe how often I typed 'ftp' when I meant 'fpt' :-> */
 158
 159         int i;
 160         int retcode = 0;                               /* assume all succeed */
 161         unsigned long insn;
 162
 163 #ifdef DEBUG_MATHEMU
 164         printk("In do_mathemu()... pc is %08lx\n", regs->pc);
 165         printk("fpqdepth is %ld\n", fpt->tss.fpqdepth);
 166         for (i = 0; i < fpt->tss.fpqdepth; i++)
 167                 printk("%d: %08lx at %08lx\n", i, fpt->tss.fpqueue[i].insn,
 168                        (unsigned long)fpt->tss.fpqueue[i].insn_addr);
 169 #endif
 170
 171         if (fpt->tss.fpqdepth == 0) {                   /* no queue, guilty insn is at regs->pc */
 172 #ifdef DEBUG_MATHEMU
 173                 printk("precise trap at %08lx\n", regs->pc);
 174 #endif
 175                 if (!get_user(insn, (u32 *)regs->pc)) {
 176                         retcode = do_one_mathemu(insn, &fpt->tss.fsr, fpt->tss.float_regs);
 177                         if (retcode) {
 178                                 /* in this case we need to fix up PC & nPC */
 179                                 regs->pc = regs->npc;
 180                                 regs->npc += 4;
 181                         }
 182                 }
 183                 return retcode;
 184         }
 185
 186         /* Normal case: need to empty the queue... */
 187         for (i = 0; i < fpt->tss.fpqdepth; i++) {
 188                 retcode = do_one_mathemu(fpt->tss.fpqueue[i].insn, &(fpt->tss.fsr), fpt->tss.float_regs);
 189                 if (!retcode)                               /* insn failed, no point doing any more */
 190                         break;
 191         }
 192         /* Now empty the queue and clear the queue_not_empty flag */
 193         if(retcode)
 194                 fpt->tss.fsr &= ~(0x3000 | FSR_CEXC_MASK);
 195         else
 196                 fpt->tss.fsr &= ~0x3000;
 197         fpt->tss.fpqdepth = 0;
 198
 199         return retcode;
 200 }
 201
 202 /* All routines returning an exception to raise should detect
 203  * such exceptions _before_ rounding to be consistant with
 204  * the behavior of the hardware in the implemented cases
 205  * (and thus with the recommendations in the V9 architecture
 206  * manual).
 207  *
 208  * We return 0 if a SIGFPE should be sent, 1 otherwise.
 209  */
 210 static int record_exception(unsigned long *pfsr, int eflag)
 211 {
 212         unsigned long fsr = *pfsr;
 213         int would_trap;
 214
 215         /* Determine if this exception would have generated a trap. */
 216         would_trap = (fsr & ((long)eflag << FSR_TEM_SHIFT)) != 0UL;
 217
 218         /* If trapping, we only want to signal one bit. */
 219         if(would_trap != 0) {
 220                 eflag &= ((fsr & FSR_TEM_MASK) >> FSR_TEM_SHIFT);
 221                 if((eflag & (eflag - 1)) != 0) {
 222                         if(eflag & FP_EX_INVALID)
 223                                 eflag = FP_EX_INVALID;
 224                         else if(eflag & FP_EX_OVERFLOW)
 225                                 eflag = FP_EX_OVERFLOW;
 226                         else if(eflag & FP_EX_UNDERFLOW)
 227                                 eflag = FP_EX_UNDERFLOW;
 228                         else if(eflag & FP_EX_DIVZERO)
 229                                 eflag = FP_EX_DIVZERO;
 230                         else if(eflag & FP_EX_INEXACT)
 231                                 eflag = FP_EX_INEXACT;
 232                 }
 233         }
 234
 235         /* Set CEXC, here is the rule:
 236          *
 237          *    In general all FPU ops will set one and only one
 238          *    bit in the CEXC field, this is always the case
 239          *    when the IEEE exception trap is enabled in TEM.
 240          */
 241         fsr &= ~(FSR_CEXC_MASK);
 242         fsr |= ((long)eflag << FSR_CEXC_SHIFT);
 243
 244         /* Set the AEXC field, rule is:
 245          *
 246          *    If a trap would not be generated, the
 247          *    CEXC just generated is OR'd into the
 248          *    existing value of AEXC.
 249          */
 250         if(would_trap == 0)
 251                 fsr |= ((long)eflag << FSR_AEXC_SHIFT);
 252
 253         /* If trapping, indicate fault trap type IEEE. */
 254         if(would_trap != 0)
 255                 fsr |= (1UL << 14);
 256
 257         *pfsr = fsr;
 258
 259         return (would_trap ? 0 : 1);
 260 }
 261
 262 static int do_one_mathemu(u32 insn, unsigned long *fsr, unsigned long *fregs)
 263 {
 264         /* Emulate the given insn, updating fsr and fregs appropriately. */
 265         int type = 0;
 266         /* 01 is single, 10 is double, 11 is quad,
 267          * 000011 is rs1, 001100 is rs2, 110000 is rd (00 in rd is fcc)
 268          * 111100000000 tells which ftt that may happen in
 269          * (this field not used on sparc32 code, as we can't
 270          * extract trap type info for ops on the FP queue)
 271          */
 272         int freg, eflag;
 273         int (*func)(void *,void *,void *) = NULL;
 274         void *rs1 = NULL, *rs2 = NULL, *rd = NULL;
 275
 276 #ifdef DEBUG_MATHEMU
 277         printk("In do_mathemu(), emulating %08lx\n", insn);
 278 #endif
 279
 280         if ((insn & 0xc1f80000) == 0x81a00000)  /* FPOP1 */ {
 281                 switch ((insn >> 5) & 0x1ff) {
 282                 /* QUAD - ftt == 3 */
 283                 case 0x001: type = 0x314; func = FMOVS; break;
 284                 case 0x005: type = 0x314; func = FNEGS; break;
 285                 case 0x009: type = 0x314; func = FABSS; break;
 286                 case 0x02b: type = 0x33c; func = FSQRTQ; break;
 287                 case 0x043: type = 0x33f; func = FADDQ; break;
 288                 case 0x047: type = 0x33f; func = FSUBQ; break;
 289                 case 0x04b: type = 0x33f; func = FMULQ; break;
 290                 case 0x04f: type = 0x33f; func = FDIVQ; break;
 291                 case 0x06e: type = 0x33a; func = FDMULQ; break;
 292                 case 0x0c7: type = 0x31c; func = FQTOS; break;
 293                 case 0x0cb: type = 0x32c; func = FQTOD; break;
 294                 case 0x0cc: type = 0x334; func = FITOQ; break;
 295                 case 0x0cd: type = 0x334; func = FSTOQ; break;
 296                 case 0x0ce: type = 0x338; func = FDTOQ; break;
 297                 case 0x0d3: type = 0x31c; func = FQTOI; break;
 298                 /* SUBNORMAL - ftt == 2 */
 299                 case 0x029: type = 0x214; func = FSQRTS; break;
 300                 case 0x02a: type = 0x228; func = FSQRTD; break;
 301                 case 0x041: type = 0x215; func = FADDS; break;
 302                 case 0x042: type = 0x22a; func = FADDD; break;
 303                 case 0x045: type = 0x215; func = FSUBS; break;
 304                 case 0x046: type = 0x22a; func = FSUBD; break;
 305                 case 0x049: type = 0x215; func = FMULS; break;
 306                 case 0x04a: type = 0x22a; func = FMULD; break;
 307                 case 0x04d: type = 0x215; func = FDIVS; break;
 308                 case 0x04e: type = 0x22a; func = FDIVD; break;
 309                 case 0x069: type = 0x225; func = FSMULD; break;
 310                 case 0x0c6: type = 0x218; func = FDTOS; break;
 311                 case 0x0c9: type = 0x224; func = FSTOD; break;
 312                 case 0x0d1: type = 0x214; func = FSTOI; break;
 313                 case 0x0d2: type = 0x218; func = FDTOI; break;
 314                 default:
 315 #ifdef DEBUG_MATHEMU
 316                         printk("unknown FPop1: %03lx\n",(insn>>5)&0x1ff);
 317 #endif
 318                 }
 319         } else if ((insn & 0xc1f80000) == 0x81a80000)   /* FPOP2 */ {
 320                 switch ((insn >> 5) & 0x1ff) {
 321                 case 0x051: type = 0x305; func = FCMPS; break;
 322                 case 0x052: type = 0x30a; func = FCMPD; break;
 323                 case 0x053: type = 0x30f; func = FCMPQ; break;
 324                 case 0x055: type = 0x305; func = FCMPES; break;
 325                 case 0x056: type = 0x30a; func = FCMPED; break;
 326                 case 0x057: type = 0x30f; func = FCMPEQ; break;
 327                 default:
 328 #ifdef DEBUG_MATHEMU
 329                         printk("unknown FPop2: %03lx\n",(insn>>5)&0x1ff);
 330 #endif
 331                 }
 332         }
 333
 334         if (!type) {    /* oops, didn't recognise that FPop */
 335                 printk("attempt to emulate unrecognised FPop!\n");
 336                 return 0;
 337         }
 338
 339         /* Decode the registers to be used */
 340         freg = (*fsr >> 14) & 0xf;
 341
 342         *fsr &= ~0x1c000;                               /* clear the traptype bits */
 343
 344         freg = ((insn >> 14) & 0x1f);
 345         switch (type & 0x3) {                           /* is rs1 single, double or quad? */
 346         case 3:
 347                 if (freg & 3) {                         /* quadwords must have bits 4&5 of the */
 348                                                         /* encoded reg. number set to zero. */
 349                         *fsr |= (6 << 14);
 350                         return 0;                       /* simulate invalid_fp_register exception */
 351                 }
 352         /* fall through */
 353         case 2:
 354                 if (freg & 1) {                         /* doublewords must have bit 5 zeroed */
 355                         *fsr |= (6 << 14);
 356                         return 0;
 357                 }
 358         }
 359         rs1 = (void *)&fregs[freg];
 360         freg = (insn & 0x1f);
 361         switch ((type >> 2) & 0x3) {                    /* same again for rs2 */
 362         case 3:
 363                 if (freg & 3) {                         /* quadwords must have bits 4&5 of the */
 364                                                         /* encoded reg. number set to zero. */
 365                         *fsr |= (6 << 14);
 366                         return 0;                       /* simulate invalid_fp_register exception */
 367                 }
 368         /* fall through */
 369         case 2:
 370                 if (freg & 1) {                         /* doublewords must have bit 5 zeroed */
 371                         *fsr |= (6 << 14);
 372                         return 0;
 373                 }
 374         }
 375         rs2 = (void *)&fregs[freg];
 376         freg = ((insn >> 25) & 0x1f);
 377         switch ((type >> 4) & 0x3) {                    /* and finally rd. This one's a bit different */
 378         case 0:                                         /* dest is fcc. (this must be FCMPQ or FCMPEQ) */
 379                 if (freg) {                             /* V8 has only one set of condition codes, so */
 380                                                         /* anything but 0 in the rd field is an error */
 381                         *fsr |= (6 << 14);              /* (should probably flag as invalid opcode */
 382                         return 0;                       /* but SIGFPE will do :-> ) */
 383                 }
 384                 rd = (void *)(fsr);                     /* FCMPQ and FCMPEQ are special and only  */
 385                 break;                                  /* set bits they're supposed to :-> */
 386         case 3:
 387                 if (freg & 3) {                         /* quadwords must have bits 4&5 of the */
 388                                                         /* encoded reg. number set to zero. */
 389                         *fsr |= (6 << 14);
 390                         return 0;                       /* simulate invalid_fp_register exception */
 391                 }
 392         /* fall through */
 393         case 2:
 394                 if (freg & 1) {                         /* doublewords must have bit 5 zeroed */
 395                         *fsr |= (6 << 14);
 396                         return 0;
 397                 }
 398         /* fall through */
 399         case 1:
 400                 rd = (void *)&fregs[freg];
 401                 break;
 402         }
 403 #ifdef DEBUG_MATHEMU
 404         printk("executing insn...\n");
 405 #endif
 406         eflag = func(rd, rs2, rs1);                     /* do the Right Thing */
 407         if(eflag == 0)
 408                 return 1;                               /* success! */
 409         return record_exception(fsr, eflag);
 410 }