arch/sh/kernel/time.c

   1 /* $Id: time.c,v 1.20 2000/02/28 12:42:51 gniibe Exp $
   2  *
   3  *  linux/arch/sh/kernel/time.c
   4  *
   5  *  Copyright (C) 1999  Tetsuya Okada & Niibe Yutaka
   6  *
   7  *  Some code taken from i386 version.
   8  *    Copyright (C) 1991, 1992, 1995  Linus Torvalds
   9  */
  10
  11 #include <linux/config.h>
  12 #include <linux/errno.h>
  13 #include <linux/sched.h>
  14 #include <linux/kernel.h>
  15 #include <linux/param.h>
  16 #include <linux/string.h>
  17 #include <linux/mm.h>
  18 #include <linux/interrupt.h>
  19 #include <linux/time.h>
  20 #include <linux/delay.h>
  21 #include <linux/init.h>
  22 #include <linux/smp.h>
  23
  24 #include <asm/processor.h>
  25 #include <asm/uaccess.h>
  26 #include <asm/io.h>
  27 #include <asm/irq.h>
  28 #include <asm/delay.h>
  29 #include <asm/machvec.h>
  30
  31 #include <linux/timex.h>
  32 #include <linux/irq.h>
  33
  34 #define TMU_TOCR_INIT   0x00
  35 #define TMU0_TCR_INIT   0x0020
  36 #define TMU_TSTR_INIT   1
  37
  38 /* RCR1 Bits */
  39 #define RCR1_CF         0x80    /* Carry Flag             */
  40 #define RCR1_CIE        0x10    /* Carry Interrupt Enable */
  41 #define RCR1_AIE        0x08    /* Alarm Interrupt Enable */
  42 #define RCR1_AF         0x01    /* Alarm Flag             */
  43
  44 /* RCR2 Bits */
  45 #define RCR2_PEF        0x80    /* PEriodic interrupt Flag */
  46 #define RCR2_PESMASK    0x70    /* Periodic interrupt Set  */
  47 #define RCR2_RTCEN      0x08    /* ENable RTC              */
  48 #define RCR2_ADJ        0x04    /* ADJustment (30-second)  */
  49 #define RCR2_RESET      0x02    /* Reset bit               */
  50 #define RCR2_START      0x01    /* Start bit               */
  51
  52 #if defined(__sh3__)
  53 #define TMU_TOCR        0xfffffe90      /* Byte access */
  54 #define TMU_TSTR        0xfffffe92      /* Byte access */
  55
  56 #define TMU0_TCOR       0xfffffe94      /* Long access */
  57 #define TMU0_TCNT       0xfffffe98      /* Long access */
  58 #define TMU0_TCR        0xfffffe9c      /* Word access */
  59
  60 #define FRQCR           0xffffff80
  61
  62 /* SH-3 RTC */
  63 #define R64CNT          0xfffffec0
  64 #define RSECCNT         0xfffffec2
  65 #define RMINCNT         0xfffffec4
  66 #define RHRCNT          0xfffffec6
  67 #define RWKCNT          0xfffffec8
  68 #define RDAYCNT         0xfffffeca
  69 #define RMONCNT         0xfffffecc
  70 #define RYRCNT          0xfffffece
  71 #define RSECAR          0xfffffed0
  72 #define RMINAR          0xfffffed2
  73 #define RHRAR           0xfffffed4
  74 #define RWKAR           0xfffffed6
  75 #define RDAYAR          0xfffffed8
  76 #define RMONAR          0xfffffeda
  77 #define RCR1            0xfffffedc
  78 #define RCR2            0xfffffede
  79
  80 #elif defined(__SH4__)
  81 #define TMU_TOCR        0xffd80000      /* Byte access */
  82 #define TMU_TSTR        0xffd80004      /* Byte access */
  83
  84 #define TMU0_TCOR       0xffd80008      /* Long access */
  85 #define TMU0_TCNT       0xffd8000c      /* Long access */
  86 #define TMU0_TCR        0xffd80010      /* Word access */
  87
  88 #define FRQCR           0xffc00000
  89
  90 /* SH-4 RTC */
  91 #define R64CNT          0xffc80000
  92 #define RSECCNT         0xffc80004
  93 #define RMINCNT         0xffc80008
  94 #define RHRCNT          0xffc8000c
  95 #define RWKCNT          0xffc80010
  96 #define RDAYCNT         0xffc80014
  97 #define RMONCNT         0xffc80018
  98 #define RYRCNT          0xffc8001c  /* 16bit */
  99 #define RSECAR          0xffc80020
 100 #define RMINAR          0xffc80024
 101 #define RHRAR           0xffc80028
 102 #define RWKAR           0xffc8002c
 103 #define RDAYAR          0xffc80030
 104 #define RMONAR          0xffc80034
 105 #define RCR1            0xffc80038
 106 #define RCR2            0xffc8003c
 107 #endif
 108
 109 #ifndef BCD_TO_BIN
 110 #define BCD_TO_BIN(val) ((val)=((val)&15) + ((val)>>4)*10)
 111 #endif
 112
 113 #ifndef BIN_TO_BCD
 114 #define BIN_TO_BCD(val) ((val)=(((val)/10)<<4) + (val)%10)
 115 #endif
 116
 117 extern rwlock_t xtime_lock;
 118 extern unsigned long wall_jiffies;
 119 #define TICK_SIZE tick
 120
 121 void do_gettimeofday(struct timeval *tv)
 122 {
 123         unsigned long flags;
 124         unsigned long usec, sec;
 125
 126         read_lock_irqsave(&xtime_lock, flags);
 127         usec = 0;
 128         {
 129                 unsigned long lost = jiffies - wall_jiffies;
 130                 if (lost)
 131                         usec += lost * (1000000 / HZ);
 132         }
 133         sec = xtime.tv_sec;
 134         usec += xtime.tv_usec;
 135         read_unlock_irqrestore(&xtime_lock, flags);
 136
 137         while (usec >= 1000000) {
 138                 usec -= 1000000;
 139                 sec++;
 140         }
 141
 142         tv->tv_sec = sec;
 143         tv->tv_usec = usec;
 144 }
 145
 146 /*
 147  * Could someone please implement this...
 148  */
 149 #define do_gettimeoffset() 0
 150
 151 void do_settimeofday(struct timeval *tv)
 152 {
 153         write_lock_irq(&xtime_lock);
 154         /*
 155          * This is revolting. We need to set "xtime" correctly. However, the
 156          * value in this location is the value at the most recent update of
 157          * wall time.  Discover what correction gettimeofday() would have
 158          * made, and then undo it!
 159          */
 160         tv->tv_usec -= do_gettimeoffset();
 161         tv->tv_usec -= (jiffies - wall_jiffies) * (1000000 / HZ);
 162
 163         while (tv->tv_usec < 0) {
 164                 tv->tv_usec += 1000000;
 165                 tv->tv_sec--;
 166         }
 167
 168         xtime = *tv;
 169         time_adjust = 0;                /* stop active adjtime() */
 170         time_status |= STA_UNSYNC;
 171         time_maxerror = NTP_PHASE_LIMIT;
 172         time_esterror = NTP_PHASE_LIMIT;
 173         write_unlock_irq(&xtime_lock);
 174 }
 175
 176 static int set_rtc_time(unsigned long nowtime)
 177 {
 178         int retval = 0;
 179         int real_seconds, real_minutes, cmos_minutes;
 180
 181         ctrl_outb(RCR2_RESET, RCR2);  /* Reset pre-scaler & stop RTC */
 182
 183         cmos_minutes = ctrl_inb(RMINCNT);
 184         BCD_TO_BIN(cmos_minutes);
 185
 186         /*
 187          * since we're only adjusting minutes and seconds,
 188          * don't interfere with hour overflow. This avoids
 189          * messing with unknown time zones but requires your
 190          * RTC not to be off by more than 15 minutes
 191          */
 192         real_seconds = nowtime % 60;
 193         real_minutes = nowtime / 60;
 194         if (((abs(real_minutes - cmos_minutes) + 15)/30) & 1)
 195                 real_minutes += 30;     /* correct for half hour time zone */
 196         real_minutes %= 60;
 197
 198         if (abs(real_minutes - cmos_minutes) < 30) {
 199                 BIN_TO_BCD(real_seconds);
 200                 BIN_TO_BCD(real_minutes);
 201                 ctrl_outb(real_seconds, RSECCNT);
 202                 ctrl_outb(real_minutes, RMINCNT);
 203         } else {
 204                 printk(KERN_WARNING
 205                        "set_rtc_time: can't update from %d to %d\n",
 206                        cmos_minutes, real_minutes);
 207                 retval = -1;
 208         }
 209
 210         ctrl_outb(RCR2_RTCEN|RCR2_START, RCR2);  /* Start RTC */
 211
 212         return retval;
 213 }
 214
 215 /* last time the RTC clock got updated */
 216 static long last_rtc_update;
 217
 218 /*
 219  * timer_interrupt() needs to keep up the real-time clock,
 220  * as well as call the "do_timer()" routine every clocktick
 221  */
 222 static inline void do_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
 223 {
 224         do_timer(regs);
 225 #if 0
 226         if (!user_mode(regs))
 227                 sh_do_profile(regs->pc);
 228 #endif
 229
 230 #ifdef CONFIG_HEARTBEAT
 231         if (sh_mv.mv_heartbeat != NULL)
 232                 sh_mv.mv_heartbeat();
 233 #endif
 234
 235         /*
 236          * If we have an externally synchronized Linux clock, then update
 237          * RTC clock accordingly every ~11 minutes. Set_rtc_mmss() has to be
 238          * called as close as possible to 500 ms before the new second starts.
 239          */
 240         if ((time_status & STA_UNSYNC) == 0 &&
 241             xtime.tv_sec > last_rtc_update + 660 &&
 242             xtime.tv_usec >= 500000 - ((unsigned) tick) / 2 &&
 243             xtime.tv_usec <= 500000 + ((unsigned) tick) / 2) {
 244                 if (set_rtc_time(xtime.tv_sec) == 0)
 245                         last_rtc_update = xtime.tv_sec;
 246                 else
 247                         last_rtc_update = xtime.tv_sec - 600; /* do it again in 60 s */
 248         }
 249 }
 250
 251 /*
 252  * This is the same as the above, except we _also_ save the current
 253  * Time Stamp Counter value at the time of the timer interrupt, so that
 254  * we later on can estimate the time of day more exactly.
 255  */
 256 static void timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
 257 {
 258         unsigned long timer_status;
 259
 260         /* Clear UNF bit */
 261         timer_status = ctrl_inw(TMU0_TCR);
 262         timer_status &= ~0x100;
 263         ctrl_outw(timer_status, TMU0_TCR);
 264
 265         /*
 266          * Here we are in the timer irq handler. We just have irqs locally
 267          * disabled but we don't know if the timer_bh is running on the other
 268          * CPU. We need to avoid to SMP race with it. NOTE: we don' t need
 269          * the irq version of write_lock because as just said we have irq
 270          * locally disabled. -arca
 271          */
 272         write_lock(&xtime_lock);
 273         do_timer_interrupt(irq, NULL, regs);
 274         write_unlock(&xtime_lock);
 275 }
 276
 277 static unsigned long get_rtc_time(void)
 278 {
 279         unsigned int sec, min, hr, wk, day, mon, yr, yr100;
 280
 281  again:
 282         do {
 283                 ctrl_outb(0, RCR1);  /* Clear CF-bit */
 284                 sec = ctrl_inb(RSECCNT);
 285                 min = ctrl_inb(RMINCNT);
 286                 hr  = ctrl_inb(RHRCNT);
 287                 wk  = ctrl_inb(RWKCNT);
 288                 day = ctrl_inb(RDAYCNT);
 289                 mon = ctrl_inb(RMONCNT);
 290 #if defined(__SH4__)
 291                 yr  = ctrl_inw(RYRCNT);
 292                 yr100 = (yr >> 8);
 293                 yr &= 0xff;
 294 #else
 295                 yr  = ctrl_inb(RYRCNT);
 296                 yr100 = (yr == 0x99) ? 0x19 : 0x20;
 297 #endif
 298         } while ((ctrl_inb(RCR1) & RCR1_CF) != 0);
 299
 300         BCD_TO_BIN(yr100);
 301         BCD_TO_BIN(yr);
 302         BCD_TO_BIN(mon);
 303         BCD_TO_BIN(day);
 304         BCD_TO_BIN(hr);
 305         BCD_TO_BIN(min);
 306         BCD_TO_BIN(sec);
 307
 308         if (yr > 99 || mon < 1 || mon > 12 || day > 31 || day < 1 ||
 309             hr > 23 || min > 59 || sec > 59) {
 310                 printk(KERN_ERR
 311                        "SH RTC: invalid value, resetting to 1 Jan 2000\n");
 312                 ctrl_outb(RCR2_RESET, RCR2);  /* Reset & Stop */
 313                 ctrl_outb(0, RSECCNT);
 314                 ctrl_outb(0, RMINCNT);
 315                 ctrl_outb(0, RHRCNT);
 316                 ctrl_outb(6, RWKCNT);
 317                 ctrl_outb(1, RDAYCNT);
 318                 ctrl_outb(1, RMONCNT);
 319 #if defined(__SH4__)
 320                 ctrl_outw(0x2000, RYRCNT);
 321 #else
 322                 ctrl_outb(0, RYRCNT);
 323 #endif
 324                 ctrl_outb(RCR2_RTCEN|RCR2_START, RCR2);  /* Start */
 325                 goto again;
 326         }
 327
 328         return mktime(yr100 * 100 + yr, mon, day, hr, min, sec);
 329 }
 330
 331 static __init unsigned int get_cpu_mhz(void)
 332 {
 333         unsigned int count;
 334         unsigned long __dummy;
 335
 336         sti();
 337         do {} while (ctrl_inb(R64CNT) != 0);
 338         ctrl_outb(RCR1_CIE, RCR1); /* Enable carry interrupt */
 339         asm volatile(
 340                 "1:\t"
 341                 "tst    %1,%1\n\t"
 342                 "bt/s   1b\n\t"
 343                 " add   #1,%0"
 344                 : "=r"(count), "=z" (__dummy)
 345                 : "0" (0), "1" (0)
 346                 : "t");
 347         cli();
 348         /*
 349          * SH-3:
 350          * CPU clock = 4 stages * loop
 351          * tst    rm,rm      if id ex
 352          * bt/s   1b            if id ex
 353          * add    #1,rd            if id ex
 354          *                            (if) pipe line stole
 355          * tst    rm,rm                  if id ex
 356          * ....
 357          *
 358          *
 359          * SH-4:
 360          * CPU clock = 6 stages * loop
 361          * I don't know why.
 362          * ....
 363          */
 364 #if defined(__SH4__)
 365         return count*6;
 366 #else
 367         return count*4;
 368 #endif
 369 }
 370
 371 static void rtc_interrupt(int irq, void *dev_id, struct pt_regs *regs)
 372 {
 373         ctrl_outb(0, RCR1);     /* Disable Carry Interrupts */
 374         regs->regs[0] = 1;
 375 }
 376
 377 static struct irqaction irq0  = { timer_interrupt, SA_INTERRUPT, 0, "timer", NULL, NULL};
 378 static struct irqaction irq1  = { rtc_interrupt, SA_INTERRUPT, 0, "rtc", NULL, NULL};
 379
 380 void __init time_init(void)
 381 {
 382         unsigned int cpu_clock, master_clock, bus_clock, module_clock;
 383         unsigned short frqcr, ifc, pfc;
 384         unsigned long interval;
 385 #if defined(__sh3__)
 386         static int ifc_table[] = { 1, 2, 4, 1, 3, 1, 1, 1 };
 387         static int pfc_table[] = { 1, 2, 4, 1, 3, 6, 1, 1 };
 388         static int stc_table[] = { 1, 2, 3, 4, 6, 8, 1, 1 };
 389 #elif defined(__SH4__)
 390         static int ifc_table[] = { 1, 2, 3, 4, 6, 8, 1, 1 };
 391 #define bfc_table ifc_table     /* Same */
 392         static int pfc_table[] = { 2, 3, 4, 6, 8, 2, 2, 2 };
 393 #endif
 394
 395         xtime.tv_sec = get_rtc_time();
 396         xtime.tv_usec = 0;
 397
 398         setup_irq(TIMER_IRQ, &irq0);
 399         setup_irq(RTC_IRQ, &irq1);
 400
 401         /* Check how fast it is.. */
 402         cpu_clock = get_cpu_mhz();
 403         disable_irq(RTC_IRQ);
 404
 405         printk("CPU clock: %d.%02dMHz\n",
 406                (cpu_clock / 1000000), (cpu_clock % 1000000)/10000);
 407 #if defined(__sh3__)
 408         {
 409                 unsigned short tmp, stc;
 410                 frqcr = ctrl_inw(FRQCR);
 411                 tmp  = (frqcr & 0x8000) >> 13;
 412                 tmp |= (frqcr & 0x0030) >>  4;
 413                 stc = stc_table[tmp];
 414                 tmp  = (frqcr & 0x4000) >> 12;
 415                 tmp |= (frqcr & 0x000c) >> 2;
 416                 ifc  = ifc_table[tmp];
 417                 tmp  = (frqcr & 0x2000) >> 11;
 418                 tmp |= frqcr & 0x0003;
 419                 pfc = pfc_table[tmp];
 420                 if (MACH_HP600) {
 421                         master_clock = cpu_clock/6;
 422                 } else {
 423                         master_clock = cpu_clock;
 424                 }
 425                 bus_clock = master_clock/pfc;
 426         }
 427 #elif defined(__SH4__)
 428         {
 429                 unsigned short bfc;
 430                 frqcr = ctrl_inw(FRQCR);
 431                 ifc  = ifc_table[(frqcr>> 6) & 0x0007];
 432                 bfc  = bfc_table[(frqcr>> 3) & 0x0007];
 433                 pfc = pfc_table[frqcr & 0x0007];
 434                 master_clock = cpu_clock * ifc;
 435                 bus_clock = master_clock/bfc;
 436         }
 437 #endif
 438         printk("Bus clock: %d.%02dMHz\n",
 439                (bus_clock/1000000), (bus_clock % 1000000)/10000);
 440         module_clock = master_clock/pfc;
 441         printk("Module clock: %d.%02dMHz\n",
 442                (module_clock/1000000), (module_clock % 1000000)/10000);
 443         interval = (module_clock/(HZ*4));
 444
 445         printk("Interval = %ld\n", interval);
 446
 447         current_cpu_data.cpu_clock    = cpu_clock;
 448         current_cpu_data.master_clock = master_clock;
 449         current_cpu_data.bus_clock    = bus_clock;
 450         current_cpu_data.module_clock = module_clock;
 451
 452         /* Start TMU0 */
 453         ctrl_outb(TMU_TOCR_INIT, TMU_TOCR);
 454         ctrl_outw(TMU0_TCR_INIT, TMU0_TCR);
 455         ctrl_outl(interval, TMU0_TCOR);
 456         ctrl_outl(interval, TMU0_TCNT);
 457         ctrl_outb(TMU_TSTR_INIT, TMU_TSTR);
 458 }