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The LDT fixes in particular fix some potentially random strange behaviour.
[davej-history.git] / drivers / ide / sis5513.c
blob571cae56377a9ba00981942216e8621ce9121341
1 /*
2 * linux/drivers/ide/sis5513.c Version 0.11 June 9, 2000
3 *
4 * Copyright (C) 1999-2000 Andre Hedrick <andre@linux-ide.org>
5 * May be copied or modified under the terms of the GNU General Public License
6 *
7 * Thanks to SIS Taiwan for direct support and hardware.
8 * Tested and designed on the SiS620/5513 chipset.
9 */
10
11 #include <linux/config.h>
12 #include <linux/types.h>
13 #include <linux/kernel.h>
14 #include <linux/delay.h>
15 #include <linux/timer.h>
16 #include <linux/mm.h>
17 #include <linux/ioport.h>
18 #include <linux/blkdev.h>
19 #include <linux/hdreg.h>
20
21 #include <linux/interrupt.h>
22 #include <linux/pci.h>
23 #include <linux/init.h>
24 #include <linux/ide.h>
25
26 #include <asm/io.h>
27 #include <asm/irq.h>
28
29 #include "ide_modes.h"
30
31 #define DISPLAY_SIS_TIMINGS
32 #define SIS5513_DEBUG_DRIVE_INFO 0
33
34 static struct pci_dev *host_dev = NULL;
35
36 #define SIS5513_FLAG_ATA_00 0x00000000
37 #define SIS5513_FLAG_ATA_16 0x00000001
38 #define SIS5513_FLAG_ATA_33 0x00000002
39 #define SIS5513_FLAG_ATA_66 0x00000004
40 #define SIS5513_FLAG_LATENCY 0x00000010
41
42 static const struct {
43 const char *name;
44 unsigned short host_id;
45 unsigned int flags;
46 } SiSHostChipInfo[] = {
47 { "SiS530", PCI_DEVICE_ID_SI_530, SIS5513_FLAG_ATA_66, },
48 { "SiS540", PCI_DEVICE_ID_SI_540, SIS5513_FLAG_ATA_66, },
49 { "SiS620", PCI_DEVICE_ID_SI_620, SIS5513_FLAG_ATA_66|SIS5513_FLAG_LATENCY, },
50 { "SiS630", PCI_DEVICE_ID_SI_630, SIS5513_FLAG_ATA_66|SIS5513_FLAG_LATENCY, },
51 { "SiS5591", PCI_DEVICE_ID_SI_5591, SIS5513_FLAG_ATA_33, },
52 { "SiS5597", PCI_DEVICE_ID_SI_5597, SIS5513_FLAG_ATA_33, },
53 { "SiS5600", PCI_DEVICE_ID_SI_5600, SIS5513_FLAG_ATA_33, },
54 { "SiS5511", PCI_DEVICE_ID_SI_5511, SIS5513_FLAG_ATA_16, },
55 };
56
57 #if 0
58
59 static struct _pio_mode_mapping {
60 byte data_active;
61 byte recovery;
62 byte pio_mode;
63 } pio_mode_mapping[] = {
64 { 8, 12, 0 },
65 { 6, 7, 1 },
66 { 4, 4, 2 },
67 { 3, 3, 3 },
68 { 3, 1, 4 }
69 };
70
71 static struct _dma_mode_mapping {
72 byte data_active;
73 byte recovery;
74 byte dma_mode;
75 } dma_mode_mapping[] = {
76 { 8, 8, 0 },
77 { 3, 2, 1 },
78 { 3, 1, 2 }
79 };
80
81 static struct _udma_mode_mapping {
82 byte cycle_time;
83 char * udma_mode;
84 } udma_mode_mapping[] = {
85 { 8, "Mode 0" },
86 { 6, "Mode 1" },
87 { 4, "Mode 2" },
88 { 3, "Mode 3" },
89 { 2, "Mode 4" },
90 { 0, "Undefined" }
91 };
92
93 static __inline__ char * find_udma_mode (byte cycle_time)
94 {
95 int n;
96
97 for (n = 0; n <= 4; n++)
98 if (udma_mode_mapping[n].cycle_time <= cycle_time)
99 return udma_mode_mapping[n].udma_mode;
100 return udma_mode_mapping[4].udma_mode;
101 }
102 #endif
103
104 #if defined(DISPLAY_SIS_TIMINGS) && defined(CONFIG_PROC_FS)
105 #include <linux/stat.h>
106 #include <linux/proc_fs.h>
107
108 static int sis_get_info(char *, char **, off_t, int);
109 extern int (*sis_display_info)(char *, char **, off_t, int); /* ide-proc.c */
110 static struct pci_dev *bmide_dev;
111
112 static char *cable_type[] = {
113 "80 pins",
114 "40 pins"
115 };
116
117 static char *recovery_time [] ={
118 "12 PCICLK", "1 PCICLK",
119 "2 PCICLK", "3 PCICLK",
120 "4 PCICLK", "5 PCICLCK",
121 "6 PCICLK", "7 PCICLCK",
122 "8 PCICLK", "9 PCICLCK",
123 "10 PCICLK", "11 PCICLK",
124 "13 PCICLK", "14 PCICLK",
125 "15 PCICLK", "15 PCICLK"
126 };
127
128 static char * cycle_time [] = {
129 "Undefined", "2 CLCK",
130 "3 CLK", "4 CLK",
131 "5 CLK", "6 CLK",
132 "7 CLK", "8 CLK"
133 };
134
135 static char * active_time [] = {
136 "8 PCICLK", "1 PCICLCK",
137 "2 PCICLK", "2 PCICLK",
138 "4 PCICLK", "5 PCICLK",
139 "6 PCICLK", "12 PCICLK"
140 };
141
142 static int sis_get_info (char *buffer, char **addr, off_t offset, int count)
143 {
144 int rc;
145 char *p = buffer;
146 byte reg,reg1;
147 u16 reg2, reg3;
148
149 p += sprintf(p, "--------------- Primary Channel ---------------- Secondary Channel -------------\n");
150 rc = pci_read_config_byte(bmide_dev, 0x4a, &reg);
151 p += sprintf(p, "Channel Status: %s \t \t \t \t %s \n",
152 (reg & 0x02) ? "On" : "Off",
153 (reg & 0x04) ? "On" : "Off");
154
155 rc = pci_read_config_byte(bmide_dev, 0x09, &reg);
156 p += sprintf(p, "Operation Mode: %s \t \t \t %s \n",
157 (reg & 0x01) ? "Native" : "Compatible",
158 (reg & 0x04) ? "Native" : "Compatible");
159
160 rc = pci_read_config_byte(bmide_dev, 0x48, &reg);
161 p += sprintf(p, "Cable Type: %s \t \t \t %s\n",
162 (reg & 0x10) ? cable_type[1] : cable_type[0],
163 (reg & 0x20) ? cable_type[1] : cable_type[0]);
164
165 rc = pci_read_config_word(bmide_dev, 0x4c, &reg2);
166 rc = pci_read_config_word(bmide_dev, 0x4e, &reg3);
167 p += sprintf(p, "Prefetch Count: %d \t \t \t \t %d\n",
168 reg2, reg3);
169
170 rc = pci_read_config_byte(bmide_dev, 0x4b, &reg);
171 p += sprintf(p, "Drive 0: Postwrite %s \t \t Postwrite %s\n",
172 (reg & 0x10) ? "Enabled" : "Disabled",
173 (reg & 0x40) ? "Enabled" : "Disabled");
174 p += sprintf(p, " Prefetch %s \t \t Prefetch %s\n",
175 (reg & 0x01) ? "Enabled" : "Disabled",
176 (reg & 0x04) ? "Enabled" : "Disabled");
177
178 rc = pci_read_config_byte(bmide_dev, 0x41, &reg);
179 rc = pci_read_config_byte(bmide_dev, 0x45, &reg1);
180 p += sprintf(p, " UDMA %s \t \t \t UDMA %s\n",
181 (reg & 0x80) ? "Enabled" : "Disabled",
182 (reg1 & 0x80) ? "Enabled" : "Disabled");
183 p += sprintf(p, " UDMA Cycle Time %s \t UDMA Cycle Time %s\n",
184 cycle_time[(reg & 0x70) >> 4], cycle_time[(reg1 & 0x70) >> 4]);
185 p += sprintf(p, " Data Active Time %s \t Data Active Time %s\n",
186 active_time[(reg & 0x07)], active_time[(reg1 &0x07)] );
187
188 rc = pci_read_config_byte(bmide_dev, 0x40, &reg);
189 rc = pci_read_config_byte(bmide_dev, 0x44, &reg1);
190 p += sprintf(p, " Data Recovery Time %s \t Data Recovery Time %s\n",
191 recovery_time[(reg & 0x0f)], recovery_time[(reg1 & 0x0f)]);
192
193
194 rc = pci_read_config_byte(bmide_dev, 0x4b, &reg);
195 p += sprintf(p, "Drive 1: Postwrite %s \t \t Postwrite %s\n",
196 (reg & 0x20) ? "Enabled" : "Disabled",
197 (reg & 0x80) ? "Enabled" : "Disabled");
198 p += sprintf(p, " Prefetch %s \t \t Prefetch %s\n",
199 (reg & 0x02) ? "Enabled" : "Disabled",
200 (reg & 0x08) ? "Enabled" : "Disabled");
201
202 rc = pci_read_config_byte(bmide_dev, 0x43, &reg);
203 rc = pci_read_config_byte(bmide_dev, 0x47, &reg1);
204 p += sprintf(p, " UDMA %s \t \t \t UDMA %s\n",
205 (reg & 0x80) ? "Enabled" : "Disabled",
206 (reg1 & 0x80) ? "Enabled" : "Disabled");
207 p += sprintf(p, " UDMA Cycle Time %s \t UDMA Cycle Time %s\n",
208 cycle_time[(reg & 0x70) >> 4], cycle_time[(reg1 & 0x70) >> 4]);
209 p += sprintf(p, " Data Active Time %s \t Data Active Time %s\n",
210 active_time[(reg & 0x07)], active_time[(reg1 &0x07)] );
211
212 rc = pci_read_config_byte(bmide_dev, 0x42, &reg);
213 rc = pci_read_config_byte(bmide_dev, 0x46, &reg1);
214 p += sprintf(p, " Data Recovery Time %s \t Data Recovery Time %s\n",
215 recovery_time[(reg & 0x0f)], recovery_time[(reg1 & 0x0f)]);
216 return p-buffer;
217 }
218 #endif /* defined(DISPLAY_SIS_TIMINGS) && defined(CONFIG_PROC_FS) */
219
220 byte sis_proc = 0;
221 extern char *ide_xfer_verbose (byte xfer_rate);
222
223 static void config_drive_art_rwp (ide_drive_t *drive)
224 {
225 ide_hwif_t *hwif = HWIF(drive);
226 struct pci_dev *dev = hwif->pci_dev;
227
228 byte reg4bh = 0;
229 byte rw_prefetch = (0x11 << drive->dn);
230
231 pci_read_config_byte(dev, 0x4b, &reg4bh);
232 if (drive->media != ide_disk)
233 return;
234
235 if ((reg4bh & rw_prefetch) != rw_prefetch)
236 pci_write_config_byte(dev, 0x4b, reg4bh|rw_prefetch);
237 }
238
239 static void config_art_rwp_pio (ide_drive_t *drive, byte pio)
240 {
241 ide_hwif_t *hwif = HWIF(drive);
242 struct pci_dev *dev = hwif->pci_dev;
243
244 byte timing, drive_pci, test1, test2;
245
246 unsigned short eide_pio_timing[6] = {600, 390, 240, 180, 120, 90};
247 unsigned short xfer_pio = drive->id->eide_pio_modes;
248
249 config_drive_art_rwp(drive);
250 pio = ide_get_best_pio_mode(drive, 255, pio, NULL);
251
252 if (xfer_pio> 4)
253 xfer_pio = 0;
254
255 if (drive->id->eide_pio_iordy > 0) {
256 for (xfer_pio = 5;
257 xfer_pio>0 &&
258 drive->id->eide_pio_iordy>eide_pio_timing[xfer_pio];
259 xfer_pio--);
260 } else {
261 xfer_pio = (drive->id->eide_pio_modes & 4) ? 0x05 :
262 (drive->id->eide_pio_modes & 2) ? 0x04 :
263 (drive->id->eide_pio_modes & 1) ? 0x03 : xfer_pio;
264 }
265
266 timing = (xfer_pio >= pio) ? xfer_pio : pio;
267
268 /*
269 * Mode 0 Mode 1 Mode 2 Mode 3 Mode 4
270 * Active time 8T (240ns) 6T (180ns) 4T (120ns) 3T (90ns) 3T (90ns)
271 * 0x41 2:0 bits 000 110 100 011 011
272 * Recovery time 12T (360ns) 7T (210ns) 4T (120ns) 3T (90ns) 1T (30ns)
273 * 0x40 3:0 bits 0000 0111 0100 0011 0001
274 * Cycle time 20T (600ns) 13T (390ns) 8T (240ns) 6T (180ns) 4T (120ns)
275 */
276
277 switch(drive->dn) {
278 case 0: drive_pci = 0x40; break;
279 case 1: drive_pci = 0x42; break;
280 case 2: drive_pci = 0x44; break;
281 case 3: drive_pci = 0x46; break;
282 default: return;
283 }
284
285 pci_read_config_byte(dev, drive_pci, &test1);
286 pci_read_config_byte(dev, drive_pci|0x01, &test2);
287
288 /*
289 * Do a blanket clear of active and recovery timings.
290 */
291
292 test1 &= ~0x07;
293 test2 &= ~0x0F;
294
295 switch(timing) {
296 case 4: test1 |= 0x01; test2 |= 0x03; break;
297 case 3: test1 |= 0x03; test2 |= 0x03; break;
298 case 2: test1 |= 0x04; test2 |= 0x04; break;
299 case 1: test1 |= 0x07; test2 |= 0x06; break;
300 default: break;
301 }
302
303 pci_write_config_byte(dev, drive_pci, test1);
304 pci_write_config_byte(dev, drive_pci|0x01, test2);
305 }
306
307 static int config_chipset_for_pio (ide_drive_t *drive, byte pio)
308 {
309 int err;
310 byte speed;
311
312 switch(pio) {
313 case 4: speed = XFER_PIO_4; break;
314 case 3: speed = XFER_PIO_3; break;
315 case 2: speed = XFER_PIO_2; break;
316 case 1: speed = XFER_PIO_1; break;
317 default: speed = XFER_PIO_0; break;
318 }
319
320 config_art_rwp_pio(drive, pio);
321 drive->current_speed = speed;
322 err = ide_config_drive_speed(drive, speed);
323 return err;
324 }
325
326 static int sis5513_tune_chipset (ide_drive_t *drive, byte speed)
327 {
328 ide_hwif_t *hwif = HWIF(drive);
329 struct pci_dev *dev = hwif->pci_dev;
330
331 byte drive_pci, test1, test2;
332 byte unmask, four_two, mask = 0;
333
334 if (host_dev) {
335 switch(host_dev->device) {
336 case PCI_DEVICE_ID_SI_530:
337 case PCI_DEVICE_ID_SI_540:
338 case PCI_DEVICE_ID_SI_620:
339 case PCI_DEVICE_ID_SI_630:
340 unmask = 0xF0;
341 four_two = 0x01;
342 break;
343 default:
344 unmask = 0xE0;
345 four_two = 0x00;
346 break;
347 }
348 } else {
349 unmask = 0xE0;
350 four_two = 0x00;
351 }
352
353 switch(drive->dn) {
354 case 0: drive_pci = 0x40;break;
355 case 1: drive_pci = 0x42;break;
356 case 2: drive_pci = 0x44;break;
357 case 3: drive_pci = 0x46;break;
358 default: return ide_dma_off;
359 }
360
361 pci_read_config_byte(dev, drive_pci, &test1);
362 pci_read_config_byte(dev, drive_pci|0x01, &test2);
363
364 if ((speed <= XFER_MW_DMA_2) && (test2 & 0x80)) {
365 pci_write_config_byte(dev, drive_pci|0x01, test2 & ~0x80);
366 pci_read_config_byte(dev, drive_pci|0x01, &test2);
367 } else {
368 pci_write_config_byte(dev, drive_pci|0x01, test2 & ~unmask);
369 }
370
371 switch(speed) {
372 #ifdef CONFIG_BLK_DEV_IDEDMA
373 case XFER_UDMA_5: /* can not do ultra mode 5 yet */
374 case XFER_UDMA_4: mask = 0x90; break;
375 case XFER_UDMA_3: mask = 0xA0; break;
376 case XFER_UDMA_2: mask = (four_two) ? 0xB0 : 0xA0; break;
377 case XFER_UDMA_1: mask = (four_two) ? 0xD0 : 0xC0; break;
378 case XFER_UDMA_0: mask = unmask; break;
379 case XFER_MW_DMA_2:
380 case XFER_MW_DMA_1:
381 case XFER_MW_DMA_0:
382 case XFER_SW_DMA_2:
383 case XFER_SW_DMA_1:
384 case XFER_SW_DMA_0: break;
385 #endif /* CONFIG_BLK_DEV_IDEDMA */
386 case XFER_PIO_4: return((int) config_chipset_for_pio(drive, 4));
387 case XFER_PIO_3: return((int) config_chipset_for_pio(drive, 3));
388 case XFER_PIO_2: return((int) config_chipset_for_pio(drive, 2));
389 case XFER_PIO_1: return((int) config_chipset_for_pio(drive, 1));
390 case XFER_PIO_0:
391 default: return((int) config_chipset_for_pio(drive, 0));
392 }
393
394 if (speed > XFER_MW_DMA_2)
395 pci_write_config_byte(dev, drive_pci|0x01, test2|mask);
396
397 drive->current_speed = speed;
398 return ((int) ide_config_drive_speed(drive, speed));
399 }
400
401 static void sis5513_tune_drive (ide_drive_t *drive, byte pio)
402 {
403 (void) config_chipset_for_pio(drive, pio);
404 }
405
406 #ifdef CONFIG_BLK_DEV_IDEDMA
407 /*
408 * ((id->hw_config & 0x4000|0x2000) && (HWIF(drive)->udma_four))
409 */
410 static int config_chipset_for_dma (ide_drive_t *drive, byte ultra)
411 {
412 struct hd_driveid *id = drive->id;
413 ide_hwif_t *hwif = HWIF(drive);
414
415 byte four_two = 0, speed = 0;
416 int err;
417
418 byte unit = (drive->select.b.unit & 0x01);
419 byte udma_66 = eighty_ninty_three(drive);
420
421 if (host_dev) {
422 switch(host_dev->device) {
423 case PCI_DEVICE_ID_SI_530:
424 case PCI_DEVICE_ID_SI_540:
425 case PCI_DEVICE_ID_SI_620:
426 case PCI_DEVICE_ID_SI_630:
427 four_two = 0x01; break;
428 default:
429 four_two = 0x00; break;
430 }
431 }
432
433 if ((id->dma_ultra & 0x0010) && (ultra) && (udma_66) && (four_two))
434 speed = XFER_UDMA_4;
435 else if ((id->dma_ultra & 0x0008) && (ultra) && (udma_66) && (four_two))
436 speed = XFER_UDMA_3;
437 else if ((id->dma_ultra & 0x0004) && (ultra))
438 speed = XFER_UDMA_2;
439 else if ((id->dma_ultra & 0x0002) && (ultra))
440 speed = XFER_UDMA_1;
441 else if ((id->dma_ultra & 0x0001) && (ultra))
442 speed = XFER_UDMA_0;
443 else if (id->dma_mword & 0x0004)
444 speed = XFER_MW_DMA_2;
445 else if (id->dma_mword & 0x0002)
446 speed = XFER_MW_DMA_1;
447 else if (id->dma_mword & 0x0001)
448 speed = XFER_MW_DMA_0;
449 else if (id->dma_1word & 0x0004)
450 speed = XFER_SW_DMA_2;
451 else if (id->dma_1word & 0x0002)
452 speed = XFER_SW_DMA_1;
453 else if (id->dma_1word & 0x0001)
454 speed = XFER_SW_DMA_0;
455 else
456 return ((int) ide_dma_off_quietly);
457
458 outb(inb(hwif->dma_base+2)|(1<<(5+unit)), hwif->dma_base+2);
459
460 err = sis5513_tune_chipset(drive, speed);
461
462 #if SIS5513_DEBUG_DRIVE_INFO
463 printk("%s: %s drive%d\n", drive->name, ide_xfer_verbose(speed), drive->dn);
464 #endif /* SIS5513_DEBUG_DRIVE_INFO */
465
466 return ((int) ((id->dma_ultra >> 11) & 3) ? ide_dma_on :
467 ((id->dma_ultra >> 8) & 7) ? ide_dma_on :
468 ((id->dma_mword >> 8) & 7) ? ide_dma_on :
469 ((id->dma_1word >> 8) & 7) ? ide_dma_on :
470 ide_dma_off_quietly);
471 }
472
473 static int config_drive_xfer_rate (ide_drive_t *drive)
474 {
475 struct hd_driveid *id = drive->id;
476 ide_dma_action_t dma_func = ide_dma_off_quietly;
477
478 if (id && (id->capability & 1) && HWIF(drive)->autodma) {
479 /* Consult the list of known "bad" drives */
480 if (ide_dmaproc(ide_dma_bad_drive, drive)) {
481 dma_func = ide_dma_off;
482 goto fast_ata_pio;
483 }
484 dma_func = ide_dma_off_quietly;
485 if (id->field_valid & 4) {
486 if (id->dma_ultra & 0x001F) {
487 /* Force if Capable UltraDMA */
488 dma_func = config_chipset_for_dma(drive, 1);
489 if ((id->field_valid & 2) &&
490 (dma_func != ide_dma_on))
491 goto try_dma_modes;
492 }
493 } else if (id->field_valid & 2) {
494 try_dma_modes:
495 if ((id->dma_mword & 0x0007) ||
496 (id->dma_1word & 0x0007)) {
497 /* Force if Capable regular DMA modes */
498 dma_func = config_chipset_for_dma(drive, 0);
499 if (dma_func != ide_dma_on)
500 goto no_dma_set;
501 }
502 } else if ((ide_dmaproc(ide_dma_good_drive, drive)) &&
503 (id->eide_dma_time > 150)) {
504 /* Consult the list of known "good" drives */
505 dma_func = config_chipset_for_dma(drive, 0);
506 if (dma_func != ide_dma_on)
507 goto no_dma_set;
508 } else {
509 goto fast_ata_pio;
510 }
511 } else if ((id->capability & 8) || (id->field_valid & 2)) {
512 fast_ata_pio:
513 dma_func = ide_dma_off_quietly;
514 no_dma_set:
515 (void) config_chipset_for_pio(drive, 5);
516 }
517
518 return HWIF(drive)->dmaproc(dma_func, drive);
519 }
520
521 /*
522 * sis5513_dmaproc() initiates/aborts (U)DMA read/write operations on a drive.
523 */
524 int sis5513_dmaproc (ide_dma_action_t func, ide_drive_t *drive)
525 {
526 switch (func) {
527 case ide_dma_check:
528 config_drive_art_rwp(drive);
529 config_art_rwp_pio(drive, 5);
530 return config_drive_xfer_rate(drive);
531 default:
532 break;
533 }
534 return ide_dmaproc(func, drive); /* use standard DMA stuff */
535 }
536 #endif /* CONFIG_BLK_DEV_IDEDMA */
537
538 unsigned int __init pci_init_sis5513 (struct pci_dev *dev, const char *name)
539 {
540 struct pci_dev *host;
541 int i = 0;
542 byte latency = 0;
543
544 pci_read_config_byte(dev, PCI_LATENCY_TIMER, &latency);
545
546 for (i = 0; i < ARRAY_SIZE (SiSHostChipInfo) && !host_dev; i++) {
547 host = pci_find_device (PCI_VENDOR_ID_SI,
548 SiSHostChipInfo[i].host_id,
549 NULL);
550 if (!host)
551 continue;
552
553 host_dev = host;
554 printk(SiSHostChipInfo[i].name);
555 printk("\n");
556 if (SiSHostChipInfo[i].flags & SIS5513_FLAG_LATENCY) {
557 if (latency != 0x10)
558 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x10);
559 }
560 }
561
562 if (host_dev) {
563 byte reg52h = 0;
564
565 pci_read_config_byte(dev, 0x52, &reg52h);
566 if (!(reg52h & 0x04)) {
567 /* set IDE controller to operate in Compabitility mode only */
568 pci_write_config_byte(dev, 0x52, reg52h|0x04);
569 }
570 #if defined(DISPLAY_SIS_TIMINGS) && defined(CONFIG_PROC_FS)
571 if (!sis_proc) {
572 sis_proc = 1;
573 bmide_dev = dev;
574 sis_display_info = &sis_get_info;
575 }
576 #endif /* defined(DISPLAY_SIS_TIMINGS) && defined(CONFIG_PROC_FS) */
577 }
578 return 0;
579 }
580
581 unsigned int __init ata66_sis5513 (ide_hwif_t *hwif)
582 {
583 byte reg48h = 0, ata66 = 0;
584 byte mask = hwif->channel ? 0x20 : 0x10;
585 pci_read_config_byte(hwif->pci_dev, 0x48, &reg48h);
586
587 if (host_dev) {
588 switch(host_dev->device) {
589 case PCI_DEVICE_ID_SI_530:
590 case PCI_DEVICE_ID_SI_540:
591 case PCI_DEVICE_ID_SI_620:
592 case PCI_DEVICE_ID_SI_630:
593 ata66 = (reg48h & mask) ? 0 : 1;
594 default:
595 break;
596 }
597 }
598 return (ata66);
599 }
600
601 void __init ide_init_sis5513 (ide_hwif_t *hwif)
602 {
603
604 hwif->irq = hwif->channel ? 15 : 14;
605
606 hwif->tuneproc = &sis5513_tune_drive;
607 hwif->speedproc = &sis5513_tune_chipset;
608
609 if (!(hwif->dma_base))
610 return;
611
612 if (host_dev) {
613 switch(host_dev->device) {
614 #ifdef CONFIG_BLK_DEV_IDEDMA
615 case PCI_DEVICE_ID_SI_530:
616 case PCI_DEVICE_ID_SI_540:
617 case PCI_DEVICE_ID_SI_620:
618 case PCI_DEVICE_ID_SI_630:
619 case PCI_DEVICE_ID_SI_5600:
620 case PCI_DEVICE_ID_SI_5597:
621 case PCI_DEVICE_ID_SI_5591:
622 hwif->autodma = 1;
623 hwif->dmaproc = &sis5513_dmaproc;
624 break;
625 #endif /* CONFIG_BLK_DEV_IDEDMA */
626 default:
627 hwif->autodma = 0;
628 break;
629 }
630 }
631 return;
632 }
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