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Import 2.1.99pre2
[davej-history.git] / drivers / macintosh / imstt.c
blob0cf18edc712358e8dd8bccb17bffd029356048db
1 /*
2 * imstt.c: Console support for PowerMac "imstt" display adaptor.
3 *
4 * Copyright (C) 1997 Sigurdur Asgeirsson
5 * Modified by Danilo Beuche 1997
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version
10 * 2 of the License, or (at your option) any later version.
11 */
12 #include <linux/module.h>
13
14 #include <linux/kernel.h>
15 #include <linux/sched.h>
16 #include <linux/delay.h>
17 #include <linux/string.h>
18 #include <linux/vc_ioctl.h>
19 #include <linux/pci.h>
20 #include <linux/nvram.h>
21 #include <asm/prom.h>
22 #include <asm/io.h>
23 #include <asm/pgtable.h>
24 #include <asm/pci-bridge.h>
25 #include <linux/selection.h>
26 #include <linux/vt_kern.h>
27 #include "pmac-cons.h"
28 #include "imstt.h"
29
30
31 enum {
32 IBMRAMDAC = 0x00,
33 TVPRAMDAC = 0x01
34 };
35
36
37 // IMS TWIN TURBO
38 enum
39 {
40 S1SA = 0, /* 0x00 */
41 S2SA = 1, /* 0x04 */
42 SP = 2, /* 0x08 */
43 DSA = 3, /* 0x0C */
44 CNT = 4, /* 0x10 */
45 DP_OCTRL = 5, /* 0x14 */
46 BLTCTL = 10, /* 0x28 */
47
48 // Scan Timing Generator Registers
49 HES = 12, /* 0x30 */
50 HEB = 13, /* 0x34 */
51 HSB = 14, /* 0x38 */
52 HT = 15, /* 0x3C */
53 VES = 16, /* 0x40 */
54 VEB = 17, /* 0x44 */
55 VSB = 18, /* 0x48 */
56 VT = 19, /* 0x4C */
57 HCIV = 20, /* 0x50 */
58 VCIV = 21, /* 0x54 */
59 TCDR = 22, /* 0x58 */
60 VIL = 23, /* 0x5C */
61 STGCTL = 24, /* 0x60 */
62
63 // Screen Refresh Generator Registers
64 SSR = 25, /* 0x64 */
65 HRIR = 26, /* 0x68 */
66 SPR = 27, /* 0x6C */
67 CMR = 28, /* 0x70 */
68 SRGCTL = 29, /* 0x74 */
69
70 // RAM Refresh Generator Registers
71 RRCIV = 30, /* 0x78 */
72 RRSC = 31, /* 0x7C */
73 RRCR = 34, /* 0x88 */
74
75 // System Registers
76 GIOE = 32, /* 0x80 */
77 GIO = 33, /* 0x84 */
78 SCR = 35, /* 0x8C */
79 SSTATUS = 36, /* 0x90 */
80 PRC = 37, /* 0x94 */
81
82 #if 0
83 // PCI Registers
84 DVID = 0x00000000L,
85 SC = 0x00000004L,
86 CCR = 0x00000008L,
87 OG = 0x0000000CL,
88 BARM = 0x00000010L,
89 BARER = 0x00000030L,
90 #endif
91 };
92
93
94 // IBM RAMDAC
95 enum
96 {
97 PADDRW = 0x00,
98 PDATA = 0x04,
99 PPMASK = 0x08,
100 PADDRR = 0x0C,
101 PIDXLO = 0x10,
102 PIDXHI = 0x14,
103 PIDXDATA = 0x18,
104 PIDXCTL = 0x1C,
105
106 PPIXREP = 0x0A,
107 PM0 = 0x20,
108 PN0 = 0x21,
109 PP0 = 0x22,
110 PC0 = 0x23
111 };
112
113 // TI TVP 3030 RAMDAC Direct Registers
114 enum
115 {
116 TVPADDRW = 0x00, // 0 Palette/Cursor RAM Write Adress/Index
117 TVPPDATA = 0x04, // 1 Palette Data RAM Data
118 TVPPMASK = 0x08, // 2 Pixel Read-Mask
119 TVPPADRR = 0x0c, // 3 Palette/Cursor RAM Read Adress
120 TVPCADRW = 0x10, // 4 Cursor/Overscan Color Write Address
121 TVPCDATA = 0x14, // 5 Cursor/Overscan Color Data
122 // 6 reserved
123 TVPCADRR = 0x1c, // 7 Cursor/Overscan Color Read Address
124 // 8 reserved
125 TVPDCCTL = 0x24, // 9 Direct Cursor Control
126 TVPIDATA = 0x28, // 10 Index Data
127 TVPCRDAT = 0x2c, // 11 Cursor RAM Data
128 TVPCXPOL = 0x30, // 12 Cursor-Position X LSB
129 TVPCXPOH = 0x34, // 13 Cursor-Position X MSB
130 TVPCYPOL = 0x38, // 14 Cursor-Position Y LSB
131 TVPCYPOH = 0x3c, // 15 Cursor-Position Y MSB
132 };
133
134 // TI TVP 3030 RAMDAC Indirect Registers
135 enum
136 {
137 TVPIRREV = 0x01, // Silicon Revision [RO]
138 TVPIRICC = 0x06, // Indirect Cursor Control (0x00)
139 TVPIRBRC = 0x07, // Byte Router Control (0xe4)
140 TVPIRLAC = 0x0f, // Latch Control (0x06)
141 TVPIRTCC = 0x18, // True Color Control (0x80)
142 TVPIRMXC = 0x19, // Multiplex Control (0x98)
143 TVPIRCLS = 0x1a, // Clock Selection (0x07)
144 TVPIRPPG = 0x1c, // Palette Page (0x00)
145 TVPIRGEC = 0x1d, // General Control (0x00)
146 TVPIRMIC = 0x1e, // Miscellaneous Control (0x00)
147 TVPIRPLA = 0x2c, // PLL Address
148 TVPIRPPD = 0x2d, // Pixel Clock PLL Data
149 TVPIRMPD = 0x2e, // Memory Clock PLL Data
150 TVPIRLPD = 0x2f, // Loop Clock PLL Data
151 TVPIRCKL = 0x30, // Color-Key Overlay Low
152 TVPIRCKH = 0x31, // Color-Key Overlay High
153 TVPIRCRL = 0x32, // Color-Key Red Low
154 TVPIRCRH = 0x33, // Color-Key Red High
155 TVPIRCGL = 0x34, // Color-Key Green Low
156 TVPIRCGH = 0x35, // Color-Key Green High
157 TVPIRCBL = 0x36, // Color-Key Blue Low
158 TVPIRCBH = 0x37, // Color-Key Blue High
159 TVPIRCKC = 0x38, // Color-Key Control (0x00)
160 TVPIRMLC = 0x39, // MCLK/Loop Clock Control (0x18)
161 TVPIRSEN = 0x3a, // Sense Test (0x00)
162 TVPIRTMD = 0x3b, // Test Mode Data
163 TVPIRRML = 0x3c, // CRC Remainder LSB [RO]
164 TVPIRRMM = 0x3d, // CRC Remainder MSB [RO]
165 TVPIRRMS = 0x3e, // CRC Bit Select [WO]
166 TVPIRDID = 0x3f, // Device ID [RO] (0x30)
167 TVPIRRES = 0xff, // Software Reset [WO]
168
169 };
170
171 struct initvalues
172 {
173 unsigned char addr, value;
174 };
175
176
177
178 // Values which only depend on resolution not on color mode
179 struct tt_single_rmodevals
180 {
181 unsigned short hes;
182 unsigned short heb;
183 unsigned short hsb;
184 unsigned short ht;
185 unsigned short ves;
186 unsigned short veb;
187 unsigned short vsb;
188 unsigned short vt;
189 };
190
191 struct tvp_single_rmodevals
192 {
193 unsigned char pclk_n;
194 unsigned char pclk_m;
195 unsigned char pclk_p;
196 };
197
198 struct ibm_single_rmodevals
199 {
200 unsigned char pclk_m;
201 unsigned char pclk_n;
202 unsigned char pclk_p;
203 unsigned char pclk_c;
204 };
205
206 // Values which only depend on color mode not on resolution
207 struct tvp_single_cmodevals
208 {
209 unsigned char tcc; // True Color control
210 unsigned char mxc; // Multiplexer control
211 unsigned char lckl_n; // N value of LCKL PLL
212 };
213
214 struct ibm_single_cmodevals
215 {
216 unsigned char pformat; // pixel format
217 };
218
219 // Values of the tvp which change depending on colormode x resolution
220 struct tvp_single_crmodevals
221 {
222 unsigned char mlc; // Memory Loop Config 0x39
223 unsigned char lckl_p; // P value of LCKL PLL
224 };
225
226 struct ibm_single_crmodevals
227 {
228 // oh nothing changes
229 };
230
231 // complete configuration for a resolution in all depths
232 // 0 = 8 Bit, 15/16 bit = 1 , 32 Bit = 2
233 struct ims_crmodevals
234 {
235 int pitch;
236 struct tt_single_rmodevals tt[2]; // for each ramdac seperate tt config
237
238 struct tvp_single_rmodevals tvp_clock; // for each ramdac seperate clock config
239 struct tvp_single_crmodevals tvp[3]; // for each colormode
240
241 struct ibm_single_rmodevals ibm_clock; // for each ramdac seperate clock config
242 // struct ibm_single_crmodevals ibm[3]; // for each color mode
243 };
244
245 struct ims_modevals
246 {
247 int dac; // which dac do we have
248 int total_vram; // how much vram is on board
249 int sense; // what monitor
250 unsigned char* fb; // frame buffer address
251 unsigned char* fb_phys; // frame buffer address
252 unsigned char* cmap; // dac address
253 unsigned char* cmap_phys; // dac address
254 unsigned int* dc; // tt address
255 unsigned int* dc_phys; // tt address
256
257 struct initvalues* init[2]; // initial register settings for each ramdac
258
259 struct ims_crmodevals* mode[20]; // for each possible mode
260
261 struct tvp_single_cmodevals tvp[3]; // for each color mode
262
263 struct ibm_single_cmodevals ibm[3]; // for each color mode
264 };
265
266
267 struct ims_crmodevals imsmode_6 =
268 {
269 640,
270 {
271 { 0x08, 0x12, 0x62, 0x6C, 0x0003, 0x002A, 0x020A, 0x020C },
272 { 0x04, 0x0009, 0x0031, 0x0036, 0x0003, 0x002a, 0x020a, 0x020d },
273 },
274 { 0xef, 0x2e, 0xb2 },
275 {
276 { 0x39, 0xf3 },
277 { 0x39, 0xf3 },
278 { 0x38, 0xf3 }
279 },
280 // IBM CLOCK
281 { 0x78, 0x13, 0x02, 0x02 },
282 };
283
284 struct ims_crmodevals imsmode_13 =
285 {
286 832,
287 {
288 { 0x05, 0x20, 0x88, 0x90, 0x0003, 0x0028, 0x0298, 0x029B },
289 { 0x04, 0x0011, 0x0045, 0x0048, 0x0003, 0x002a, 0x029a, 0x029b},
290 },
291 { 0xfe, 0x3e, 0xf1 },
292 {
293 { 0x39, 0xf3 },
294 { 0x38, 0xf3 },
295 { 0x38, 0xf2 }
296 },
297 { 0x3E, 0x0A, 0x01, 0x02 }
298 };
299 struct ims_crmodevals imsmode_17 =
300 {
301 1024,
302 {
303 { 0x0A, 0x1C, 0x9C, 0xA6, 0x0003, 0x0020, 0x0320, 0x0323 } ,
304 { 0x06, 0x0210, 0x0250, 0x0053, 0x1003, 0x0021, 0x0321, 0x0324 },
305 },
306 { 0xfc, 0x3a, 0xf1 },
307 {
308 { 0x39, 0xf3 },
309 { 0x38, 0xf3 },
310 { 0x38, 0xf2 }
311 },
312 { 0x07, 0x00, 0x01, 0x02 }
313 };
314 struct ims_crmodevals imsmode_18 =
315 {
316 1152,
317 {
318 { 0, 0, 0, 0, 0, 0, 0, 0 },
319 { 0x09, 0x0011, 0x059, 0x5b, 0x0003, 0x0031, 0x0397, 0x039a },
320 },
321 { 0xfd, 0x3a, 0xf1 },
322 {
323 { 0x39, 0xf3 },
324 { 0x38, 0xf3 },
325 { 0x38, 0xf2 }
326 },
327 { 0, 0, 0, 0 }
328 };
329 struct ims_crmodevals imsmode_19 =
330 {
331 1280,
332 {
333 { 0, 0, 0, 0, 0, 0, 0, 0 },
334 { 0x09, 0x0016, 0x0066, 0x0069, 0x0003, 0x0027, 0x03e7, 0x03e8 },
335 },
336 { 0xf7, 0x36, 0xf0 },
337 {
338 { 0x38, 0xf3 },
339 { 0x38, 0xf2 },
340 { 0x38, 0xf1 }
341 },
342 { 0, 0, 0, 0 }
343 };
344 struct ims_crmodevals imsmode_20 =
345 {
346 1280,
347 {
348 { 0, 0, 0, 0, 0, 0, 0, 0 },
349 { 0x09, 0x0018, 0x0068, 0x006a, 0x0003, 0x0029, 0x0429, 0x042a },
350 },
351 { 0xf0, 0x2d, 0xf0 },
352 {
353 { 0x38, 0xf3 },
354 { 0x38, 0xf2 },
355 { 0x38, 0xf1 }
356 },
357 { 0, 0, 0, 0 }
358 };
359
360 // IBM RAMDAC initial register values
361
362 static struct initvalues ibm_initregs[] =
363 {
364 { 0x02, 0x21 }, /* (0x01) Miscellaneous Clock Control */
365 { 0x03, 0x00 }, /* (0x00) Sync Control */
366 { 0x04, 0x00 }, /* (0x00) Horizontal Sync Position */
367 { 0x05, 0x00 }, /* (0x00) Power Management */
368 { 0x06, 0x0B }, /* (0x02) DAC Operation */
369 { 0x07, 0x00 }, /* (0x00) Palette Control */
370 { 0x08, 0x01 }, /* (0x01) System Clock Control */
371 { 0x0B, 0x00 }, /* (U) 8 BPP Control */
372 { 0x0C, 0xC4 }, /* (U) 16 BPP Control */
373 { 0x0D, 0x00 }, /* (U) 24 BPP Packed Control */
374 { 0x0E, 0x03 }, /* (U) 32 BPP Control */
375 { 0x10, 0x05 }, /* (0x00) Pixel PLL Control 1 */
376 { 0x11, 0x00 }, /* (0x00) Pixel PLL Control 2 */
377 { 0x15, 0x08 }, /* (0x08) SYSCLK N (System PLL Reference Divider) */
378 { 0x16, 0x57 }, /* (0x41) SYSCLK M (System PLL VCO Divider) */
379 { 0x17, 0x00 }, /* (U) SYSCLK P */
380 { 0x18, 0x00 }, /* (U) SYSCLK C */
381 { 0x30, 0x00 }, /* (0x00) Cursor Control */
382 { 0x60, 0xFF }, /* (U) Border Color Red */
383 { 0x61, 0xFF }, /* (U) Border Color Green */
384 { 0x62, 0xFF }, /* (U) Border Color Blue */
385 { 0x70, 0x01 }, /* (0x00) Miscellaneous Control 1 */
386 { 0x71, 0x45 }, /* (0x00) Miscellaneous Control 2 */
387 { 0x72, 0x00 }, /* (0x00) Miscellaneous Control 3 */
388 { 0x78, 0x00 }, /* (0x00) Key Control/DB Operation */
389 { 0x00, 0x00 }
390 };
391
392
393 static struct initvalues tvp_initregs[] =
394 {
395 { 0x6, 0x00},
396 { 0x7, 0xe4},
397 { 0xf, 0x06},
398 { 0x18, 0x80},
399 { 0x19, 0x4d},
400 { 0x1a, 0x05},
401 { 0x1c, 0x00},
402 { 0x1d, 0x00},
403 { 0x1e, 0x08},
404 { 0x30, 0xff},
405 { 0x31, 0xff},
406 { 0x32, 0xff},
407 { 0x33, 0xff},
408 { 0x34, 0xff},
409 { 0x35, 0xff},
410 { 0x36, 0xff},
411 { 0x37, 0xff},
412 { 0x38, 0x00},
413 { TVPIRPLA, 0x00 },
414 { TVPIRPPD, 0xc0 },
415 { TVPIRPPD, 0xd5 },
416 { TVPIRPPD, 0xea },
417 { TVPIRPLA, 0x00 },
418 { TVPIRMPD, 0xb9 },
419 { TVPIRMPD, 0x3a },
420 { TVPIRMPD, 0xb1 },
421 { TVPIRPLA, 0x00 },
422 { TVPIRLPD, 0xc1 },
423 { TVPIRLPD, 0x3d },
424 { TVPIRLPD, 0xf3 },
425 { 0x00, 0x00 }
426 };
427
428
429 static struct ims_modevals ims_info =
430 {
431 -1, // DAC
432 -1, // VRAM
433 -1, // Monitor;
434 0, // Framebuffer
435 0, // Framebuffer_phys
436 0, // colormap
437 0, // colormap_phys
438 0, // dc
439 0, // dc_phys
440 { ibm_initregs, tvp_initregs},
441 {
442 NULL,
443 NULL,
444 NULL,
445 NULL,
446 &imsmode_6,
447 &imsmode_6,
448 NULL,
449 NULL,
450 NULL,
451 NULL,
452 NULL,
453 NULL,
454 &imsmode_13,
455 NULL,
456 NULL,
457 NULL,
458 &imsmode_17,
459 &imsmode_18,
460 &imsmode_19,
461 &imsmode_20
462 },
463 {
464 { 0x80, 0x4d, 0xc1 },
465 { 0x44, 0x55, 0xe1 },
466 { 0x46, 0x5d, 0xf1 }
467 },
468 {
469 { 0x03 },
470 { 0x04 },
471 { 0x06 }
472 }
473 };
474
475
476
477
478 // static void set_imstt_clock(unsigned char *params);
479 static void map_imstt_display(struct device_node *, int);
480 static int read_imstt_sense(void);
481 static int imstt_vram_reqd(int vmode, int cmode);
482
483
484 #if 0
485 static int get_tvp_ireg(int iaddr)
486 {
487 ims_info.cmap[0] = iaddr & 0xff; eieio();
488 return ims_info.cmap[40];
489 }
490 #endif
491
492 static void set_tvp_ireg(int iaddr,unsigned char value)
493 {
494 ims_info.cmap[0] = iaddr & 0xff; eieio();
495 ims_info.cmap[40] = value; eieio();
496 }
497 /*
498 * Get the monitor sense value.
499 * Note that this can be called before calibrate_delay,
500 * so we can't use udelay.
501 */
502 static int
503 read_imstt_sense()
504 {
505 #if 0
506 int sense;
507 unsigned gio, gioe;
508
509 gio = ld_le32(ims_info.dc + GIO) & ~0x0038;
510 gioe = ld_le32(dc_
511
512 out_le32(ims_info.dc + GIOE, reg); /* drive all lines high */
513 __delay(200);
514 out_le32(ims_info.dc + GIOE, 077); /* turn off drivers */
515 __delay(2000);
516 sense = (in_le32(ims_info.dc + GIOE) & 0x1c0) << 2;
517
518 /* drive each sense line low in turn and collect the other 2 */
519 out_le32(ims_info.dc + GIOE, 033); /* drive A low */
520 __delay(2000);
521 sense |= (in_le32(ims_info.dc + GIOE) & 0xc0) >> 2;
522 out_le32(ims_info.dc + GIOE, 055); /* drive B low */
523 __delay(2000);
524 sense |= ((in_le32(ims_info.dc + GIOE) & 0x100) >> 5)
525 | ((in_le32(ims_info.dc + GIOE) & 0x40) >> 4);
526 out_le32(ims_info.dc + GIOE, 066); /* drive C low */
527 __delay(2000);
528 sense |= (in_le32(ims_info.dc + GIOE) & 0x180) >> 7;
529
530 out_le32(ims_info.dc + GIOE, 077); /* turn off drivers */
531 return sense;
532 #else
533 return 0;
534 #endif
535 }
536
537 static inline int imstt_vram_reqd(int vmode, int cmode)
538 {
539 return vmode_attrs[vmode-1].vres *
540 (ims_info.mode[vmode-1])->pitch * ( 1 << cmode);
541 }
542
543 void
544 map_imstt_display_tvp(struct device_node *dp)
545 {
546 map_imstt_display(dp,1);
547 }
548
549 void
550 map_imstt_display_ibm(struct device_node *dp)
551 {
552 map_imstt_display(dp,0);
553 }
554
555 static void
556 map_imstt_display(struct device_node *dp, int which)
557 {
558 int i, sense;
559 unsigned long addr, size, tmp;
560 unsigned char bus, devfn;
561 unsigned short cmd;
562
563 if (dp->next != 0)
564 printk("Warning: only using first imstt display device\n");
565
566 #if 0
567 printk("pmac_display_init: node = %p, addrs =", dp->node);
568 for (i = 0; i < dp->n_addrs; ++i)
569 printk(" %x(%x)", dp->addrs[i].address, dp->addrs[i].size);
570 printk(", intrs =");
571 for (i = 0; i < dp->n_intrs; ++i)
572 printk(" %x", dp->intrs[i]);
573 printk("\n");
574 #endif
575
576 /* Map in frame buffer and registers */
577 for (i = 0; i < dp->n_addrs; ++i) {
578 addr = dp->addrs[i].address;
579 size = dp->addrs[i].size;
580 if (size >= 0x02000000) {
581 ims_info.fb = __ioremap(addr, size, _PAGE_NO_CACHE);
582 ims_info.fb_phys = (unsigned char*)addr;
583 ims_info.dc = (unsigned*)(ims_info.fb + 0x00800000);
584 ims_info.dc_phys = (unsigned*)(ims_info.fb_phys + 0x00800000);
585 ims_info.cmap = (unsigned char*)(ims_info.fb + 0x00840000);
586 ims_info.cmap_phys = (unsigned char*)(ims_info.fb_phys + 0x00840000);
587 printk("mapped ims_info.fb=%x(%x)", (unsigned)ims_info.fb, (unsigned)size);
588 printk(" ims_info.dc=%x, ims_info.cmap=%x\n", (unsigned)ims_info.dc, (unsigned)ims_info.cmap);
589 }
590 }
591
592 /* enable memory-space accesses using config-space command register */
593 if (pci_device_loc(dp, &bus, &devfn) == 0) {
594 pcibios_read_config_word(bus, devfn, PCI_COMMAND, &cmd);
595
596 printk("command word 0x%04X\n", cmd);
597
598 if (cmd != 0xffff) {
599 cmd |= PCI_COMMAND_MEMORY;
600 pcibios_write_config_word(bus, devfn, PCI_COMMAND, cmd);
601 }
602 }
603 else
604 printk("unable to find pci device\n");
605
606 tmp = in_le32(ims_info.dc + SSTATUS);
607 printk("chip version %ld, ", (tmp & 0x0F00) >> 8);
608
609 tmp = in_le32(ims_info.dc + PRC);
610
611 if (0 == which )
612 ims_info.total_vram = (tmp & 0x0004) ? 0x000400000L : 0x000200000L;
613 else
614 ims_info.total_vram = 0x000800000L;
615
616 printk("VRAM size %ldM\n", ims_info.total_vram / 0x000100000L);
617
618 if (ims_info.total_vram == 0x000800000L)
619 {
620 ims_info.dac = TVPRAMDAC;
621 printk("Selecting TVP 3030 RAMDAC\n");
622 }
623 else
624 {
625 ims_info.dac = IBMRAMDAC;
626 printk("Selecting IBM RAMDAC\n");
627 }
628
629 sense = read_imstt_sense();
630 printk("Monitor sense value = 0x%x, ", sense);
631 #if 0
632 if (video_mode == VMODE_NVRAM) {
633 video_mode = nvram_read_byte(NV_VMODE);
634 if (video_mode <= 0 || video_mode > VMODE_MAX
635 || imstt_reg_init[video_mode-1] == 0)
636 video_mode = VMODE_CHOOSE;
637 }
638 if (video_mode == VMODE_CHOOSE)
639 video_mode = map_monitor_sense(sense);
640 if (imstt_reg_init[video_mode-1] == 0)
641 video_mode = VMODE_640_480_67;
642
643 /*
644 * Reduce the pixel size if we don't have enough VRAM.
645 */
646 if (color_mode == CMODE_NVRAM)
647 color_mode = nvram_read_byte(NV_CMODE);
648 if (color_mode < CMODE_8 || color_mode > CMODE_32)
649 color_mode = CMODE_8;
650 while (color_mode > CMODE_8
651 && imstt_vram_reqd(video_mode, color_mode) > ims_info.total_vram)
652 --color_mode;
653
654 #endif
655 // Hack Hack Hack !!!
656 video_mode = VMODE_640_480_67;
657 color_mode = CMODE_8;
658 }
659
660 /*
661 * We dont need it ( all is done in ims_init )
662 static void
663 set_imstt_clock_tvp(char* tvprv)
664 {
665 int j;
666 for (j=0;j<3;j++)
667 {
668 set_tvp_ireg(TVPIRPLA,(j << 4) | (j << 2) | j); // Select same value for all plls
669 set_tvp_ireg(TVPIRPPD,tvprv[j]);
670 set_tvp_ireg(TVPIRMPD,tvprv[3+j]);
671 set_tvp_ireg(TVPIRLPD,tvprv[6+j]);
672 }
673 }
674
675 static void
676 set_imstt_clock_ibm(unsigned char *params)
677 {
678 ims_info.cmap[PIDXHI] = 0; eieio();
679 ims_info.cmap[PIDXLO] = PM0; eieio();
680 ims_info.cmap[PIDXDATA] = params[0]; eieio();
681
682 ims_info.cmap[PIDXLO] = PN0; eieio();
683 ims_info.cmap[PIDXDATA] = params[1]; eieio();
684
685 ims_info.cmap[PIDXLO] = PP0; eieio();
686 ims_info.cmap[PIDXDATA] = params[2]; eieio();
687
688 ims_info.cmap[PIDXLO] = PC0; eieio();
689 ims_info.cmap[PIDXDATA] = params[3]; eieio();
690 }
691 */
692
693 void
694 imstt_init()
695 {
696 int i, yoff, hres;
697 unsigned long ctl, pitch, tmp, scrCmode;
698 struct ims_crmodevals *init;
699
700 if (video_mode <= 0 || video_mode > VMODE_MAX ) panic("imstt: display mode %d not supported(not in valid range)", video_mode);
701 if ((init = ims_info.mode[video_mode-1]) == 0) panic("imstt: display mode %d not supported(no mode definition)", video_mode);
702 if (init->tt[ims_info.dac].vt == 0) panic("imstt: display mode %d not supported (no timing definition)", video_mode);
703
704
705 n_scanlines = vmode_attrs[video_mode-1].vres;
706 hres = vmode_attrs[video_mode-1].hres;
707 pixel_size = 1 << color_mode;
708 line_pitch = init->pitch * pixel_size;
709 row_pitch = line_pitch * 16;
710
711 /* initialize the card */
712 tmp = in_le32(ims_info.dc + STGCTL);
713 out_le32(ims_info.dc + STGCTL, tmp & ~0x1);
714 #if 0
715 out_le32(ims_info.dc + SCR, 0);
716 #endif
717
718 switch(ims_info.dac)
719 {
720 case IBMRAMDAC:
721 ims_info.cmap[PPMASK] = 0xFF; eieio();
722 ims_info.cmap[PIDXHI] = 0x00; eieio();
723 for (i = 0; ims_info.init[IBMRAMDAC][i].addr != 0 && ims_info.init[IBMRAMDAC][i].value != 0 ;i++)
724 {
725 ims_info.cmap[PIDXLO] = ims_info.init[IBMRAMDAC][i].addr; eieio();
726 ims_info.cmap[PIDXDATA] = ims_info.init[IBMRAMDAC][i].value; eieio();
727 }
728
729 ims_info.cmap[PIDXHI] = 0; eieio();
730 ims_info.cmap[PIDXLO] = PM0; eieio();
731 ims_info.cmap[PIDXDATA] = init->ibm_clock.pclk_m; eieio();
732
733 ims_info.cmap[PIDXLO] = PN0; eieio();
734 ims_info.cmap[PIDXDATA] = init->ibm_clock.pclk_n; eieio();
735
736 ims_info.cmap[PIDXLO] = PP0; eieio();
737 ims_info.cmap[PIDXDATA] = init->ibm_clock.pclk_p; eieio();
738
739 ims_info.cmap[PIDXLO] = PC0; eieio();
740 ims_info.cmap[PIDXDATA] = init->ibm_clock.pclk_c; eieio();
741
742 ims_info.cmap[PIDXLO] = PPIXREP; eieio();
743 ims_info.cmap[PIDXDATA] = ims_info.ibm[color_mode].pformat; eieio();
744
745 break;
746 case TVPRAMDAC:
747 for (i = 0; ims_info.init[TVPRAMDAC][i].addr != 0 && ims_info.init[TVPRAMDAC][i].value != 0 ;i++)
748 {
749 set_tvp_ireg(ims_info.init[TVPRAMDAC][i].addr,ims_info.init[TVPRAMDAC][i].value);
750 }
751 set_tvp_ireg(TVPIRPLA,0x00);
752 set_tvp_ireg(TVPIRPPD,init->tvp_clock.pclk_n);
753 set_tvp_ireg(TVPIRPPD,init->tvp_clock.pclk_m);
754 set_tvp_ireg(TVPIRPPD,init->tvp_clock.pclk_p);
755
756 set_tvp_ireg(TVPIRTCC,ims_info.tvp[color_mode].tcc);
757 set_tvp_ireg(TVPIRMXC,ims_info.tvp[color_mode].mxc);
758
759 set_tvp_ireg(TVPIRPLA,0x00);
760 set_tvp_ireg(TVPIRLPD,ims_info.tvp[color_mode].lckl_n);
761
762 set_tvp_ireg(TVPIRPLA,0x15);
763 set_tvp_ireg(TVPIRMLC,(init->tvp[color_mode]).mlc);
764
765 set_tvp_ireg(TVPIRPLA,0x2a);
766 set_tvp_ireg(TVPIRLPD,init->tvp[color_mode].lckl_p);
767 break;
768 }
769
770
771 switch(color_mode) {
772 case CMODE_32:
773 ctl = 0x1785;
774 pitch = init->pitch;
775 scrCmode = 0x300;
776 break;
777 case CMODE_16:
778 ctl = 0x1783;
779 pitch = init->pitch / 2;
780 scrCmode = 0x100;
781 break;
782 case CMODE_8:
783 default:
784 ctl = 0x1781;
785 pitch = init->pitch / 4;
786 scrCmode = 0x000;
787 break;
788 }
789
790 out_le32(&ims_info.dc[HES], init->tt[ims_info.dac].hes);
791 out_le32(&ims_info.dc[HEB], init->tt[ims_info.dac].heb);
792 out_le32(&ims_info.dc[HSB], init->tt[ims_info.dac].hsb);
793 out_le32(&ims_info.dc[HT], init->tt[ims_info.dac].ht);
794 out_le32(&ims_info.dc[VES], init->tt[ims_info.dac].ves);
795 out_le32(&ims_info.dc[VEB], init->tt[ims_info.dac].veb);
796 out_le32(&ims_info.dc[VSB], init->tt[ims_info.dac].vsb);
797 out_le32(&ims_info.dc[VT], init->tt[ims_info.dac].vt);
798 out_le32(&ims_info.dc[HCIV], 1);
799 out_le32(&ims_info.dc[VCIV], 1);
800 out_le32(&ims_info.dc[TCDR], 4);
801 out_le32(&ims_info.dc[VIL], 0);
802
803 out_le32(&ims_info.dc[SSR], 0);
804 out_le32(&ims_info.dc[HRIR], 0x0200);
805 out_le32(&ims_info.dc[CMR], 0x01FF);
806 out_le32(&ims_info.dc[SRGCTL], 0x0003);
807 switch(ims_info.total_vram)
808 {
809 case 0x000200000:
810 out_le32(&ims_info.dc[SCR], 0x0059D| scrCmode);
811 break;
812 case 0x000400000:
813 pitch /= 2;
814 out_le32(&ims_info.dc[SCR], 0x00D0DC | scrCmode);
815 break;
816 case 0x000800000:
817 pitch /= 2;
818 out_le32(&ims_info.dc[SCR], 0x0150DD | scrCmode);
819 break;
820 }
821
822 out_le32(&ims_info.dc[SPR], pitch);
823
824 if (ims_info.dac == IBMRAMDAC)
825 {
826
827
828 }
829
830 pmac_init_palette(); /* Initialize colormap */
831
832 out_le32(&ims_info.dc[STGCTL], ctl);
833
834 yoff = (n_scanlines % 16) / 2;
835 fb_start = ims_info.fb + yoff * line_pitch;
836
837 /* Clear screen */
838 {
839 unsigned long *p;
840 p = (unsigned long*)ims_info.fb;
841 for (i = n_scanlines * line_pitch / sizeof(unsigned); i != 0; --i)
842 *p++ = 0;
843 }
844
845 display_info.height = n_scanlines;
846 display_info.width = hres;
847 display_info.depth = pixel_size * 8;
848 display_info.pitch = line_pitch;
849 display_info.mode = video_mode;
850
851 if (ims_info.dac == IBMRAMDAC )
852 strncpy(display_info.name, "IMS,tt128mb2/4", sizeof(display_info.name));
853 else
854 strncpy(display_info.name, "IMS,tt128mb8/8A", sizeof(display_info.name));
855
856 display_info.fb_address = (unsigned long) ims_info.fb_phys;
857 display_info.cmap_adr_address = (unsigned long) &ims_info.cmap_phys[PADDRW];
858 display_info.cmap_data_address = (unsigned long) &ims_info.cmap_phys[PDATA];
859 display_info.disp_reg_address = (unsigned long) NULL;
860 }
861
862 int
863 imstt_setmode(struct vc_mode *mode, int doit)
864 {
865 int cmode;
866 struct ims_crmodevals *init;
867
868 if (video_mode <= 0 || video_mode > VMODE_MAX )
869 return -EINVAL;
870 if ((init = ims_info.mode[video_mode-1]) == 0)
871 return -EINVAL;
872 if (init->tt[ims_info.dac].vt == 0)
873 return -EINVAL;
874
875 if (mode->mode <= 0 || mode->mode > VMODE_MAX
876 || (ims_info.mode[mode->mode-1] == 0))
877 return -EINVAL;
878 switch (mode->depth) {
879 case 24:
880 case 32:
881 cmode = CMODE_32;
882 break;
883 case 16:
884 cmode = CMODE_16;
885 break;
886 case 8:
887 case 0: /* (default) */
888 cmode = CMODE_8;
889 break;
890 default:
891 return -EINVAL;
892 }
893 if (imstt_vram_reqd(mode->mode, cmode) > ims_info.total_vram)
894 return -EINVAL;
895 if (doit) {
896 video_mode = mode->mode;
897 color_mode = cmode;
898 imstt_init();
899 }
900 return 0;
901 }
902
903 // set palette for TI TVP3030 ramdac (used on 8MB version)
904 void
905 imstt_set_palette_tvp(unsigned char red[], unsigned char green[],
906 unsigned char blue[], int index, int ncolors)
907 {
908 int i;
909 for (i = 0; i < ncolors; ++i) {
910 ims_info.cmap[TVPADDRW] = index + i; eieio();
911 ims_info.cmap[TVPPDATA] = red[i]; eieio();
912 ims_info.cmap[TVPPDATA] = green[i]; eieio();
913 ims_info.cmap[TVPPDATA] = blue[i]; eieio();
914 }
915 }
916
917 // set palette for IBM ramdac (used on 2MB/4MB version)
918 void
919 imstt_set_palette_ibm(unsigned char red[], unsigned char green[],
920 unsigned char blue[], int index, int ncolors)
921 {
922 int i;
923
924 for (i = 0; i < ncolors; ++i) {
925 ims_info.cmap[PADDRW] = index + i; eieio();
926 ims_info.cmap[PDATA] = red[i]; eieio();
927 ims_info.cmap[PDATA] = green[i]; eieio();
928 ims_info.cmap[PDATA] = blue[i]; eieio();
929 }
930 }
931
932 void
933 imstt_set_blanking(int blank_mode)
934 {
935 long ctrl;
936
937 ctrl = ld_le32(ims_info.dc + STGCTL) | 0x0030;
938 if (blank_mode & VESA_VSYNC_SUSPEND)
939 ctrl &= ~0x0020;
940 if (blank_mode & VESA_HSYNC_SUSPEND)
941 ctrl &= ~0x0010;
942 out_le32(ims_info.dc + STGCTL, ctrl);
943 }
944
945
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