2 * linux/arch/i386/kernel/time.c
4 * Copyright (C) 1991, 1992, 1995 Linus Torvalds
6 * This file contains the PC-specific time handling details:
7 * reading the RTC at bootup, etc..
8 * 1994-07-02 Alan Modra
9 * fixed set_rtc_mmss, fixed time.year for >= 2000, new mktime
10 * 1995-03-26 Markus Kuhn
11 * fixed 500 ms bug at call to set_rtc_mmss, fixed DS12887
12 * precision CMOS clock update
13 * 1996-05-03 Ingo Molnar
14 * fixed time warps in do_[slow|fast]_gettimeoffset()
15 * 1997-09-10 Updated NTP code according to technical memorandum Jan '96
16 * "A Kernel Model for Precision Timekeeping" by Dave Mills
17 * 1998-09-05 (Various)
18 * More robust do_fast_gettimeoffset() algorithm implemented
19 * (works with APM, Cyrix 6x86MX and Centaur C6),
20 * monotonic gettimeofday() with fast_get_timeoffset(),
21 * drift-proof precision TSC calibration on boot
22 * (C. Scott Ananian <cananian@alumni.princeton.edu>, Andrew D.
23 * Balsa <andrebalsa@altern.org>, Philip Gladstone <philip@raptor.com>;
24 * ported from 2.0.35 Jumbo-9 by Michael Krause <m.krause@tu-harburg.de>).
25 * 1998-12-16 Andrea Arcangeli
26 * Fixed Jumbo-9 code in 2.1.131: do_gettimeofday was missing 1 jiffy
27 * because was not accounting lost_ticks.
28 * 1998-12-24 Copyright (C) 1998 Andrea Arcangeli
29 * Fixed a xtime SMP race (we need the xtime_lock rw spinlock to
30 * serialize accesses to xtime/lost_ticks).
33 #include <linux/errno.h>
34 #include <linux/sched.h>
35 #include <linux/kernel.h>
36 #include <linux/param.h>
37 #include <linux/string.h>
39 #include <linux/interrupt.h>
40 #include <linux/time.h>
41 #include <linux/delay.h>
42 #include <linux/init.h>
43 #include <linux/smp.h>
49 #include <asm/delay.h>
50 #include <asm/mpspec.h>
51 #include <asm/uaccess.h>
52 #include <asm/processor.h>
54 #include <linux/mc146818rtc.h>
55 #include <linux/timex.h>
56 #include <linux/config.h>
58 #include <asm/fixmap.h>
59 #include <asm/cobalt.h>
62 * for x86_do_profile()
64 #include <linux/irq.h>
67 unsigned long cpu_hz
; /* Detected as we calibrate the TSC */
69 /* Number of usecs that the last interrupt was delayed */
70 static int delay_at_last_interrupt
;
72 static unsigned long last_tsc_low
; /* lsb 32 bits of Time Stamp Counter */
74 /* Cached *multiplier* to convert TSC counts to microseconds.
75 * (see the equation below).
76 * Equal to 2^32 * (1 / (clocks per usec) ).
77 * Initialized in time_init.
79 unsigned long fast_gettimeoffset_quotient
=0;
81 extern rwlock_t xtime_lock
;
82 extern unsigned long wall_jiffies
;
84 spinlock_t rtc_lock
= SPIN_LOCK_UNLOCKED
;
86 static inline unsigned long do_fast_gettimeoffset(void)
88 register unsigned long eax
, edx
;
90 /* Read the Time Stamp Counter */
94 /* .. relative to previous jiffy (32 bits is enough) */
95 eax
-= last_tsc_low
; /* tsc_low delta */
98 * Time offset = (tsc_low delta) * fast_gettimeoffset_quotient
99 * = (tsc_low delta) * (usecs_per_clock)
100 * = (tsc_low delta) * (usecs_per_jiffy / clocks_per_jiffy)
102 * Using a mull instead of a divl saves up to 31 clock cycles
103 * in the critical path.
107 :"=a" (eax
), "=d" (edx
)
108 :"g" (fast_gettimeoffset_quotient
),
111 /* our adjusted time offset in microseconds */
112 return delay_at_last_interrupt
+ edx
;
115 #define TICK_SIZE tick
117 spinlock_t i8253_lock
= SPIN_LOCK_UNLOCKED
;
119 extern spinlock_t i8259A_lock
;
121 #ifndef CONFIG_X86_TSC
123 /* This function must be called with interrupts disabled
124 * It was inspired by Steve McCanne's microtime-i386 for BSD. -- jrs
126 * However, the pc-audio speaker driver changes the divisor so that
127 * it gets interrupted rather more often - it loads 64 into the
128 * counter rather than 11932! This has an adverse impact on
129 * do_gettimeoffset() -- it stops working! What is also not
130 * good is that the interval that our timer function gets called
131 * is no longer 10.0002 ms, but 9.9767 ms. To get around this
132 * would require using a different timing source. Maybe someone
133 * could use the RTC - I know that this can interrupt at frequencies
134 * ranging from 8192Hz to 2Hz. If I had the energy, I'd somehow fix
135 * it so that at startup, the timer code in sched.c would select
136 * using either the RTC or the 8253 timer. The decision would be
137 * based on whether there was any other device around that needed
138 * to trample on the 8253. I'd set up the RTC to interrupt at 1024 Hz,
139 * and then do some jiggery to have a version of do_timer that
140 * advanced the clock by 1/1024 s. Every time that reached over 1/100
141 * of a second, then do all the old code. If the time was kept correct
142 * then do_gettimeoffset could just return 0 - there is no low order
143 * divider that can be accessed.
145 * Ideally, you would be able to use the RTC for the speaker driver,
146 * but it appears that the speaker driver really needs interrupt more
147 * often than every 120 us or so.
149 * Anyway, this needs more thought.... pjsg (1993-08-28)
151 * If you are really that interested, you should be reading
152 * comp.protocols.time.ntp!
155 static unsigned long do_slow_gettimeoffset(void)
159 static int count_p
= LATCH
; /* for the first call after boot */
160 static unsigned long jiffies_p
= 0;
163 * cache volatile jiffies temporarily; we have IRQs turned off.
165 unsigned long jiffies_t
;
167 /* gets recalled with irq locally disabled */
168 spin_lock(&i8253_lock
);
169 /* timer count may underflow right here */
170 outb_p(0x00, 0x43); /* latch the count ASAP */
172 count
= inb_p(0x40); /* read the latched count */
175 * We do this guaranteed double memory access instead of a _p
176 * postfix in the previous port access. Wheee, hackady hack
180 count
|= inb_p(0x40) << 8;
181 spin_unlock(&i8253_lock
);
184 * avoiding timer inconsistencies (they are rare, but they happen)...
185 * there are two kinds of problems that must be avoided here:
186 * 1. the timer counter underflows
187 * 2. hardware problem with the timer, not giving us continuous time,
188 * the counter does small "jumps" upwards on some Pentium systems,
189 * (see c't 95/10 page 335 for Neptun bug.)
192 /* you can safely undefine this if you don't have the Neptune chipset */
194 #define BUGGY_NEPTUN_TIMER
196 if( jiffies_t
== jiffies_p
) {
197 if( count
> count_p
) {
202 spin_lock(&i8259A_lock
);
204 * This is tricky when I/O APICs are used;
205 * see do_timer_interrupt().
208 spin_unlock(&i8259A_lock
);
210 /* assumption about timer being IRQ0 */
213 * We cannot detect lost timer interrupts ...
214 * well, that's why we call them lost, don't we? :)
215 * [hmm, on the Pentium and Alpha we can ... sort of]
219 #ifdef BUGGY_NEPTUN_TIMER
221 * for the Neptun bug we know that the 'latch'
222 * command doesnt latch the high and low value
223 * of the counter atomically. Thus we have to
224 * substract 256 from the counter
225 * ... funny, isnt it? :)
230 printk("do_slow_gettimeoffset(): hardware timer problem?\n");
235 jiffies_p
= jiffies_t
;
239 count
= ((LATCH
-1) - count
) * TICK_SIZE
;
240 count
= (count
+ LATCH
/2) / LATCH
;
245 static unsigned long (*do_gettimeoffset
)(void) = do_slow_gettimeoffset
;
249 #define do_gettimeoffset() do_fast_gettimeoffset()
254 * This version of gettimeofday has microsecond resolution
255 * and better than microsecond precision on fast x86 machines with TSC.
257 void do_gettimeofday(struct timeval
*tv
)
260 unsigned long usec
, sec
;
262 read_lock_irqsave(&xtime_lock
, flags
);
263 usec
= do_gettimeoffset();
265 unsigned long lost
= jiffies
- wall_jiffies
;
267 usec
+= lost
* (1000000 / HZ
);
270 usec
+= xtime
.tv_usec
;
271 read_unlock_irqrestore(&xtime_lock
, flags
);
273 while (usec
>= 1000000) {
282 void do_settimeofday(struct timeval
*tv
)
284 write_lock_irq(&xtime_lock
);
286 * This is revolting. We need to set "xtime" correctly. However, the
287 * value in this location is the value at the most recent update of
288 * wall time. Discover what correction gettimeofday() would have
289 * made, and then undo it!
291 tv
->tv_usec
-= do_gettimeoffset();
292 tv
->tv_usec
-= (jiffies
- wall_jiffies
) * (1000000 / HZ
);
294 while (tv
->tv_usec
< 0) {
295 tv
->tv_usec
+= 1000000;
300 time_adjust
= 0; /* stop active adjtime() */
301 time_status
|= STA_UNSYNC
;
302 time_maxerror
= NTP_PHASE_LIMIT
;
303 time_esterror
= NTP_PHASE_LIMIT
;
304 write_unlock_irq(&xtime_lock
);
308 * In order to set the CMOS clock precisely, set_rtc_mmss has to be
309 * called 500 ms after the second nowtime has started, because when
310 * nowtime is written into the registers of the CMOS clock, it will
311 * jump to the next second precisely 500 ms later. Check the Motorola
312 * MC146818A or Dallas DS12887 data sheet for details.
314 * BUG: This routine does not handle hour overflow properly; it just
315 * sets the minutes. Usually you'll only notice that after reboot!
317 static int set_rtc_mmss(unsigned long nowtime
)
320 int real_seconds
, real_minutes
, cmos_minutes
;
321 unsigned char save_control
, save_freq_select
;
323 /* gets recalled with irq locally disabled */
324 spin_lock(&rtc_lock
);
325 save_control
= CMOS_READ(RTC_CONTROL
); /* tell the clock it's being set */
326 CMOS_WRITE((save_control
|RTC_SET
), RTC_CONTROL
);
328 save_freq_select
= CMOS_READ(RTC_FREQ_SELECT
); /* stop and reset prescaler */
329 CMOS_WRITE((save_freq_select
|RTC_DIV_RESET2
), RTC_FREQ_SELECT
);
331 cmos_minutes
= CMOS_READ(RTC_MINUTES
);
332 if (!(save_control
& RTC_DM_BINARY
) || RTC_ALWAYS_BCD
)
333 BCD_TO_BIN(cmos_minutes
);
336 * since we're only adjusting minutes and seconds,
337 * don't interfere with hour overflow. This avoids
338 * messing with unknown time zones but requires your
339 * RTC not to be off by more than 15 minutes
341 real_seconds
= nowtime
% 60;
342 real_minutes
= nowtime
/ 60;
343 if (((abs(real_minutes
- cmos_minutes
) + 15)/30) & 1)
344 real_minutes
+= 30; /* correct for half hour time zone */
347 if (abs(real_minutes
- cmos_minutes
) < 30) {
348 if (!(save_control
& RTC_DM_BINARY
) || RTC_ALWAYS_BCD
) {
349 BIN_TO_BCD(real_seconds
);
350 BIN_TO_BCD(real_minutes
);
352 CMOS_WRITE(real_seconds
,RTC_SECONDS
);
353 CMOS_WRITE(real_minutes
,RTC_MINUTES
);
356 "set_rtc_mmss: can't update from %d to %d\n",
357 cmos_minutes
, real_minutes
);
361 /* The following flags have to be released exactly in this order,
362 * otherwise the DS12887 (popular MC146818A clone with integrated
363 * battery and quartz) will not reset the oscillator and will not
364 * update precisely 500 ms later. You won't find this mentioned in
365 * the Dallas Semiconductor data sheets, but who believes data
366 * sheets anyway ... -- Markus Kuhn
368 CMOS_WRITE(save_control
, RTC_CONTROL
);
369 CMOS_WRITE(save_freq_select
, RTC_FREQ_SELECT
);
370 spin_unlock(&rtc_lock
);
375 /* last time the cmos clock got updated */
376 static long last_rtc_update
= 0;
381 * timer_interrupt() needs to keep up the real-time clock,
382 * as well as call the "do_timer()" routine every clocktick
384 static inline void do_timer_interrupt(int irq
, void *dev_id
, struct pt_regs
*regs
)
386 #ifdef CONFIG_X86_IO_APIC
389 * Subtle, when I/O APICs are used we have to ack timer IRQ
390 * manually to reset the IRR bit for do_slow_gettimeoffset().
391 * This will also deassert NMI lines for the watchdog if run
392 * on an 82489DX-based system.
394 spin_lock(&i8259A_lock
);
396 /* Ack the IRQ; AEOI will end it automatically. */
398 spin_unlock(&i8259A_lock
);
403 /* Clear the interrupt */
404 co_cpu_write(CO_CPU_STAT
,co_cpu_read(CO_CPU_STAT
) & ~CO_STAT_TIMEINTR
);
408 * In the SMP case we use the local APIC timer interrupt to do the
409 * profiling, except when we simulate SMP mode on a uniprocessor
410 * system, in that case we have to call the local interrupt handler.
412 #ifndef CONFIG_X86_LOCAL_APIC
413 if (!user_mode(regs
))
414 x86_do_profile(regs
->eip
);
416 if (!smp_found_config
)
417 smp_local_timer_interrupt(regs
);
421 * If we have an externally synchronized Linux clock, then update
422 * CMOS clock accordingly every ~11 minutes. Set_rtc_mmss() has to be
423 * called as close as possible to 500 ms before the new second starts.
425 if ((time_status
& STA_UNSYNC
) == 0 &&
426 xtime
.tv_sec
> last_rtc_update
+ 660 &&
427 xtime
.tv_usec
>= 500000 - ((unsigned) tick
) / 2 &&
428 xtime
.tv_usec
<= 500000 + ((unsigned) tick
) / 2) {
429 if (set_rtc_mmss(xtime
.tv_sec
) == 0)
430 last_rtc_update
= xtime
.tv_sec
;
432 last_rtc_update
= xtime
.tv_sec
- 600; /* do it again in 60 s */
437 /* The PS/2 uses level-triggered interrupts. You can't
438 turn them off, nor would you want to (any attempt to
439 enable edge-triggered interrupts usually gets intercepted by a
440 special hardware circuit). Hence we have to acknowledge
441 the timer interrupt. Through some incredibly stupid
442 design idea, the reset for IRQ 0 is done by setting the
443 high bit of the PPI port B (0x61). Note that some PS/2s,
444 notably the 55SX, work fine if this is removed. */
446 irq
= inb_p( 0x61 ); /* read the current state */
447 outb_p( irq
|0x80, 0x61 ); /* reset the IRQ */
452 static int use_tsc
= 0;
455 * This is the same as the above, except we _also_ save the current
456 * Time Stamp Counter value at the time of the timer interrupt, so that
457 * we later on can estimate the time of day more exactly.
459 static void timer_interrupt(int irq
, void *dev_id
, struct pt_regs
*regs
)
464 * Here we are in the timer irq handler. We just have irqs locally
465 * disabled but we don't know if the timer_bh is running on the other
466 * CPU. We need to avoid to SMP race with it. NOTE: we don' t need
467 * the irq version of write_lock because as just said we have irq
468 * locally disabled. -arca
470 write_lock(&xtime_lock
);
475 * It is important that these two operations happen almost at
476 * the same time. We do the RDTSC stuff first, since it's
477 * faster. To avoid any inconsistencies, we need interrupts
482 * Interrupts are just disabled locally since the timer irq
483 * has the SA_INTERRUPT flag set. -arca
486 /* read Pentium cycle counter */
488 rdtscl(last_tsc_low
);
490 spin_lock(&i8253_lock
);
491 outb_p(0x00, 0x43); /* latch the count ASAP */
493 count
= inb_p(0x40); /* read the latched count */
494 count
|= inb(0x40) << 8;
495 spin_unlock(&i8253_lock
);
497 count
= ((LATCH
-1) - count
) * TICK_SIZE
;
498 delay_at_last_interrupt
= (count
+ LATCH
/2) / LATCH
;
501 do_timer_interrupt(irq
, NULL
, regs
);
503 write_unlock(&xtime_lock
);
507 /* not static: needed by APM */
508 unsigned long get_cmos_time(void)
510 unsigned int year
, mon
, day
, hour
, min
, sec
;
513 /* The Linux interpretation of the CMOS clock register contents:
514 * When the Update-In-Progress (UIP) flag goes from 1 to 0, the
515 * RTC registers show the second which has precisely just started.
516 * Let's hope other operating systems interpret the RTC the same way.
518 /* read RTC exactly on falling edge of update flag */
519 for (i
= 0 ; i
< 1000000 ; i
++) /* may take up to 1 second... */
520 if (CMOS_READ(RTC_FREQ_SELECT
) & RTC_UIP
)
522 for (i
= 0 ; i
< 1000000 ; i
++) /* must try at least 2.228 ms */
523 if (!(CMOS_READ(RTC_FREQ_SELECT
) & RTC_UIP
))
525 do { /* Isn't this overkill ? UIP above should guarantee consistency */
526 sec
= CMOS_READ(RTC_SECONDS
);
527 min
= CMOS_READ(RTC_MINUTES
);
528 hour
= CMOS_READ(RTC_HOURS
);
529 day
= CMOS_READ(RTC_DAY_OF_MONTH
);
530 mon
= CMOS_READ(RTC_MONTH
);
531 year
= CMOS_READ(RTC_YEAR
);
532 } while (sec
!= CMOS_READ(RTC_SECONDS
));
533 if (!(CMOS_READ(RTC_CONTROL
) & RTC_DM_BINARY
) || RTC_ALWAYS_BCD
)
542 if ((year
+= 1900) < 1970)
544 return mktime(year
, mon
, day
, hour
, min
, sec
);
547 static struct irqaction irq0
= { timer_interrupt
, SA_INTERRUPT
, 0, "timer", NULL
, NULL
};
549 /* ------ Calibrate the TSC -------
550 * Return 2^32 * (1 / (TSC clocks per usec)) for do_fast_gettimeoffset().
551 * Too much 64-bit arithmetic here to do this cleanly in C, and for
552 * accuracy's sake we want to keep the overhead on the CTC speaker (channel 2)
553 * output busy loop as low as possible. We avoid reading the CTC registers
554 * directly because of the awkward 8-bit access mechanism of the 82C54
558 #define CALIBRATE_LATCH (5 * LATCH)
559 #define CALIBRATE_TIME (5 * 1000020/HZ)
561 static unsigned long __init
calibrate_tsc(void)
563 /* Set the Gate high, disable speaker */
564 outb((inb(0x61) & ~0x02) | 0x01, 0x61);
567 * Now let's take care of CTC channel 2
569 * Set the Gate high, program CTC channel 2 for mode 0,
570 * (interrupt on terminal count mode), binary count,
571 * load 5 * LATCH count, (LSB and MSB) to begin countdown.
573 outb(0xb0, 0x43); /* binary, mode 0, LSB/MSB, Ch 2 */
574 outb(CALIBRATE_LATCH
& 0xff, 0x42); /* LSB of count */
575 outb(CALIBRATE_LATCH
>> 8, 0x42); /* MSB of count */
578 unsigned long startlow
, starthigh
;
579 unsigned long endlow
, endhigh
;
582 rdtsc(startlow
,starthigh
);
586 } while ((inb(0x61) & 0x20) == 0);
587 rdtsc(endlow
,endhigh
);
589 last_tsc_low
= endlow
;
591 /* Error: ECTCNEVERSET */
595 /* 64-bit subtract - gcc just messes up with long longs */
596 __asm__("subl %2,%0\n\t"
598 :"=a" (endlow
), "=d" (endhigh
)
599 :"g" (startlow
), "g" (starthigh
),
600 "0" (endlow
), "1" (endhigh
));
602 /* Error: ECPUTOOFAST */
606 /* Error: ECPUTOOSLOW */
607 if (endlow
<= CALIBRATE_TIME
)
611 :"=a" (endlow
), "=d" (endhigh
)
612 :"r" (endlow
), "0" (0), "1" (CALIBRATE_TIME
));
618 * The CTC wasn't reliable: we got a hit on the very first read,
619 * or the CPU was so fast/slow that the quotient wouldn't fit in
626 void __init
time_init(void)
628 extern int x86_udelay_tsc
;
630 xtime
.tv_sec
= get_cmos_time();
634 * If we have APM enabled or the CPU clock speed is variable
635 * (CPU stops clock on HLT or slows clock to save power)
636 * then the TSC timestamps may diverge by up to 1 jiffy from
637 * 'real time' but nothing will break.
638 * The most frequent case is that the CPU is "woken" from a halt
639 * state by the timer interrupt itself, so we get 0 error. In the
640 * rare cases where a driver would "wake" the CPU and request a
641 * timestamp, the maximum error is < 1 jiffy. But timestamps are
642 * still perfectly ordered.
643 * Note that the TSC counter will be reset if APM suspends
644 * to disk; this won't break the kernel, though, 'cuz we're
645 * smart. See arch/i386/kernel/apm.c.
648 * Firstly we have to do a CPU check for chips with
649 * a potentially buggy TSC. At this point we haven't run
650 * the ident/bugs checks so we must run this hook as it
651 * may turn off the TSC flag.
653 * NOTE: this doesnt yet handle SMP 486 machines where only
654 * some CPU's have a TSC. Thats never worked and nobody has
655 * moaned if you have the only one in the world - you fix it!
661 unsigned long tsc_quotient
= calibrate_tsc();
663 fast_gettimeoffset_quotient
= tsc_quotient
;
666 * We could be more selective here I suspect
667 * and just enable this for the next intel chips ?
670 #ifndef do_gettimeoffset
671 do_gettimeoffset
= do_fast_gettimeoffset
;
673 do_get_fast_time
= do_gettimeofday
;
675 /* report CPU clock rate in Hz.
676 * The formula is (10^6 * 2^32) / (2^32 * 1 / (clocks/us)) =
677 * clock/second. Our precision is about 100 ppm.
679 { unsigned long eax
=0, edx
=1000000;
681 :"=a" (cpu_hz
), "=d" (edx
)
683 "0" (eax
), "1" (edx
));
684 printk("Detected %ld Hz processor.\n", cpu_hz
);
690 printk("Starting Cobalt Timer system clock\n");
692 /* Set the countdown value */
693 co_cpu_write(CO_CPU_TIMEVAL
, CO_TIME_HZ
/HZ
);
695 /* Start the timer */
696 co_cpu_write(CO_CPU_CTRL
, co_cpu_read(CO_CPU_CTRL
) | CO_CTRL_TIMERUN
);
698 /* Enable (unmask) the timer interrupt */
699 co_cpu_write(CO_CPU_CTRL
, co_cpu_read(CO_CPU_CTRL
) & ~CO_CTRL_TIMEMASK
);
701 /* Wire cpu IDT entry to s/w handler (and Cobalt APIC to IDT) */
702 setup_irq(CO_IRQ_TIMER
, &irq0
);