include/asm-ppc/processor.h

   1 #ifndef __ASM_PPC_PROCESSOR_H
   2 #define __ASM_PPC_PROCESSOR_H
   3
   4 /*
   5  * Default implementation of macro that returns current
   6  * instruction pointer ("program counter").
   7  */
   8 #define current_text_addr() ({ __label__ _l; _l: &&_l;})
   9
  10 #include <linux/config.h>
  11
  12 #include <asm/ptrace.h>
  13 #include <asm/residual.h>
  14
  15 /* Bit encodings for Machine State Register (MSR) */
  16 #ifdef CONFIG_PPC64
  17 #define MSR_SF          (1<<63)
  18 #define MSR_ISF         (1<<61)
  19 #endif /* CONFIG_PPC64 */
  20 #define MSR_POW         (1<<18)         /* Enable Power Management */
  21 #define MSR_TGPR        (1<<17)         /* TLB Update registers in use */
  22 #define MSR_ILE         (1<<16)         /* Interrupt Little-Endian enable */
  23 #define MSR_EE          (1<<15)         /* External Interrupt enable */
  24 #define MSR_PR          (1<<14)         /* Supervisor/User privilege */
  25 #define MSR_FP          (1<<13)         /* Floating Point enable */
  26 #define MSR_ME          (1<<12)         /* Machine Check enable */
  27 #define MSR_FE0         (1<<11)         /* Floating Exception mode 0 */
  28 #define MSR_SE          (1<<10)         /* Single Step */
  29 #define MSR_BE          (1<<9)          /* Branch Trace */
  30 #define MSR_FE1         (1<<8)          /* Floating Exception mode 1 */
  31 #define MSR_IP          (1<<6)          /* Exception prefix 0x000/0xFFF */
  32 #define MSR_IR          (1<<5)          /* Instruction MMU enable */
  33 #define MSR_DR          (1<<4)          /* Data MMU enable */
  34 #define MSR_RI          (1<<1)          /* Recoverable Exception */
  35 #define MSR_LE          (1<<0)          /* Little-Endian enable */
  36
  37 #ifdef CONFIG_APUS
  38 #define MSR_            MSR_ME|MSR_IP|MSR_RI
  39 #else
  40 #define MSR_            MSR_ME|MSR_RI
  41 #endif
  42 #define MSR_KERNEL      MSR_|MSR_IR|MSR_DR
  43 #define MSR_USER        MSR_KERNEL|MSR_PR|MSR_EE
  44
  45 /* Bit encodings for Hardware Implementation Register (HID0)
  46    on PowerPC 603, 604, etc. processors (not 601). */
  47 #define HID0_EMCP       (1<<31)         /* Enable Machine Check pin */
  48 #define HID0_EBA        (1<<29)         /* Enable Bus Address Parity */
  49 #define HID0_EBD        (1<<28)         /* Enable Bus Data Parity */
  50 #define HID0_SBCLK      (1<<27)
  51 #define HID0_EICE       (1<<26)
  52 #define HID0_ECLK       (1<<25)
  53 #define HID0_PAR        (1<<24)
  54 #define HID0_DOZE       (1<<23)
  55 #define HID0_NAP        (1<<22)
  56 #define HID0_SLEEP      (1<<21)
  57 #define HID0_DPM        (1<<20)
  58 #define HID0_ICE        (1<<15)         /* Instruction Cache Enable */
  59 #define HID0_DCE        (1<<14)         /* Data Cache Enable */
  60 #define HID0_ILOCK      (1<<13)         /* Instruction Cache Lock */
  61 #define HID0_DLOCK      (1<<12)         /* Data Cache Lock */
  62 #define HID0_ICFI       (1<<11)         /* Instruction Cache Flash Invalidate */
  63 #define HID0_DCI        (1<<10)         /* Data Cache Invalidate */
  64 #define HID0_SIED       (1<<7)          /* Serial Instruction Execution [Disable] */
  65 #define HID0_BHTE       (1<<2)          /* Branch History Table Enable */
  66 #define HID0_BTCD       (1<<1)          /* Branch target cache disable */
  67
  68 /* fpscr settings */
  69 #define FPSCR_FX        (1<<31)
  70 #define FPSCR_FEX       (1<<30)
  71
  72 #define _MACH_prep     1
  73 #define _MACH_Pmac     2  /* pmac or pmac clone (non-chrp) */
  74 #define _MACH_chrp     4  /* chrp machine */
  75 #define _MACH_mbx      8  /* Motorola MBX board */
  76 #define _MACH_apus    16  /* amiga with phase5 powerup */
  77 #define _MACH_fads    32  /* Motorola FADS board */
  78 #define _MACH_rpxlite 64  /* RPCG RPX-Lite 8xx board */
  79 #define _MACH_bseip   128 /* Bright Star Engineering ip-Engine */
  80 #define _MACH_yk      256 /* Motorola Yellowknife */
  81
  82 /* see residual.h for these */
  83 #define _PREP_Motorola 0x01  /* motorola prep */
  84 #define _PREP_Firm     0x02  /* firmworks prep */
  85 #define _PREP_IBM      0x00  /* ibm prep */
  86 #define _PREP_Bull     0x03  /* bull prep */
  87 #define _PREP_Radstone 0x04  /* Radstone Technology PLC prep */
  88
  89 /*
  90  * Radstone board types
  91  */
  92 #define RS_SYS_TYPE_PPC1   0
  93 #define RS_SYS_TYPE_PPC2   1
  94 #define RS_SYS_TYPE_PPC1a  2
  95 #define RS_SYS_TYPE_PPC2a  3
  96 #define RS_SYS_TYPE_PPC4   4
  97 #define RS_SYS_TYPE_PPC4a  5
  98 #define RS_SYS_TYPE_PPC2ep 6
  99
 100 /* these are arbitrary */
 101 #define _CHRP_Motorola 0x04  /* motorola chrp, the cobra */
 102 #define _CHRP_IBM      0x05  /* IBM chrp, the longtrail and longtrail 2 */
 103
 104 #define _GLOBAL(n)\
 105         .globl n;\
 106 n:
 107
 108 #define TBRU    269     /* Time base Upper/Lower (Reading) */
 109 #define TBRL    268
 110 #define TBWU    284     /* Time base Upper/Lower (Writing) */
 111 #define TBWL    285
 112 #define XER     1
 113 #define LR      8
 114 #define CTR     9
 115 #define HID0    1008    /* Hardware Implementation */
 116 #define PVR     287     /* Processor Version */
 117 #define IBAT0U  528     /* Instruction BAT #0 Upper/Lower */
 118 #define IBAT0L  529
 119 #define IBAT1U  530     /* Instruction BAT #1 Upper/Lower */
 120 #define IBAT1L  531
 121 #define IBAT2U  532     /* Instruction BAT #2 Upper/Lower */
 122 #define IBAT2L  533
 123 #define IBAT3U  534     /* Instruction BAT #3 Upper/Lower */
 124 #define IBAT3L  535
 125 #define DBAT0U  536     /* Data BAT #0 Upper/Lower */
 126 #define DBAT0L  537
 127 #define DBAT1U  538     /* Data BAT #1 Upper/Lower */
 128 #define DBAT1L  539
 129 #define DBAT2U  540     /* Data BAT #2 Upper/Lower */
 130 #define DBAT2L  541
 131 #define DBAT3U  542     /* Data BAT #3 Upper/Lower */
 132 #define DBAT3L  543
 133 #define DMISS   976     /* TLB Lookup/Refresh registers */
 134 #define DCMP    977
 135 #define HASH1   978
 136 #define HASH2   979
 137 #define IMISS   980
 138 #define ICMP    981
 139 #define RPA     982
 140 #define SDR1    25      /* MMU hash base register */
 141 #define DAR     19      /* Data Address Register */
 142 #define SPR0    272     /* Supervisor Private Registers */
 143 #define SPRG0   272
 144 #define SPR1    273
 145 #define SPRG1   273
 146 #define SPR2    274
 147 #define SPRG2   274
 148 #define SPR3    275
 149 #define SPRG3   275
 150 #define DSISR   18
 151 #define SRR0    26      /* Saved Registers (exception) */
 152 #define SRR1    27
 153 #define IABR    1010    /* Instruction Address Breakpoint */
 154 #define DEC     22      /* Decrementer */
 155 #define EAR     282     /* External Address Register */
 156 #define L2CR    1017    /* PPC 750 L2 control register */
 157
 158 #define THRM1   1020
 159 #define THRM2   1021
 160 #define THRM3   1022
 161 #define THRM1_TIN 0x1
 162 #define THRM1_TIV 0x2
 163 #define THRM1_THRES (0x7f<<2)
 164 #define THRM1_TID (1<<29)
 165 #define THRM1_TIE (1<<30)
 166 #define THRM1_V   (1<<31)
 167 #define THRM3_E   (1<<31)
 168
 169 /* Segment Registers */
 170 #define SR0     0
 171 #define SR1     1
 172 #define SR2     2
 173 #define SR3     3
 174 #define SR4     4
 175 #define SR5     5
 176 #define SR6     6
 177 #define SR7     7
 178 #define SR8     8
 179 #define SR9     9
 180 #define SR10    10
 181 #define SR11    11
 182 #define SR12    12
 183 #define SR13    13
 184 #define SR14    14
 185 #define SR15    15
 186
 187 #ifndef __ASSEMBLY__
 188 extern int _machine;
 189
 190 /* Temporary hacks until we can clean things up better - Corey */
 191 extern int have_of;
 192 extern int is_prep;
 193 extern int is_chrp;
 194 extern int is_powerplus;
 195
 196 /* what kind of prep workstation we are */
 197 extern int _prep_type;
 198 /*
 199  * This is used to identify the board type from a given PReP board
 200  * vendor. Board revision is also made available.
 201  */
 202 extern unsigned char ucSystemType;
 203 extern unsigned char ucBoardRev;
 204 extern unsigned char ucBoardRevMaj, ucBoardRevMin;
 205
 206 struct task_struct;
 207 void start_thread(struct pt_regs *regs, unsigned long nip, unsigned long sp);
 208 void release_thread(struct task_struct *);
 209
 210 /*
 211  * Create a new kernel thread.
 212  */
 213 extern long kernel_thread(int (*fn)(void *), void *arg, unsigned long flags);
 214
 215 /*
 216  * Bus types
 217  */
 218 #define EISA_bus 0
 219 #define EISA_bus__is_a_macro /* for versions in ksyms.c */
 220 #define MCA_bus 0
 221 #define MCA_bus__is_a_macro /* for versions in ksyms.c */
 222
 223 /* Lazy FPU handling on uni-processor */
 224 extern struct task_struct *last_task_used_math;
 225
 226 /*
 227  * this is the minimum allowable io space due to the location
 228  * of the io areas on prep (first one at 0x80000000) but
 229  * as soon as I get around to remapping the io areas with the BATs
 230  * to match the mac we can raise this. -- Cort
 231  */
 232 #define TASK_SIZE       (0x80000000UL)
 233
 234 /* This decides where the kernel will search for a free chunk of vm
 235  * space during mmap's.
 236  */
 237 #define TASK_UNMAPPED_BASE      (TASK_SIZE / 8 * 3)
 238
 239 typedef struct {
 240         unsigned long seg;
 241 } mm_segment_t;
 242
 243 struct thread_struct {
 244         unsigned long   ksp;            /* Kernel stack pointer */
 245         unsigned long   *pg_tables;     /* Base of page-table tree */
 246         unsigned long   wchan;          /* Event task is sleeping on */
 247         struct pt_regs  *regs;          /* Pointer to saved register state */
 248         mm_segment_t    fs;             /* for get_fs() validation */
 249         signed long     last_syscall;
 250         double          fpr[32];        /* Complete floating point set */
 251         unsigned long   fpscr_pad;      /* fpr ... fpscr must be contiguous */
 252         unsigned long   fpscr;          /* Floating point status */
 253 };
 254
 255 #define INIT_SP         (sizeof(init_stack) + (unsigned long) &init_stack)
 256
 257 #define INIT_TSS  { \
 258         INIT_SP, /* ksp */ \
 259         (unsigned long *) swapper_pg_dir, /* pg_tables */ \
 260         0, /* wchan */ \
 261         (struct pt_regs *)INIT_SP - 1, /* regs */ \
 262         KERNEL_DS, /*fs*/ \
 263         0, /* last_syscall */ \
 264         {0}, 0, 0 \
 265 }
 266
 267 /*
 268  * Note: the vm_start and vm_end fields here should *not*
 269  * be in kernel space.  (Could vm_end == vm_start perhaps?)
 270  */
 271 #define INIT_MMAP { &init_mm, 0, 0x1000, NULL, \
 272                     PAGE_SHARED, VM_READ | VM_WRITE | VM_EXEC, \
 273                     1, NULL, NULL }
 274
 275 /*
 276  * Return saved PC of a blocked thread. For now, this is the "user" PC
 277  */
 278 static inline unsigned long thread_saved_pc(struct thread_struct *t)
 279 {
 280         return (t->regs) ? t->regs->nip : 0;
 281 }
 282
 283 #define copy_segments(nr, tsk, mm)      do { } while (0)
 284 #define release_segments(mm)            do { } while (0)
 285 #define forget_segments()               do { } while (0)
 286
 287 /*
 288  * NOTE! The task struct and the stack go together
 289  */
 290 #define alloc_task_struct() \
 291         ((struct task_struct *) __get_free_pages(GFP_KERNEL,1))
 292 #define free_task_struct(p)     free_pages((unsigned long)(p),1)
 293
 294 /* in process.c - for early bootup debug -- Cort */
 295 int ll_printk(const char *, ...);
 296 void ll_puts(const char *);
 297
 298 #define init_task       (init_task_union.task)
 299 #define init_stack      (init_task_union.stack)
 300
 301 /* In misc.c */
 302 void _nmask_and_or_msr(unsigned long nmask, unsigned long or_val);
 303
 304 #endif /* ndef ASSEMBLY*/
 305
 306
 307 #endif /* __ASM_PPC_PROCESSOR_H */