include/asm-alpha/core_apecs.h

   1 #ifndef __ALPHA_APECS__H__
   2 #define __ALPHA_APECS__H__
   3
   4 #include <linux/config.h>
   5 #include <linux/types.h>
   6 #include <asm/compiler.h>
   7
   8 /*
   9  * APECS is the internal name for the 2107x chipset which provides
  10  * memory controller and PCI access for the 21064 chip based systems.
  11  *
  12  * This file is based on:
  13  *
  14  * DECchip 21071-AA and DECchip 21072-AA Core Logic Chipsets
  15  * Data Sheet
  16  *
  17  * EC-N0648-72
  18  *
  19  *
  20  * david.rusling@reo.mts.dec.com Initial Version.
  21  *
  22  */
  23
  24 /*
  25    An AVANTI *might* be an XL, and an XL has only 27 bits of ISA address
  26    that get passed through the PCI<->ISA bridge chip. So we've gotta use
  27    both windows to max out the physical memory we can DMA to. Sigh...
  28
  29    If we try a window at 0 for 1GB as a work-around, we run into conflicts
  30    with ISA/PCI bus memory which can't be relocated, like VGA aperture and
  31    BIOS ROMs. So we must put the windows high enough to avoid these areas.
  32
  33    We put window 1 at BUS 64Mb for 64Mb, mapping physical 0 to 64Mb-1,
  34    and window 2 at BUS 1Gb for 1Gb, mapping physical 0 to 1Gb-1.
  35    Yes, this does map 0 to 64Mb-1 twice, but only window 1 will actually
  36    be used for that range (via virt_to_bus()).
  37
  38    Note that we actually fudge the window 1 maximum as 48Mb instead of 64Mb,
  39    to keep virt_to_bus() from returning an address in the first window, for
  40    a data area that goes beyond the 64Mb first DMA window.  Sigh...
  41    The fudge factor MUST match with <asm/dma.h> MAX_DMA_ADDRESS, but
  42    we can't just use that here, because of header file looping... :-(
  43
  44    Window 1 will be used for all DMA from the ISA bus; yes, that does
  45    limit what memory an ISA floppy or sound card or Ethernet can touch, but
  46    it's also a known limitation on other platforms as well. We use the
  47    same technique that is used on INTEL platforms with similar limitation:
  48    set MAX_DMA_ADDRESS and clear some pages' DMAable flags during mem_init().
  49    We trust that any ISA bus device drivers will *always* ask for DMAable
  50    memory explicitly via kmalloc()/get_free_pages() flags arguments.
  51
  52    Note that most PCI bus devices' drivers do *not* explicitly ask for
  53    DMAable memory; they count on being able to DMA to any memory they
  54    get from kmalloc()/get_free_pages(). They will also use window 1 for
  55    any physical memory accesses below 64Mb; the rest will be handled by
  56    window 2, maxing out at 1Gb of memory. I trust this is enough... :-)
  57
  58    We hope that the area before the first window is large enough so that
  59    there will be no overlap at the top end (64Mb). We *must* locate the
  60    PCI cards' memory just below window 1, so that there's still the
  61    possibility of being able to access it via SPARSE space. This is
  62    important for cards such as the Matrox Millennium, whose Xserver
  63    wants to access memory-mapped registers in byte and short lengths.
  64
  65    Note that the XL is treated differently from the AVANTI, even though
  66    for most other things they are identical. It didn't seem reasonable to
  67    make the AVANTI support pay for the limitations of the XL. It is true,
  68    however, that an XL kernel will run on an AVANTI without problems.
  69 */
  70 #define APECS_XL_DMA_WIN1_BASE          (64*1024*1024)
  71 #define APECS_XL_DMA_WIN1_SIZE          (64*1024*1024)
  72 #define APECS_XL_DMA_WIN1_SIZE_PARANOID (48*1024*1024)
  73 #define APECS_XL_DMA_WIN2_BASE          (1024*1024*1024)
  74 #define APECS_XL_DMA_WIN2_SIZE          (1024*1024*1024)
  75
  76
  77 /* These are for normal APECS family machines, AVANTI/MUSTANG/EB64/PC64.  */
  78
  79 #define APECS_DMA_WIN_BASE_DEFAULT      (1024*1024*1024)
  80 #define APECS_DMA_WIN_SIZE_DEFAULT      (1024*1024*1024)
  81
  82 #if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_SRM_SETUP)
  83 #define APECS_DMA_WIN_BASE              alpha_mv.dma_win_base
  84 #define APECS_DMA_WIN_SIZE              alpha_mv.dma_win_size
  85 #else
  86 #define APECS_DMA_WIN_BASE              APECS_DMA_WIN_BASE_DEFAULT
  87 #define APECS_DMA_WIN_SIZE              APECS_DMA_WIN_SIZE_DEFAULT
  88 #endif
  89
  90
  91 /*
  92  * 21071-DA Control and Status registers.
  93  * These are used for PCI memory access.
  94  */
  95 #define APECS_IOC_DCSR                  (IDENT_ADDR + 0x1A0000000UL)
  96 #define APECS_IOC_PEAR                  (IDENT_ADDR + 0x1A0000020UL)
  97 #define APECS_IOC_SEAR                  (IDENT_ADDR + 0x1A0000040UL)
  98 #define APECS_IOC_DR1                   (IDENT_ADDR + 0x1A0000060UL)
  99 #define APECS_IOC_DR2                   (IDENT_ADDR + 0x1A0000080UL)
 100 #define APECS_IOC_DR3                   (IDENT_ADDR + 0x1A00000A0UL)
 101
 102 #define APECS_IOC_TB1R                  (IDENT_ADDR + 0x1A00000C0UL)
 103 #define APECS_IOC_TB2R                  (IDENT_ADDR + 0x1A00000E0UL)
 104
 105 #define APECS_IOC_PB1R                  (IDENT_ADDR + 0x1A0000100UL)
 106 #define APECS_IOC_PB2R                  (IDENT_ADDR + 0x1A0000120UL)
 107
 108 #define APECS_IOC_PM1R                  (IDENT_ADDR + 0x1A0000140UL)
 109 #define APECS_IOC_PM2R                  (IDENT_ADDR + 0x1A0000160UL)
 110
 111 #define APECS_IOC_HAXR0                 (IDENT_ADDR + 0x1A0000180UL)
 112 #define APECS_IOC_HAXR1                 (IDENT_ADDR + 0x1A00001A0UL)
 113 #define APECS_IOC_HAXR2                 (IDENT_ADDR + 0x1A00001C0UL)
 114
 115 #define APECS_IOC_PMLT                  (IDENT_ADDR + 0x1A00001E0UL)
 116
 117 #define APECS_IOC_TLBTAG0               (IDENT_ADDR + 0x1A0000200UL)
 118 #define APECS_IOC_TLBTAG1               (IDENT_ADDR + 0x1A0000220UL)
 119 #define APECS_IOC_TLBTAG2               (IDENT_ADDR + 0x1A0000240UL)
 120 #define APECS_IOC_TLBTAG3               (IDENT_ADDR + 0x1A0000260UL)
 121 #define APECS_IOC_TLBTAG4               (IDENT_ADDR + 0x1A0000280UL)
 122 #define APECS_IOC_TLBTAG5               (IDENT_ADDR + 0x1A00002A0UL)
 123 #define APECS_IOC_TLBTAG6               (IDENT_ADDR + 0x1A00002C0UL)
 124 #define APECS_IOC_TLBTAG7               (IDENT_ADDR + 0x1A00002E0UL)
 125
 126 #define APECS_IOC_TLBDATA0              (IDENT_ADDR + 0x1A0000300UL)
 127 #define APECS_IOC_TLBDATA1              (IDENT_ADDR + 0x1A0000320UL)
 128 #define APECS_IOC_TLBDATA2              (IDENT_ADDR + 0x1A0000340UL)
 129 #define APECS_IOC_TLBDATA3              (IDENT_ADDR + 0x1A0000360UL)
 130 #define APECS_IOC_TLBDATA4              (IDENT_ADDR + 0x1A0000380UL)
 131 #define APECS_IOC_TLBDATA5              (IDENT_ADDR + 0x1A00003A0UL)
 132 #define APECS_IOC_TLBDATA6              (IDENT_ADDR + 0x1A00003C0UL)
 133 #define APECS_IOC_TLBDATA7              (IDENT_ADDR + 0x1A00003E0UL)
 134
 135 #define APECS_IOC_TBIA                  (IDENT_ADDR + 0x1A0000400UL)
 136
 137
 138 /*
 139  * 21071-CA Control and Status registers.
 140  * These are used to program memory timing,
 141  *  configure memory and initialise the B-Cache.
 142  */
 143 #define APECS_MEM_GCR                   (IDENT_ADDR + 0x180000000UL)
 144 #define APECS_MEM_EDSR                  (IDENT_ADDR + 0x180000040UL)
 145 #define APECS_MEM_TAR                   (IDENT_ADDR + 0x180000060UL)
 146 #define APECS_MEM_ELAR                  (IDENT_ADDR + 0x180000080UL)
 147 #define APECS_MEM_EHAR                  (IDENT_ADDR + 0x1800000a0UL)
 148 #define APECS_MEM_SFT_RST               (IDENT_ADDR + 0x1800000c0UL)
 149 #define APECS_MEM_LDxLAR                (IDENT_ADDR + 0x1800000e0UL)
 150 #define APECS_MEM_LDxHAR                (IDENT_ADDR + 0x180000100UL)
 151 #define APECS_MEM_GTR                   (IDENT_ADDR + 0x180000200UL)
 152 #define APECS_MEM_RTR                   (IDENT_ADDR + 0x180000220UL)
 153 #define APECS_MEM_VFPR                  (IDENT_ADDR + 0x180000240UL)
 154 #define APECS_MEM_PDLDR                 (IDENT_ADDR + 0x180000260UL)
 155 #define APECS_MEM_PDhDR                 (IDENT_ADDR + 0x180000280UL)
 156
 157 /* Bank x Base Address Register */
 158 #define APECS_MEM_B0BAR                 (IDENT_ADDR + 0x180000800UL)
 159 #define APECS_MEM_B1BAR                 (IDENT_ADDR + 0x180000820UL)
 160 #define APECS_MEM_B2BAR                 (IDENT_ADDR + 0x180000840UL)
 161 #define APECS_MEM_B3BAR                 (IDENT_ADDR + 0x180000860UL)
 162 #define APECS_MEM_B4BAR                 (IDENT_ADDR + 0x180000880UL)
 163 #define APECS_MEM_B5BAR                 (IDENT_ADDR + 0x1800008A0UL)
 164 #define APECS_MEM_B6BAR                 (IDENT_ADDR + 0x1800008C0UL)
 165 #define APECS_MEM_B7BAR                 (IDENT_ADDR + 0x1800008E0UL)
 166 #define APECS_MEM_B8BAR                 (IDENT_ADDR + 0x180000900UL)
 167
 168 /* Bank x Configuration Register */
 169 #define APECS_MEM_B0BCR                 (IDENT_ADDR + 0x180000A00UL)
 170 #define APECS_MEM_B1BCR                 (IDENT_ADDR + 0x180000A20UL)
 171 #define APECS_MEM_B2BCR                 (IDENT_ADDR + 0x180000A40UL)
 172 #define APECS_MEM_B3BCR                 (IDENT_ADDR + 0x180000A60UL)
 173 #define APECS_MEM_B4BCR                 (IDENT_ADDR + 0x180000A80UL)
 174 #define APECS_MEM_B5BCR                 (IDENT_ADDR + 0x180000AA0UL)
 175 #define APECS_MEM_B6BCR                 (IDENT_ADDR + 0x180000AC0UL)
 176 #define APECS_MEM_B7BCR                 (IDENT_ADDR + 0x180000AE0UL)
 177 #define APECS_MEM_B8BCR                 (IDENT_ADDR + 0x180000B00UL)
 178
 179 /* Bank x Timing Register A */
 180 #define APECS_MEM_B0TRA                 (IDENT_ADDR + 0x180000C00UL)
 181 #define APECS_MEM_B1TRA                 (IDENT_ADDR + 0x180000C20UL)
 182 #define APECS_MEM_B2TRA                 (IDENT_ADDR + 0x180000C40UL)
 183 #define APECS_MEM_B3TRA                 (IDENT_ADDR + 0x180000C60UL)
 184 #define APECS_MEM_B4TRA                 (IDENT_ADDR + 0x180000C80UL)
 185 #define APECS_MEM_B5TRA                 (IDENT_ADDR + 0x180000CA0UL)
 186 #define APECS_MEM_B6TRA                 (IDENT_ADDR + 0x180000CC0UL)
 187 #define APECS_MEM_B7TRA                 (IDENT_ADDR + 0x180000CE0UL)
 188 #define APECS_MEM_B8TRA                 (IDENT_ADDR + 0x180000D00UL)
 189
 190 /* Bank x Timing Register B */
 191 #define APECS_MEM_B0TRB                 (IDENT_ADDR + 0x180000E00UL)
 192 #define APECS_MEM_B1TRB                 (IDENT_ADDR + 0x180000E20UL)
 193 #define APECS_MEM_B2TRB                 (IDENT_ADDR + 0x180000E40UL)
 194 #define APECS_MEM_B3TRB                 (IDENT_ADDR + 0x180000E60UL)
 195 #define APECS_MEM_B4TRB                 (IDENT_ADDR + 0x180000E80UL)
 196 #define APECS_MEM_B5TRB                 (IDENT_ADDR + 0x180000EA0UL)
 197 #define APECS_MEM_B6TRB                 (IDENT_ADDR + 0x180000EC0UL)
 198 #define APECS_MEM_B7TRB                 (IDENT_ADDR + 0x180000EE0UL)
 199 #define APECS_MEM_B8TRB                 (IDENT_ADDR + 0x180000F00UL)
 200
 201
 202 /*
 203  * Memory spaces:
 204  */
 205 #define APECS_IACK_SC                   (IDENT_ADDR + 0x1b0000000UL)
 206 #define APECS_CONF                      (IDENT_ADDR + 0x1e0000000UL)
 207 #define APECS_IO                        (IDENT_ADDR + 0x1c0000000UL)
 208 #define APECS_SPARSE_MEM                (IDENT_ADDR + 0x200000000UL)
 209 #define APECS_DENSE_MEM                 (IDENT_ADDR + 0x300000000UL)
 210
 211
 212 /*
 213  * Bit definitions for I/O Controller status register 0:
 214  */
 215 #define APECS_IOC_STAT0_CMD             0xf
 216 #define APECS_IOC_STAT0_ERR             (1<<4)
 217 #define APECS_IOC_STAT0_LOST            (1<<5)
 218 #define APECS_IOC_STAT0_THIT            (1<<6)
 219 #define APECS_IOC_STAT0_TREF            (1<<7)
 220 #define APECS_IOC_STAT0_CODE_SHIFT      8
 221 #define APECS_IOC_STAT0_CODE_MASK       0x7
 222 #define APECS_IOC_STAT0_P_NBR_SHIFT     13
 223 #define APECS_IOC_STAT0_P_NBR_MASK      0x7ffff
 224
 225 #define APECS_HAE_ADDRESS               APECS_IOC_HAXR1
 226
 227
 228 /*
 229  * Data structure for handling APECS machine checks:
 230  */
 231
 232 struct el_apecs_mikasa_sysdata_mcheck
 233 {
 234         unsigned long coma_gcr;
 235         unsigned long coma_edsr;
 236         unsigned long coma_ter;
 237         unsigned long coma_elar;
 238         unsigned long coma_ehar;
 239         unsigned long coma_ldlr;
 240         unsigned long coma_ldhr;
 241         unsigned long coma_base0;
 242         unsigned long coma_base1;
 243         unsigned long coma_base2;
 244         unsigned long coma_base3;
 245         unsigned long coma_cnfg0;
 246         unsigned long coma_cnfg1;
 247         unsigned long coma_cnfg2;
 248         unsigned long coma_cnfg3;
 249         unsigned long epic_dcsr;
 250         unsigned long epic_pear;
 251         unsigned long epic_sear;
 252         unsigned long epic_tbr1;
 253         unsigned long epic_tbr2;
 254         unsigned long epic_pbr1;
 255         unsigned long epic_pbr2;
 256         unsigned long epic_pmr1;
 257         unsigned long epic_pmr2;
 258         unsigned long epic_harx1;
 259         unsigned long epic_harx2;
 260         unsigned long epic_pmlt;
 261         unsigned long epic_tag0;
 262         unsigned long epic_tag1;
 263         unsigned long epic_tag2;
 264         unsigned long epic_tag3;
 265         unsigned long epic_tag4;
 266         unsigned long epic_tag5;
 267         unsigned long epic_tag6;
 268         unsigned long epic_tag7;
 269         unsigned long epic_data0;
 270         unsigned long epic_data1;
 271         unsigned long epic_data2;
 272         unsigned long epic_data3;
 273         unsigned long epic_data4;
 274         unsigned long epic_data5;
 275         unsigned long epic_data6;
 276         unsigned long epic_data7;
 277
 278         unsigned long pceb_vid;
 279         unsigned long pceb_did;
 280         unsigned long pceb_revision;
 281         unsigned long pceb_command;
 282         unsigned long pceb_status;
 283         unsigned long pceb_latency;
 284         unsigned long pceb_control;
 285         unsigned long pceb_arbcon;
 286         unsigned long pceb_arbpri;
 287
 288         unsigned long esc_id;
 289         unsigned long esc_revision;
 290         unsigned long esc_int0;
 291         unsigned long esc_int1;
 292         unsigned long esc_elcr0;
 293         unsigned long esc_elcr1;
 294         unsigned long esc_last_eisa;
 295         unsigned long esc_nmi_stat;
 296
 297         unsigned long pci_ir;
 298         unsigned long pci_imr;
 299         unsigned long svr_mgr;
 300 };
 301
 302 /* This for the normal APECS machines.  */
 303 struct el_apecs_sysdata_mcheck
 304 {
 305         unsigned long coma_gcr;
 306         unsigned long coma_edsr;
 307         unsigned long coma_ter;
 308         unsigned long coma_elar;
 309         unsigned long coma_ehar;
 310         unsigned long coma_ldlr;
 311         unsigned long coma_ldhr;
 312         unsigned long coma_base0;
 313         unsigned long coma_base1;
 314         unsigned long coma_base2;
 315         unsigned long coma_cnfg0;
 316         unsigned long coma_cnfg1;
 317         unsigned long coma_cnfg2;
 318         unsigned long epic_dcsr;
 319         unsigned long epic_pear;
 320         unsigned long epic_sear;
 321         unsigned long epic_tbr1;
 322         unsigned long epic_tbr2;
 323         unsigned long epic_pbr1;
 324         unsigned long epic_pbr2;
 325         unsigned long epic_pmr1;
 326         unsigned long epic_pmr2;
 327         unsigned long epic_harx1;
 328         unsigned long epic_harx2;
 329         unsigned long epic_pmlt;
 330         unsigned long epic_tag0;
 331         unsigned long epic_tag1;
 332         unsigned long epic_tag2;
 333         unsigned long epic_tag3;
 334         unsigned long epic_tag4;
 335         unsigned long epic_tag5;
 336         unsigned long epic_tag6;
 337         unsigned long epic_tag7;
 338         unsigned long epic_data0;
 339         unsigned long epic_data1;
 340         unsigned long epic_data2;
 341         unsigned long epic_data3;
 342         unsigned long epic_data4;
 343         unsigned long epic_data5;
 344         unsigned long epic_data6;
 345         unsigned long epic_data7;
 346 };
 347
 348 struct el_apecs_procdata
 349 {
 350         unsigned long paltemp[32];  /* PAL TEMP REGS. */
 351         /* EV4-specific fields */
 352         unsigned long exc_addr;     /* Address of excepting instruction. */
 353         unsigned long exc_sum;      /* Summary of arithmetic traps. */
 354         unsigned long exc_mask;     /* Exception mask (from exc_sum). */
 355         unsigned long iccsr;        /* IBox hardware enables. */
 356         unsigned long pal_base;     /* Base address for PALcode. */
 357         unsigned long hier;         /* Hardware Interrupt Enable. */
 358         unsigned long hirr;         /* Hardware Interrupt Request. */
 359         unsigned long csr;          /* D-stream fault info. */
 360         unsigned long dc_stat;      /* D-cache status (ECC/Parity Err). */
 361         unsigned long dc_addr;      /* EV3 Phys Addr for ECC/DPERR. */
 362         unsigned long abox_ctl;     /* ABox Control Register. */
 363         unsigned long biu_stat;     /* BIU Status. */
 364         unsigned long biu_addr;     /* BUI Address. */
 365         unsigned long biu_ctl;      /* BIU Control. */
 366         unsigned long fill_syndrome;/* For correcting ECC errors. */
 367         unsigned long fill_addr;    /* Cache block which was being read */
 368         unsigned long va;           /* Effective VA of fault or miss. */
 369         unsigned long bc_tag;       /* Backup Cache Tag Probe Results.*/
 370 };
 371
 372
 373 #ifdef __KERNEL__
 374
 375 #ifndef __EXTERN_INLINE
 376 #define __EXTERN_INLINE extern inline
 377 #define __IO_EXTERN_INLINE
 378 #endif
 379
 380 /*
 381  * Translate physical memory address as seen on (PCI) bus into
 382  * a kernel virtual address and vv.
 383  */
 384
 385 /*
 386  * NOTE: we fudge the window 1 maximum as 48Mb instead of 64Mb, to prevent
 387  * virt_to_bus() from returning an address in the first window, for a
 388  * data area that goes beyond the 64Mb first DMA window. Sigh...
 389  * This MUST match with <asm/dma.h> MAX_DMA_ADDRESS for consistency, but
 390  * we can't just use that here, because of header file looping... :-(
 391  */
 392
 393 __EXTERN_INLINE unsigned long apecs_virt_to_bus(void * address)
 394 {
 395         unsigned long paddr = virt_to_phys(address);
 396         return paddr + APECS_DMA_WIN_BASE;
 397 }
 398
 399 static inline unsigned long apecs_xl_virt_to_bus(void * address)
 400 {
 401         unsigned long paddr = virt_to_phys(address);
 402         if (paddr < APECS_XL_DMA_WIN1_SIZE_PARANOID)
 403           return paddr + APECS_XL_DMA_WIN1_BASE;
 404         else
 405           return paddr + APECS_XL_DMA_WIN2_BASE; /* win 2 xlates to 0 also */
 406 }
 407
 408 __EXTERN_INLINE void * apecs_bus_to_virt(unsigned long address)
 409 {
 410         /*
 411          * This check is a sanity check but also ensures that bus
 412          * address 0 maps to virtual address 0 which is useful to
 413          * detect null "pointers" (the NCR driver is much simpler if
 414          * NULL pointers are preserved).
 415          */
 416         if (address < APECS_DMA_WIN_BASE)
 417                 return 0;
 418         return phys_to_virt(address - APECS_DMA_WIN_BASE);
 419 }
 420
 421 static inline void * apecs_xl_bus_to_virt(unsigned long address)
 422 {
 423         /*
 424          * This check is a sanity check but also ensures that bus
 425          * address 0 maps to virtual address 0 which is useful to
 426          * detect null "pointers" (the NCR driver is much simpler if
 427          * NULL pointers are preserved).
 428          */
 429         if (address < APECS_XL_DMA_WIN1_BASE)
 430                 return 0;
 431         else if (address < (APECS_XL_DMA_WIN1_BASE + APECS_XL_DMA_WIN1_SIZE))
 432                 address -= APECS_XL_DMA_WIN1_BASE;
 433         else /* should be more checking here, maybe? */
 434                 address -= APECS_XL_DMA_WIN2_BASE;
 435         return phys_to_virt(address);
 436 }
 437
 438 /*
 439  * I/O functions:
 440  *
 441  * Unlike Jensen, the APECS machines have no concept of local
 442  * I/O---everything goes over the PCI bus.
 443  *
 444  * There is plenty room for optimization here.  In particular,
 445  * the Alpha's insb/insw/extb/extw should be useful in moving
 446  * data to/from the right byte-lanes.
 447  */
 448
 449 #define vip     volatile int *
 450 #define vuip    volatile unsigned int *
 451 #define vulp    volatile unsigned long *
 452
 453 __EXTERN_INLINE unsigned int apecs_inb(unsigned long addr)
 454 {
 455         long result = *(vip) ((addr << 5) + APECS_IO + 0x00);
 456         return __kernel_extbl(result, addr & 3);
 457 }
 458
 459 __EXTERN_INLINE void apecs_outb(unsigned char b, unsigned long addr)
 460 {
 461         unsigned long w;
 462
 463         w = __kernel_insbl(b, addr & 3);
 464         *(vuip) ((addr << 5) + APECS_IO + 0x00) = w;
 465         mb();
 466 }
 467
 468 __EXTERN_INLINE unsigned int apecs_inw(unsigned long addr)
 469 {
 470         long result = *(vip) ((addr << 5) + APECS_IO + 0x08);
 471         return __kernel_extwl(result, addr & 3);
 472 }
 473
 474 __EXTERN_INLINE void apecs_outw(unsigned short b, unsigned long addr)
 475 {
 476         unsigned long w;
 477
 478         w = __kernel_inswl(b, addr & 3);
 479         *(vuip) ((addr << 5) + APECS_IO + 0x08) = w;
 480         mb();
 481 }
 482
 483 __EXTERN_INLINE unsigned int apecs_inl(unsigned long addr)
 484 {
 485         return *(vuip) ((addr << 5) + APECS_IO + 0x18);
 486 }
 487
 488 __EXTERN_INLINE void apecs_outl(unsigned int b, unsigned long addr)
 489 {
 490         *(vuip) ((addr << 5) + APECS_IO + 0x18) = b;
 491         mb();
 492 }
 493
 494
 495 /*
 496  * Memory functions.  64-bit and 32-bit accesses are done through
 497  * dense memory space, everything else through sparse space.
 498  */
 499
 500 __EXTERN_INLINE unsigned long apecs_readb(unsigned long addr)
 501 {
 502         unsigned long result, msb;
 503
 504         if (addr >= (1UL << 24)) {
 505                 msb = addr & 0xf8000000;
 506                 addr -= msb;
 507                 set_hae(msb);
 508         }
 509         result = *(vip) ((addr << 5) + APECS_SPARSE_MEM + 0x00);
 510         return __kernel_extbl(result, addr & 3);
 511 }
 512
 513 __EXTERN_INLINE unsigned long apecs_readw(unsigned long addr)
 514 {
 515         unsigned long result, msb;
 516
 517         if (addr >= (1UL << 24)) {
 518                 msb = addr & 0xf8000000;
 519                 addr -= msb;
 520                 set_hae(msb);
 521         }
 522         result = *(vip) ((addr << 5) + APECS_SPARSE_MEM + 0x08);
 523         return __kernel_extwl(result, addr & 3);
 524 }
 525
 526 __EXTERN_INLINE unsigned long apecs_readl(unsigned long addr)
 527 {
 528         return *(vuip) (addr + APECS_DENSE_MEM);
 529 }
 530
 531 __EXTERN_INLINE unsigned long apecs_readq(unsigned long addr)
 532 {
 533         return *(vulp) (addr + APECS_DENSE_MEM);
 534 }
 535
 536 __EXTERN_INLINE void apecs_writeb(unsigned char b, unsigned long addr)
 537 {
 538         unsigned long msb;
 539
 540         if (addr >= (1UL << 24)) {
 541                 msb = addr & 0xf8000000;
 542                 addr -= msb;
 543                 set_hae(msb);
 544         }
 545         *(vuip) ((addr << 5) + APECS_SPARSE_MEM + 0x00) = b * 0x01010101;
 546 }
 547
 548 __EXTERN_INLINE void apecs_writew(unsigned short b, unsigned long addr)
 549 {
 550         unsigned long msb;
 551
 552         if (addr >= (1UL << 24)) {
 553                 msb = addr & 0xf8000000;
 554                 addr -= msb;
 555                 set_hae(msb);
 556         }
 557         *(vuip) ((addr << 5) + APECS_SPARSE_MEM + 0x08) = b * 0x00010001;
 558 }
 559
 560 __EXTERN_INLINE void apecs_writel(unsigned int b, unsigned long addr)
 561 {
 562         *(vuip) (addr + APECS_DENSE_MEM) = b;
 563 }
 564
 565 __EXTERN_INLINE void apecs_writeq(unsigned long b, unsigned long addr)
 566 {
 567         *(vulp) (addr + APECS_DENSE_MEM) = b;
 568 }
 569
 570 /* Find the DENSE memory area for a given bus address.  */
 571
 572 __EXTERN_INLINE unsigned long apecs_dense_mem(unsigned long addr)
 573 {
 574         return APECS_DENSE_MEM;
 575 }
 576
 577 #undef vip
 578 #undef vuip
 579 #undef vulp
 580
 581 #ifdef __WANT_IO_DEF
 582
 583 #ifdef CONFIG_ALPHA_XL
 584 #define virt_to_bus     apecs_xl_virt_to_bus
 585 #define bus_to_virt     apecs_xl_bus_to_virt
 586 #else
 587 #define virt_to_bus     apecs_virt_to_bus
 588 #define bus_to_virt     apecs_bus_to_virt
 589 #endif
 590
 591 #define __inb           apecs_inb
 592 #define __inw           apecs_inw
 593 #define __inl           apecs_inl
 594 #define __outb          apecs_outb
 595 #define __outw          apecs_outw
 596 #define __outl          apecs_outl
 597 #define __readb         apecs_readb
 598 #define __readw         apecs_readw
 599 #define __readl         apecs_readl
 600 #define __readq         apecs_readq
 601 #define __writeb        apecs_writeb
 602 #define __writew        apecs_writew
 603 #define __writel        apecs_writel
 604 #define __writeq        apecs_writeq
 605 #define dense_mem       apecs_dense_mem
 606
 607 #define inb(port) \
 608 (__builtin_constant_p((port))?__inb(port):_inb(port))
 609
 610 #define outb(x, port) \
 611 (__builtin_constant_p((port))?__outb((x),(port)):_outb((x),(port)))
 612
 613 #define readl(a)        __readl((unsigned long)(a))
 614 #define readq(a)        __readq((unsigned long)(a))
 615 #define writel(v,a)     __writel((v),(unsigned long)(a))
 616 #define writeq(v,a)     __writeq((v),(unsigned long)(a))
 617
 618 #endif /* __WANT_IO_DEF */
 619
 620 #ifdef __IO_EXTERN_INLINE
 621 #undef __EXTERN_INLINE
 622 #undef __IO_EXTERN_INLINE
 623 #endif
 624
 625 #endif /* __KERNEL__ */
 626
 627 #endif /* __ALPHA_APECS__H__ */