drivers/scsi/fastlane.c

   1 /* fastlane.c: Driver for Phase5's Fastlane SCSI Controller.
   2  *
   3  * Copyright (C) 1996 Jesper Skov (jskov@cygnus.co.uk)
   4  *
   5  * This driver is based on the CyberStorm driver, hence the occasional
   6  * reference to CyberStorm.
   7  *
   8  * Betatesting & crucial adjustments by
   9  *        Patrik Rak (prak3264@ss1000.ms.mff.cuni.cz)
  10  *
  11  */
  12
  13 /* TODO:
  14  *
  15  * o According to the doc from laire, it is required to reset the DMA when
  16  *   the transfer is done. ATM we reset DMA just before every new
  17  *   dma_init_(read|write).
  18  *
  19  * 1) Figure out how to make a cleaner merge with the sparc driver with regard
  20  *    to the caches and the Sparc MMU mapping.
  21  * 2) Make as few routines required outside the generic driver. A lot of the
  22  *    routines in this file used to be inline!
  23  */
  24
  25 #include <linux/module.h>
  26
  27 #include <linux/init.h>
  28 #include <linux/kernel.h>
  29 #include <linux/delay.h>
  30 #include <linux/types.h>
  31 #include <linux/string.h>
  32 #include <linux/malloc.h>
  33 #include <linux/blk.h>
  34 #include <linux/proc_fs.h>
  35 #include <linux/stat.h>
  36
  37 #include "scsi.h"
  38 #include "hosts.h"
  39 #include "NCR53C9x.h"
  40 #include "fastlane.h"
  41
  42 #include <linux/zorro.h>
  43 #include <asm/irq.h>
  44 #include <asm/io.h>
  45 #include <asm/amigaints.h>
  46 #include <asm/amigahw.h>
  47
  48 #include <asm/pgtable.h>
  49
  50 /* Such day has just come... */
  51 #if 0
  52 /* Let this defined unless you really need to enable DMA IRQ one day */
  53 #define NODMAIRQ
  54 #endif
  55
  56 static int  dma_bytes_sent(struct NCR_ESP *esp, int fifo_count);
  57 static int  dma_can_transfer(struct NCR_ESP *esp, Scsi_Cmnd *sp);
  58 static inline void dma_clear(struct NCR_ESP *esp);
  59 static void dma_dump_state(struct NCR_ESP *esp);
  60 static void dma_init_read(struct NCR_ESP *esp, __u32 addr, int length);
  61 static void dma_init_write(struct NCR_ESP *esp, __u32 vaddr, int length);
  62 static void dma_ints_off(struct NCR_ESP *esp);
  63 static void dma_ints_on(struct NCR_ESP *esp);
  64 static int  dma_irq_p(struct NCR_ESP *esp);
  65 static void dma_irq_exit(struct NCR_ESP *esp);
  66 static void dma_led_off(struct NCR_ESP *esp);
  67 static void dma_led_on(struct NCR_ESP *esp);
  68 static int  dma_ports_p(struct NCR_ESP *esp);
  69 static void dma_setup(struct NCR_ESP *esp, __u32 addr, int count, int write);
  70
  71 static unsigned char ctrl_data = 0;     /* Keep backup of the stuff written
  72                                  * to ctrl_reg. Always write a copy
  73                                  * to this register when writing to
  74                                  * the hardware register!
  75                                  */
  76
  77 volatile unsigned char cmd_buffer[16];
  78                                 /* This is where all commands are put
  79                                  * before they are transfered to the ESP chip
  80                                  * via PIO.
  81                                  */
  82
  83 /***************************************************************** Detection */
  84 int __init fastlane_esp_detect(Scsi_Host_Template *tpnt)
  85 {
  86         struct NCR_ESP *esp;
  87         struct zorro_dev *z = NULL;
  88         unsigned long address;
  89
  90         if ((z = zorro_find_device(ZORRO_PROD_PHASE5_BLIZZARD_1230_II_FASTLANE_Z3_CYBERSCSI_CYBERSTORM060, z))) {
  91             unsigned long board = z->resource.start;
  92             if (request_mem_region(board+FASTLANE_ESP_ADDR,
  93                                    sizeof(struct ESP_regs), "NCR53C9x")) {
  94                 /* Check if this is really a fastlane controller. The problem
  95                  * is that also the cyberstorm and blizzard controllers use
  96                  * this ID value. Fortunately only Fastlane maps in Z3 space
  97                  */
  98                 if (board < 0x1000000) {
  99                         release_mem_region(board+FASTLANE_ESP_ADDR,
 100                                            sizeof(struct ESP_regs));
 101                         return 0;
 102                 }
 103                 strcpy(z->name, "Fastlane Z3 SCSI Host Adapter");
 104
 105                 esp = esp_allocate(tpnt, (void *)board+FASTLANE_ESP_ADDR);
 106
 107                 /* Do command transfer with programmed I/O */
 108                 esp->do_pio_cmds = 1;
 109
 110                 /* Required functions */
 111                 esp->dma_bytes_sent = &dma_bytes_sent;
 112                 esp->dma_can_transfer = &dma_can_transfer;
 113                 esp->dma_dump_state = &dma_dump_state;
 114                 esp->dma_init_read = &dma_init_read;
 115                 esp->dma_init_write = &dma_init_write;
 116                 esp->dma_ints_off = &dma_ints_off;
 117                 esp->dma_ints_on = &dma_ints_on;
 118                 esp->dma_irq_p = &dma_irq_p;
 119                 esp->dma_ports_p = &dma_ports_p;
 120                 esp->dma_setup = &dma_setup;
 121
 122                 /* Optional functions */
 123                 esp->dma_barrier = 0;
 124                 esp->dma_drain = 0;
 125                 esp->dma_invalidate = 0;
 126                 esp->dma_irq_entry = 0;
 127                 esp->dma_irq_exit = &dma_irq_exit;
 128                 esp->dma_led_on = &dma_led_on;
 129                 esp->dma_led_off = &dma_led_off;
 130                 esp->dma_poll = 0;
 131                 esp->dma_reset = 0;
 132
 133                 /* Initialize the portBits (enable IRQs) */
 134                 ctrl_data = (FASTLANE_DMA_FCODE |
 135 #ifndef NODMAIRQ
 136                              FASTLANE_DMA_EDI |
 137 #endif
 138                              FASTLANE_DMA_ESI);
 139
 140
 141                 /* SCSI chip clock */
 142                 esp->cfreq = 40000000;
 143
 144
 145                 /* Map the physical address space into virtual kernel space */
 146                 address = (unsigned long)
 147                         ioremap_nocache(board, z->resource.end-board+1);
 148
 149                 if(!address){
 150                         printk("Could not remap Fastlane controller memory!");
 151                         scsi_unregister (esp->ehost);
 152                         release_mem_region(board+FASTLANE_ESP_ADDR,
 153                                            sizeof(struct ESP_regs));
 154                         return 0;
 155                 }
 156
 157
 158                 /* The DMA registers on the Fastlane are mapped
 159                  * relative to the device (i.e. in the same Zorro
 160                  * I/O block).
 161                  */
 162                 esp->dregs = (void *)(address + FASTLANE_DMA_ADDR);
 163
 164                 /* ESP register base */
 165                 esp->eregs = (struct ESP_regs *)(address + FASTLANE_ESP_ADDR);
 166
 167                 /* Board base */
 168                 esp->edev = (void *) address;
 169
 170                 /* Set the command buffer */
 171                 esp->esp_command = (volatile unsigned char*) cmd_buffer;
 172                 esp->esp_command_dvma = virt_to_bus(cmd_buffer);
 173
 174                 esp->irq = IRQ_AMIGA_PORTS;
 175                 esp->slot = board+FASTLANE_ESP_ADDR;
 176                 request_irq(IRQ_AMIGA_PORTS, esp_intr, SA_SHIRQ,
 177                             "Fastlane SCSI", esp_intr);
 178
 179                 /* Controller ID */
 180                 esp->scsi_id = 7;
 181
 182                 /* We don't have a differential SCSI-bus. */
 183                 esp->diff = 0;
 184
 185                 dma_clear(esp);
 186                 esp_initialize(esp);
 187
 188                 printk("ESP: Total of %d ESP hosts found, %d actually in use.\n", nesps, esps_in_use);
 189                 esps_running = esps_in_use;
 190                 return esps_in_use;
 191             }
 192         }
 193         return 0;
 194 }
 195
 196
 197 /************************************************************* DMA Functions */
 198 static int dma_bytes_sent(struct NCR_ESP *esp, int fifo_count)
 199 {
 200         /* Since the Fastlane DMA is fully dedicated to the ESP chip,
 201          * the number of bytes sent (to the ESP chip) equals the number
 202          * of bytes in the FIFO - there is no buffering in the DMA controller.
 203          * XXXX Do I read this right? It is from host to ESP, right?
 204          */
 205         return fifo_count;
 206 }
 207
 208 static int dma_can_transfer(struct NCR_ESP *esp, Scsi_Cmnd *sp)
 209 {
 210         unsigned long sz = sp->SCp.this_residual;
 211         if(sz > 0xfffc)
 212                 sz = 0xfffc;
 213         return sz;
 214 }
 215
 216 static void dma_dump_state(struct NCR_ESP *esp)
 217 {
 218         ESPLOG(("esp%d: dma -- cond_reg<%02x>\n",
 219                 esp->esp_id, ((struct fastlane_dma_registers *)
 220                               (esp->dregs))->cond_reg));
 221         ESPLOG(("intreq:<%04x>, intena:<%04x>\n",
 222                 custom.intreqr, custom.intenar));
 223 }
 224
 225 static void dma_init_read(struct NCR_ESP *esp, __u32 addr, int length)
 226 {
 227         struct fastlane_dma_registers *dregs =
 228                 (struct fastlane_dma_registers *) (esp->dregs);
 229         unsigned long *t;
 230
 231         cache_clear(addr, length);
 232
 233         dma_clear(esp);
 234
 235         t = (unsigned long *)((addr & 0x00ffffff) + esp->edev);
 236
 237         dregs->clear_strobe = 0;
 238         *t = addr;
 239
 240         ctrl_data = (ctrl_data & FASTLANE_DMA_MASK) | FASTLANE_DMA_ENABLE;
 241         dregs->ctrl_reg = ctrl_data;
 242 }
 243
 244 static void dma_init_write(struct NCR_ESP *esp, __u32 addr, int length)
 245 {
 246         struct fastlane_dma_registers *dregs =
 247                 (struct fastlane_dma_registers *) (esp->dregs);
 248         unsigned long *t;
 249
 250         cache_push(addr, length);
 251
 252         dma_clear(esp);
 253
 254         t = (unsigned long *)((addr & 0x00ffffff) + (esp->edev));
 255
 256         dregs->clear_strobe = 0;
 257         *t = addr;
 258
 259         ctrl_data = ((ctrl_data & FASTLANE_DMA_MASK) |
 260                      FASTLANE_DMA_ENABLE |
 261                      FASTLANE_DMA_WRITE);
 262         dregs->ctrl_reg = ctrl_data;
 263 }
 264
 265 static inline void dma_clear(struct NCR_ESP *esp)
 266 {
 267         struct fastlane_dma_registers *dregs =
 268                 (struct fastlane_dma_registers *) (esp->dregs);
 269         unsigned long *t;
 270
 271         ctrl_data = (ctrl_data & FASTLANE_DMA_MASK);
 272         dregs->ctrl_reg = ctrl_data;
 273
 274         t = (unsigned long *)(esp->edev);
 275
 276         dregs->clear_strobe = 0;
 277         *t = 0 ;
 278 }
 279
 280
 281 static void dma_ints_off(struct NCR_ESP *esp)
 282 {
 283         disable_irq(esp->irq);
 284 }
 285
 286 static void dma_ints_on(struct NCR_ESP *esp)
 287 {
 288         enable_irq(esp->irq);
 289 }
 290
 291 static void dma_irq_exit(struct NCR_ESP *esp)
 292 {
 293         struct fastlane_dma_registers *dregs =
 294                 (struct fastlane_dma_registers *) (esp->dregs);
 295
 296         dregs->ctrl_reg = ctrl_data & ~(FASTLANE_DMA_EDI|FASTLANE_DMA_ESI);
 297 #ifdef __mc68000__
 298         nop();
 299 #endif
 300         dregs->ctrl_reg = ctrl_data;
 301 }
 302
 303 static int dma_irq_p(struct NCR_ESP *esp)
 304 {
 305         struct fastlane_dma_registers *dregs =
 306                 (struct fastlane_dma_registers *) (esp->dregs);
 307         unsigned char dma_status;
 308
 309         dma_status = dregs->cond_reg;
 310
 311         if(dma_status & FASTLANE_DMA_IACT)
 312                 return 0;       /* not our IRQ */
 313
 314         /* Return non-zero if ESP requested IRQ */
 315         return (
 316 #ifndef NODMAIRQ
 317            (dma_status & FASTLANE_DMA_CREQ) &&
 318 #endif
 319            (!(dma_status & FASTLANE_DMA_MINT)) &&
 320            (esp_read(((struct ESP_regs *) (esp->eregs))->esp_status) & ESP_STAT_INTR));
 321 }
 322
 323 static void dma_led_off(struct NCR_ESP *esp)
 324 {
 325         ctrl_data &= ~FASTLANE_DMA_LED;
 326         ((struct fastlane_dma_registers *)(esp->dregs))->ctrl_reg = ctrl_data;
 327 }
 328
 329 static void dma_led_on(struct NCR_ESP *esp)
 330 {
 331         ctrl_data |= FASTLANE_DMA_LED;
 332         ((struct fastlane_dma_registers *)(esp->dregs))->ctrl_reg = ctrl_data;
 333 }
 334
 335 static int dma_ports_p(struct NCR_ESP *esp)
 336 {
 337         return ((custom.intenar) & IF_PORTS);
 338 }
 339
 340 static void dma_setup(struct NCR_ESP *esp, __u32 addr, int count, int write)
 341 {
 342         /* On the Sparc, DMA_ST_WRITE means "move data from device to memory"
 343          * so when (write) is true, it actually means READ!
 344          */
 345         if(write){
 346                 dma_init_read(esp, addr, count);
 347         } else {
 348                 dma_init_write(esp, addr, count);
 349         }
 350 }
 351
 352 #ifdef MODULE
 353
 354 #define HOSTS_C
 355
 356 #include "fastlane.h"
 357
 358 Scsi_Host_Template driver_template = SCSI_FASTLANE;
 359
 360 #include "scsi_module.c"
 361
 362 #endif
 363
 364 int fastlane_esp_release(struct Scsi_Host *instance)
 365 {
 366 #ifdef MODULE
 367         unsigned long address = (unsigned long)((struct NCR_ESP *)instance->hostdata)->edev;
 368         esp_deallocate((struct NCR_ESP *)instance->hostdata);
 369         esp_release();
 370         release_mem_region(address, sizeof(struct ESP_regs));
 371         free_irq(IRQ_AMIGA_PORTS, esp_intr);
 372 #endif
 373         return 1;
 374 }