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Import 2.3.16
[davej-history.git] / drivers / sound / maestro.c
blob7f9ca3df7df8486ccd46070c10410d13493fa413
1 /*****************************************************************************
2 *
3 * ESS Maestro/Maestro-2/Maestro-2E driver for Linux 2.2.x
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
18 *
19 * (c) Copyright 1999 Alan Cox <alan.cox@linux.org>
20 *
21 * Based heavily on SonicVibes.c:
22 * Copyright (C) 1998-1999 Thomas Sailer (sailer@ife.ee.ethz.ch)
23 *
24 * Heavily modified by Zach Brown <zab@redhat.com> based on lunch
25 * with ESS engineers. Many thanks to Howard Kim for providing
26 * contacts and hardware. Honorable mention goes to Eric
27 * Brombaugh for the BOB routines and nice hacking in general.
28 *
29 * Supported devices:
30 * /dev/dsp0-7 standard /dev/dsp device, (mostly) OSS compatible
31 * /dev/mixer standard /dev/mixer device, (mostly) OSS compatible
32 *
33 * Hardware Description
34 *
35 * A working Maestro setup contains the Maestro chip wired to a
36 * codec or 2. In the Maestro we have the APUs, the ASP, and the
37 * Wavecache. The APUs can be though of as virtual audio routing
38 * channels. They can take data from a number of sources and perform
39 * basic encodings of the data. The wavecache is a storehouse for
40 * PCM data. Typically it deals with PCI and interracts with the
41 * APUs. The ASP is a wacky DSP like device that ESS is loathe
42 * to release docs on. Thankfully it isn't required on the Maestro
43 * until you start doing insane things like FM emulation and surround
44 * encoding. The codecs are almost always AC-97 compliant codecs,
45 * but it appears that early Maestros may have had PT101 (an ESS
46 * part?) wired to them. The only real difference in the Maestro
47 * families is external goop like docking capability, memory for
48 * the ASP, and trivial initialization differences.
49 *
50 * Driver Operation
51 *
52 * We only drive the APU/Wavecache as typical DACs and drive the
53 * mixers in the codecs. There are 64 APUs. We assign 4 to each
54 * /dev/dsp? device. 2 channels for both in and out.
55 *
56 * For output we maintain a ring buffer of data that we are dmaing
57 * to the card. In mono operation this is nice and easy. When
58 * we receive data we tack it onto the ring buffer and make sure
59 * the APU assigned to it is playing over the data. When we fill
60 * the ring buffer we put the client to sleep until there is
61 * room again. Easy.
62 *
63 * However, this starts to stink when we use stereo. The APUs
64 * supposedly can decode LRLR packed stereo data, but it
65 * doesn't work. So we're forced to use dual mono APUs walking over
66 * mono encoded data. This requires us to split the input from
67 * the client and complicates the buffer maths tremendously. Ick.
68 *
69 * Once input is actually written, it will be worth pointing out
70 * that only 44/16 input actually works.
71 *
72 * TODO
73 * Leaks memory?
74 * recording is horribly broken
75 * apus or dmas get out sync
76 * bob can be started twice
77 * anyone have a pt101 codec?
78 * ess's ac97 codec (es1921) doesn't work
79 * generally test across codecs..
80 * mmap(), but beware stereo encoding nastiness.
81 */
82
83 /*****************************************************************************/
84
85
86 #ifdef MODULE
87 #include <linux/module.h>
88 #ifdef MODVERSIONS
89 #include <linux/modversions.h>
90 #endif
91 #endif
92
93 #include <linux/version.h>
94 #include <linux/string.h>
95 #include <linux/ctype.h>
96 #include <linux/ioport.h>
97 #include <linux/sched.h>
98 #include <linux/delay.h>
99 #include <linux/sound.h>
100 #include <linux/malloc.h>
101 #include <linux/soundcard.h>
102 #include <linux/pci.h>
103 #include <asm/io.h>
104 #include <asm/dma.h>
105 #include <linux/init.h>
106 #include <linux/poll.h>
107 #include <asm/spinlock.h>
108 #include <asm/uaccess.h>
109 #include <asm/hardirq.h>
110
111 #include "maestro.h"
112 #include "maestro_tables.h"
113
114 /* --------------------------------------------------------------------- */
115
116 #define M_DEBUG 1
117
118 #ifdef M_DEBUG
119 static int debug=0;
120 #define M_printk(args...) {if (debug) printk(args);}
121 #else
122 #define M_printk(x)
123 #endif
124
125 /* --------------------------------------------------------------------- */
126
127 #define DRIVER_VERSION "0.03"
128
129 #ifndef PCI_VENDOR_ESS
130 #define PCI_VENDOR_ESS 0x125D
131 #define PCI_DEVICE_ID_ESS_ESS1968 0x1968 /* Maestro 2 */
132 #define PCI_DEVICE_ID_ESS_ESS1978 0x1978 /* Maestro 2E */
133
134 #define PCI_VENDOR_ESS_OLD 0x1285 /* vendor id for maestro 1 */
135 #define PCI_DEVICE_ID_ESS_ESS0100 0x0100 /* maestro 1 */
136 #endif /* PCI_VENDOR_ESS */
137
138 #define ESS_CHAN_HARD 0x100
139
140 #define ESS_CFMT_STEREO 0x01
141 #define ESS_CFMT_16BIT 0x02
142 #define ESS_CFMT_MASK 0x03
143 #define ESS_CFMT_ASHIFT 0
144 #define ESS_CFMT_CSHIFT 4
145
146 #define ESS_ENABLE_PE 1
147 #define ESS_ENABLE_RE 2
148
149 #define ESS_STATE_MAGIC 0x125D1968
150 #define ESS_CARD_MAGIC 0x19283746
151
152 #define DAC_RUNNING 1
153 #define ADC_RUNNING 2
154
155 static const unsigned sample_size[] = { 1, 2, 2, 4 };
156 static const unsigned sample_shift[] = { 0, 1, 1, 2 };
157
158 enum card_types_t {
159 TYPE_MAESTRO,
160 TYPE_MAESTRO2,
161 TYPE_MAESTRO2E
162 };
163
164 static const char *card_names[]={
165 [TYPE_MAESTRO] = "ESS Maestro",
166 [TYPE_MAESTRO2] = "ESS Maestro 2",
167 [TYPE_MAESTRO2E] = "ESS Maestro 2E"
168 };
169
170 #define SND_DEV_DSP16 5
171
172 /* --------------------------------------------------------------------- */
173
174 struct ess_state {
175 unsigned int magic;
176 /* FIXME: we probably want submixers in here, but only one record pair */
177 u8 apu[4]; /* Left, Right, Left In, Right In */
178 u8 apu_mode[4]; /* Running mode for this APU */
179 u8 apu_pan[4]; /* Panning setup for this APU */
180 struct ess_card *card; /* Card info */
181 /* wave stuff */
182 unsigned int rateadc, ratedac;
183 unsigned char fmt, enable;
184
185 spinlock_t lock;
186 struct semaphore open_sem;
187 mode_t open_mode;
188 wait_queue_head_t open_wait;
189
190 /* soundcore stuff */
191 int dev_audio;
192
193 struct dmabuf {
194 void *rawbuf;
195 unsigned buforder;
196 unsigned numfrag;
197 unsigned fragshift;
198 unsigned hwptr, swptr;
199 unsigned total_bytes;
200 int count;
201 unsigned error; /* over/underrun */
202 wait_queue_head_t wait;
203 /* redundant, but makes calculations easier */
204 unsigned fragsize;
205 unsigned dmasize;
206 unsigned fragsamples;
207 /* OSS stuff */
208 unsigned mapped:1;
209 unsigned ready:1;
210 unsigned endcleared:1;
211 unsigned ossfragshift;
212 int ossmaxfrags;
213 unsigned subdivision;
214 u16 base; /* Offset for ptr */
215 } dma_dac, dma_adc;
216 };
217
218 struct ess_card {
219 unsigned int magic;
220
221 /* We keep maestro cards in a linked list */
222 struct ess_card *next;
223
224 int dev_mixer;
225
226 int card_type;
227
228 /* as most of this is static,
229 perhaps it should be a pointer to a global struct */
230 struct mixer_goo {
231 int modcnt;
232 int supported_mixers;
233 int stereo_mixers;
234 int record_sources;
235 /* the caller must guarantee arg sanity before calling these */
236 int (*read_mixer)(struct ess_card *card, int index);
237 void (*write_mixer)(struct ess_card *card,int mixer, int vol);
238 int (*recmask_io)(struct ess_card *card,int rw,int mask);
239 } mix;
240
241 struct ess_state channels[8];
242 u16 maestro_map[32]; /* Register map */
243
244 /* hardware resources */
245 u32 iobase;
246 u32 irq;
247
248 };
249
250 extern __inline__ unsigned ld2(unsigned int x)
251 {
252 unsigned r = 0;
253
254 if (x >= 0x10000) {
255 x >>= 16;
256 r += 16;
257 }
258 if (x >= 0x100) {
259 x >>= 8;
260 r += 8;
261 }
262 if (x >= 0x10) {
263 x >>= 4;
264 r += 4;
265 }
266 if (x >= 4) {
267 x >>= 2;
268 r += 2;
269 }
270 if (x >= 2)
271 r++;
272 return r;
273 }
274
275
276 /* --------------------------------------------------------------------- */
277
278 static struct ess_card *devs = NULL;
279
280 /* --------------------------------------------------------------------- */
281
282
283 /*
284 * ESS Maestro AC97 codec programming interface.
285 */
286
287 static void maestro_ac97_set(int io, u8 cmd, u16 val)
288 {
289 int i;
290 /*
291 * Wait for the codec bus to be free
292 */
293
294 for(i=0;i<10000;i++)
295 {
296 if(!(inb(io+ESS_AC97_INDEX)&1))
297 break;
298 }
299 /*
300 * Write the bus
301 */
302 outw(val, io+ESS_AC97_DATA);
303 udelay(1);
304 /* should actually be delaying 10 milliseconds? */
305 outb(cmd, io+ESS_AC97_INDEX);
306 udelay(1);
307 }
308
309 static u16 maestro_ac97_get(int io, u8 cmd)
310 {
311 int sanity=100000;
312 u16 data;
313 int i;
314
315 /*
316 * Wait for the codec bus to be free
317 */
318
319 for(i=0;i<10000;i++)
320 {
321 if(!(inb(io+ESS_AC97_INDEX)&1))
322 break;
323 }
324
325 outb(cmd|0x80, io+ESS_AC97_INDEX);
326 udelay(1);
327
328 while(inb(io+ESS_AC97_INDEX)&1)
329 {
330 sanity--;
331 if(!sanity)
332 {
333 printk(KERN_ERR "maestro: ac97 codec read timeout.\n");
334 return 0;
335 }
336 }
337 data=inw(io+ESS_AC97_DATA);
338 udelay(1);
339 return data;
340 }
341
342 /*
343 * The Maestro can be wired to a standard AC97 compliant codec
344 * (see www.intel.com for the pdf's on this), or to a PT101 codec
345 * which appears to be the ES1918 (data sheet on the esstech.com.tw site)
346 *
347 * The PT101 setup is untested.
348 */
349
350 static u16 maestro_ac97_init(int iobase)
351 {
352
353 int val, seid, caps;
354 u16 vend1, vend2;
355
356 #if 0 /* an experiment for another time */
357 /* aim at the second codec */
358 outw(0x21, iobase+0x38);
359 outw(0x5555, iobase+0x3a);
360 outw(0x5555, iobase+0x3c);
361 udelay(1);
362 vend1 = maestro_ac97_get(iobase, 0x7c);
363 vend2 = maestro_ac97_get(iobase, 0x7e);
364 if(vend1 != 0xffff || vend2 != 0xffff) {
365 printk("maestro: It seems you have a second codec: %x %x, please report this.\n",
366 vend1,vend2);
367 }
368 /* back to the first */
369 outw(0x0, iobase+0x38);
370 outw(0x0, iobase+0x3a);
371 outw(0x0, iobase+0x3c);
372 #endif
373
374 /* should make sure we're ac97 2.1? */
375 vend1 = maestro_ac97_get(iobase, 0x7c);
376 vend2 = maestro_ac97_get(iobase, 0x7e);
377
378 val = maestro_ac97_get(iobase, 0x00);
379 seid = val >> 8;
380 caps = val & 255;
381
382 printk(KERN_INFO "maestro: AC97 Codec detected: v: 0x%2x%2x 3d: 0x%x caps: 0x%x\n",
383 vend1,vend2,seid, caps);
384
385 switch ((long)(vend1 << 16) | vend2) {
386 /* magic vendor specifc init code, _no_ idea what these do */
387 #if 0
388 case 0x83847609: /* ESS 1921 */
389 maestro_ac97_set(iobase,0x76,0xABBA); /* o/~ Take a chance on me o/~ */
390 udelay(20);
391 maestro_ac97_set(iobase,0x78,0x3002);
392 udelay(20);
393 maestro_ac97_set(iobase,0x78,0x3802);
394 udelay(20);
395 break;
396 #endif
397 default: break;
398 }
399
400 /* set master, headphone, master mono */
401 maestro_ac97_set(iobase, 0x02, 0x0000);
402 /* always set headphones to max unmuted, OSS won't
403 let us change it :( */
404 maestro_ac97_set(iobase, 0x04, 0x0000);
405 maestro_ac97_set(iobase, 0x06, 0x0000);
406 maestro_ac97_set(iobase, 0x08, 0x0606);
407 /* beep, phone, mic, line, cd video, aux */
408 maestro_ac97_set(iobase, 0x0A, 0x1F1F);
409 maestro_ac97_set(iobase, 0x0C, 0x1F1F);
410 maestro_ac97_set(iobase, 0x0E, 0x1F1F);
411 maestro_ac97_set(iobase, 0x10, 0x1F1F);
412 maestro_ac97_set(iobase, 0x12, 0x1F1F);
413 maestro_ac97_set(iobase, 0x14, 0x1F1F);
414 maestro_ac97_set(iobase, 0x16, 0x1F1F);
415 /* unmute, but set pcm out to 1/2 */
416 maestro_ac97_set(iobase, 0x18, 0x0808);
417 /* null record select */
418 maestro_ac97_set(iobase, 0x1A, 0x0000);
419 /* record gain, record gain mic.. */
420 maestro_ac97_set(iobase, 0x1C, 0x0404);
421 maestro_ac97_set(iobase, 0x1E, 0x0404);
422 /* null misc stuff */
423 maestro_ac97_set(iobase, 0x20, 0x0000);
424 /* power up various units? */
425 maestro_ac97_set(iobase, 0x26, 0x000F);
426
427 return 0;
428 }
429
430 static u16 maestro_pt101_init(int iobase)
431 {
432 printk(KERN_INFO "maestro: PT101 Codec detected, initializing but _not_ installing mixer device.\n");
433 /* who knows.. */
434 maestro_ac97_set(iobase, 0x2A, 0x0001);
435 maestro_ac97_set(iobase, 0x2C, 0x0000);
436 maestro_ac97_set(iobase, 0x2C, 0xFFFF);
437 maestro_ac97_set(iobase, 0x10, 0x9F1F);
438 maestro_ac97_set(iobase, 0x12, 0x0808);
439 maestro_ac97_set(iobase, 0x14, 0x9F1F);
440 maestro_ac97_set(iobase, 0x16, 0x9F1F);
441 maestro_ac97_set(iobase, 0x18, 0x0404);
442 maestro_ac97_set(iobase, 0x1A, 0x0000);
443 maestro_ac97_set(iobase, 0x1C, 0x0000);
444 maestro_ac97_set(iobase, 0x02, 0x0404);
445 maestro_ac97_set(iobase, 0x04, 0x0808);
446 maestro_ac97_set(iobase, 0x0C, 0x801F);
447 maestro_ac97_set(iobase, 0x0E, 0x801F);
448 return 0;
449 }
450
451 static void maestro_ac97_reset(int ioaddr)
452 {
453 outw(0x2000, ioaddr+0x36);
454 udelay(20);
455 outw(0x0000, ioaddr+0x36);
456 udelay(200);
457 }
458
459 /*
460 * Indirect register access. Not all registers are readable so we
461 * need to keep register state ourselves
462 */
463
464 #define WRITEABLE_MAP 0xEFFFFF
465 #define READABLE_MAP 0x64003F
466
467 /*
468 * The Maestro engineers were a little indirection happy. These indirected
469 * registers themselves include indirect registers at another layer
470 */
471
472 static void maestro_write(struct ess_state *ess, u16 reg, u16 data)
473 {
474 long ioaddr = ess->card->iobase;
475 unsigned long flags;
476 save_flags(flags);
477 cli();
478 outw(reg, ioaddr+0x02);
479 outw(data, ioaddr+0x00);
480 ess->card->maestro_map[reg]=data;
481 restore_flags(flags);
482 }
483
484 static u16 maestro_read(struct ess_state *ess, u16 reg)
485 {
486 long ioaddr = ess->card->iobase;
487 if(READABLE_MAP & (1<<reg))
488 {
489 unsigned long flags;
490 save_flags(flags);
491 cli();
492 outw(reg, ioaddr+0x02);
493 ess->card->maestro_map[reg]=inw(ioaddr+0x00);
494 restore_flags(flags);
495 }
496 return ess->card->maestro_map[reg];
497 }
498
499 /*
500 * These routines handle accessing the second level indirections to the
501 * wave ram.
502 */
503
504 /*
505 * The register names are the ones ESS uses (see 104T31.ZIP)
506 */
507
508 #define IDR0_DATA_PORT 0x00
509 #define IDR1_CRAM_POINTER 0x01
510 #define IDR2_CRAM_DATA 0x02
511 #define IDR3_WAVE_DATA 0x03
512 #define IDR4_WAVE_PTR_LOW 0x04
513 #define IDR5_WAVE_PTR_HI 0x05
514 #define IDR6_TIMER_CTRL 0x06
515 #define IDR7_WAVE_ROMRAM 0x07
516
517 static void apu_index_set(struct ess_state *ess, u16 index)
518 {
519 int i;
520 maestro_write(ess, IDR1_CRAM_POINTER, index);
521 for(i=0;i<1000;i++)
522 if(maestro_read(ess, IDR1_CRAM_POINTER)==index)
523 return;
524 printk(KERN_WARNING "maestro: APU register select failed.\n");
525 }
526
527 static void apu_data_set(struct ess_state *ess, u16 data)
528 {
529 int i;
530 for(i=0;i<1000;i++)
531 {
532 if(maestro_read(ess, IDR0_DATA_PORT)==data)
533 return;
534 maestro_write(ess, IDR0_DATA_PORT, data);
535 }
536 }
537
538 /*
539 * This is the public interface for APU manipulation. It handles the
540 * interlock to avoid two APU writes in parallel etc. Don't diddle
541 * directly with the stuff above.
542 */
543
544 static void apu_set_register(struct ess_state *ess, u16 channel, u8 reg, u16 data)
545 {
546 unsigned long flags;
547
548 if(channel&ESS_CHAN_HARD)
549 channel&=~ESS_CHAN_HARD;
550 else
551 {
552 if(channel>3)
553 printk("BAD CHANNEL %d.\n",channel);
554 else
555 channel = ess->apu[channel];
556 }
557
558 reg|=(channel<<4);
559
560 save_flags(flags);
561 cli();
562 apu_index_set(ess, reg);
563 apu_data_set(ess, data);
564 restore_flags(flags);
565 }
566
567 static u16 apu_get_register(struct ess_state *ess, u16 channel, u8 reg)
568 {
569 unsigned long flags;
570 u16 v;
571
572 if(channel&ESS_CHAN_HARD)
573 channel&=~ESS_CHAN_HARD;
574 else
575 channel = ess->apu[channel];
576
577 reg|=(channel<<4);
578
579 save_flags(flags);
580 cli();
581 apu_index_set(ess, reg);
582 v=maestro_read(ess, IDR0_DATA_PORT);
583 restore_flags(flags);
584 return v;
585 }
586
587
588 /*
589 * The wavecache does pci fetches for us and feeds
590 * them to the APUs..
591 * XXX describe interface
592 */
593
594 static void wave_set_register(struct ess_state *ess, u16 reg, u16 value)
595 {
596 long ioaddr = ess->card->iobase;
597 unsigned long flags;
598
599 save_flags(flags);
600 cli();
601 outw(reg, ioaddr+0x10);
602 outw(value, ioaddr+0x12);
603 restore_flags(flags);
604 }
605
606 static u16 wave_get_register(struct ess_state *ess, u16 reg)
607 {
608 long ioaddr = ess->card->iobase;
609 unsigned long flags;
610 u16 value;
611
612 save_flags(flags);
613 cli();
614 outw(reg, ioaddr+0x10);
615 value=inw(ioaddr+0x12);
616 restore_flags(flags);
617
618 return value;
619 }
620
621 static void sound_reset(int ioaddr)
622 {
623 outw(0x2000, 0x18+ioaddr);
624 udelay(10);
625 outw(0x0000, 0x18+ioaddr);
626 udelay(10);
627 }
628
629 static void set_apu_fmt(struct ess_state *s, int apu, int mode)
630 {
631 if(mode&ESS_CFMT_16BIT) {
632 s->apu_mode[apu] = 0x10;
633 s->apu_mode[apu+1] = 0x10;
634 } else {
635 s->apu_mode[apu] = 0x30;
636 s->apu_mode[apu+1] = 0x30;
637 }
638 }
639
640 static void set_fmt(struct ess_state *s, unsigned char mask, unsigned char data)
641 {
642 s->fmt = (s->fmt & mask) | data;
643 set_apu_fmt(s, 0, s->fmt & ESS_CFMT_MASK);
644 set_apu_fmt(s, 2, (s->fmt >> ESS_CFMT_CSHIFT) & ESS_CFMT_MASK);
645 }
646
647 static u16 compute_rate(u32 freq)
648 {
649 if(freq==48000)
650 return 0xFFFF;
651 freq<<=16;
652 freq/=48000;
653 return freq;
654 }
655
656 static void set_dac_rate(struct ess_state *s, unsigned rate)
657 {
658 u32 freq;
659
660 if (rate > 48000)
661 rate = 48000;
662 if (rate < 4000)
663 rate = 4000;
664
665 s->ratedac = rate;
666
667 if(!(s->fmt & ESS_CFMT_16BIT))
668 rate >>= 1; /* who knows */
669
670 /* M_printk("computing dac rate %d with mode %d\n",rate,s->fmt);*/
671
672 freq = compute_rate(rate);
673
674 /* Load the frequency, turn on 6dB, turn off the effects */
675 apu_set_register(s, 0, 2, (freq&0xFF)<<8|0x10);
676 apu_set_register(s, 0, 3, freq>>8);
677 apu_set_register(s, 1, 2, (freq&0xFF)<<8|0x10);
678 apu_set_register(s, 1, 3, freq>>8);
679 }
680
681 static void set_adc_rate(struct ess_state *s, unsigned rate)
682 {
683 u32 freq;
684
685 if (rate > 48000)
686 rate = 48000;
687 if (rate < 4000)
688 rate = 4000;
689
690 s->rateadc = rate;
691
692 freq = compute_rate(rate);
693
694 /* Load the frequency, turn on 6dB, turn off the effects */
695 apu_set_register(s, 2, 2, (freq&0xFF)<<8|0x10);
696 apu_set_register(s, 2, 3, freq>>8);
697 apu_set_register(s, 3, 2, (freq&0xFF)<<8|0x10);
698 apu_set_register(s, 3, 3, freq>>8);
699 }
700
701
702 /*
703 * Native play back driver
704 */
705
706 static void ess_play_setup(struct ess_state *ess, int mode, u32 rate, void *buffer, int size)
707 {
708 u32 pa;
709 u32 tmpval;
710 int high_apu = 0;
711 int channel;
712
713 M_printk("mode=%d rate=%d buf=%p len=%d.\n",
714 mode, rate, buffer, size);
715
716 /* all maestro sizes are in 16bit words */
717 size >>=1;
718
719 /* we're given the full size of the buffer, but
720 in stereo each channel will only play its half */
721 if(mode&ESS_CFMT_STEREO) {
722 size >>=1;
723 high_apu++;
724 }
725
726 for(channel=0; channel <= high_apu; channel++)
727 {
728 int i;
729
730 /*
731 * To understand this it helps to know how the
732 * wave cache works. There are 4 DSP wavecache
733 * blocks which are 0x1FC->0x1FF. They are selected
734 * by setting bits 22,21,20 of the address to
735 * 1 X Y where X Y select the block.
736 *
737 * In addition stereo pairing is supported. This is
738 * set in the wave cache control for the channel as is
739 * 8bit unsigned.
740 *
741 * Note that this causes a problem. With our limit of
742 * about 12 full duplex pairs (48 channels active) we
743 * will need to do a lot of juggling to get all the
744 * memory we want sufficiently close together.
745 *
746 * Even with 64K blocks that means
747 * 24 channel pairs
748 * 6 pairs/block
749 *
750 * 10K per channel pair = 5000 samples.
751 */
752
753 if(!channel)
754 pa = virt_to_bus(buffer);
755 else
756 /* right channel plays its split half.
757 *2 accomodates for rampant shifting earlier */
758 pa = virt_to_bus(buffer + size*2);
759
760 M_printk("sending pa %x to %d\n",pa,channel);
761
762 wave_set_register(ess, 0x01FC, (pa&0xFFE00000)>>12);
763
764 /* set the wavecache control reg */
765 tmpval = (pa - 0x10) & 0xFFF8;
766 #if 0
767 if(mode & 1) tmpval |= 2; /* stereo */
768 #endif
769 if(!(mode & 2)) tmpval |= 4; /* 8bit */
770 wave_set_register(ess, ess->apu[channel]<<3, tmpval);
771
772 pa&=0x1FFFFF; /* Low 21 bits */
773 pa>>=1; /* words */
774
775 /* base offset of dma calcs when reading the pointer
776 on this left one */
777 if(!channel) ess->dma_dac.base = pa&0xFFFF;
778
779 #if 0
780 if(mode&ESS_CFMT_STEREO) /* Enable stereo */
781 pa|=0x00800000;
782 #endif
783 pa|=0x00400000; /* System RAM */
784
785 /* Begin loading the APU */
786 for(i=0;i<15;i++) /* clear all PBRs */
787 apu_set_register(ess, channel, i, 0x0000);
788
789 /* Load the frequency, turn on 6dB, turn off the effects */
790 /* apu_set_register(ess, channel, 2, (rate&0xFF)<<8|0x10);
791 apu_set_register(ess, channel, 3, rate>>8);*/
792
793 /* Load the buffer into the wave engine */
794 apu_set_register(ess, channel, 4, ((pa>>16)&0xFF)<<8);
795 /* XXX reg is little endian.. */
796 apu_set_register(ess, channel, 5, pa&0xFFFF);
797 apu_set_register(ess, channel, 6, (pa+size)&0xFFFF);
798 /* setting loop == sample len */
799 apu_set_register(ess, channel, 7, size);
800
801 /* clear effects/env.. */
802 apu_set_register(ess, channel, 8, 0x0000);
803 /* aplitudeNow to 0xd0? */
804 apu_set_register(ess, channel, 9, 0xD000);
805
806 /* set the panning reg of the apu to left/right/mid.. */
807
808 /* clear routing stuff */
809 apu_set_register(ess, channel, 11, 0x0000);
810 /* mark dma and turn on filter stuff? */
811 apu_set_register(ess, channel, 0, 0x400F);
812
813 if(mode&ESS_CFMT_STEREO)
814 /* set panning: left or right */
815 apu_set_register(ess, channel, 10, 0x8F00 | (channel ? 0x10 : 0));
816 else
817 apu_set_register(ess, channel, 10, 0x8F08);
818
819 }
820
821 /* clear WP interupts */
822 outw(1, ess->card->iobase+0x04);
823 /* enable WP ints */
824 outw(inw(ess->card->iobase+0x18)|4, ess->card->iobase+0x18);
825
826 set_dac_rate(ess,rate);
827
828 for(channel=0; channel<=high_apu; channel++)
829 {
830 /* Turn on the DMA */
831 if(mode&ESS_CFMT_16BIT)
832 {
833 apu_set_register(ess, channel, 0,
834 (apu_get_register(ess, channel, 0)&0xFF0F)|0x10);
835 ess->apu_mode[channel]=0x10;
836 }
837 else
838 {
839 apu_set_register(ess, channel, 0,
840 (apu_get_register(ess, channel, 0)&0xFF0F)|0x30);
841 ess->apu_mode[channel]=0x30;
842 }
843 }
844 }
845
846 /* --------------------------------------------------------------------- */
847
848 static void set_dmaa(struct ess_state *s, unsigned int addr, unsigned int count)
849 {
850 }
851
852 static void set_dmac(struct ess_state *s, unsigned int addr, unsigned int count)
853 {
854 }
855
856 /* Playback pointer */
857 extern __inline__ unsigned get_dmaa(struct ess_state *s)
858 {
859 long ioport = s->card->iobase;
860 int offset;
861
862 outw(1, ioport+2);
863 outw(s->apu[0]<<4|5, ioport);
864 outw(0, ioport+2);
865 offset=inw(ioport);
866
867 /* M_printk("dmaa: offset: %d, base: %d\n",offset,s->dma_dac.base);*/
868
869 offset-=s->dma_dac.base;
870
871 return (offset&0xFFFE)/*<<1*/; /* XXX printk didn't have it */
872 }
873
874 /* Record pointer */
875 extern __inline__ unsigned get_dmac(struct ess_state *s)
876 {
877 long ioport = s->card->iobase;
878 int offset;
879
880 outw(1, ioport+2);
881 outw(s->apu[2]<<4|5, ioport);
882 outw(0, ioport+2);
883 offset=inw(ioport);
884
885 /* The offset is an address not a position relative to base */
886
887 return (offset&0xFFFE)<<1; /* hardware is in words */
888 }
889
890 /*
891 * Meet Bob, the timer...
892 */
893
894 static void ess_interrupt(int irq, void *dev_id, struct pt_regs *regs);
895
896 #define ESS_HW_TIMER
897
898 #ifndef ESS_HW_TIMER
899
900 /* old kernel timer based timer ints, should BOB prove flakey */
901
902 static struct timer_list tmp_timer;
903
904 static int bob_stopped;
905
906 static void ess_interrupt_fake(unsigned long v)
907 {
908 ess_interrupt(5, (void *)v, NULL);
909 del_timer(&tmp_timer);
910 if(!bob_stopped)
911 {
912 tmp_timer.expires=jiffies+1;
913 add_timer(&tmp_timer);
914 }
915 else
916 M_printk("Stopping bob (SW)\n");
917 }
918
919 static void stop_bob(struct ess_state *s)
920 {
921 bob_stopped=1;
922 }
923
924 static void kill_bob(struct ess_state *s)
925 {
926 del_timer(&tmp_timer);
927 M_printk("Killing bob (SW)\n");
928 }
929
930 static void start_bob(struct ess_state *s)
931 {
932 static int init=1;
933 if(init)
934 {
935 init=0;
936 init_timer(&tmp_timer);
937 tmp_timer.function = ess_interrupt_fake;
938 }
939 bob_stopped = 0;
940 if(!timer_pending(&tmp_timer))
941 {
942 del_timer(&tmp_timer);
943 tmp_timer.expires = jiffies+1;
944 tmp_timer.data = (unsigned long)s->card;
945 add_timer(&tmp_timer);
946 M_printk("Starting bob (SW)\n");
947 }
948 }
949
950 #else
951
952 /* nice HW BOB implementation. cheers, eric. */
953
954 static void stop_bob(struct ess_state *s)
955 {
956 /* Mask IDR 11,17 */
957 maestro_write(s, 0x11, maestro_read(s, 0x11)&~1);
958 maestro_write(s, 0x17, maestro_read(s, 0x17)&~1);
959 }
960
961 /* eventually we could be clever and limit bob ints
962 to the frequency at which our smallest duration
963 chunks may expire */
964 static void start_bob(struct ess_state *s)
965 {
966 stop_bob(s); // make sure bob's not already running
967
968 maestro_write(s, 6, 0x8000 |(1<<12) | (5<<5) | 11); // (50MHz/2^14)/12 = 254 Hz = 40 mS
969
970 /* Now set IDR 11/17 */
971 maestro_write(s, 0x11, maestro_read(s, 0x11)|1);
972 maestro_write(s, 0x17, maestro_read(s, 0x17)|1);
973 }
974 #endif // ESS_HW_TIMER
975 /* --------------------------------------------------------------------- */
976
977 static int adc_active = 0;
978
979 extern inline void stop_adc(struct ess_state *s)
980 {
981 unsigned long flags;
982
983 spin_lock_irqsave(&s->lock, flags);
984 /* Stop left and right recording APU */
985 s->enable &= ~ADC_RUNNING;
986 apu_set_register(s, 2, 0, apu_get_register(s, 2, 0)&0xFF0F);
987 apu_set_register(s, 3, 0, apu_get_register(s, 3, 0)&0xFF0F);
988 adc_active&=~1;
989 // if(!adc_active)
990 // stop_bob(s);
991 spin_unlock_irqrestore(&s->lock, flags);
992 }
993
994 extern inline void stop_dac(struct ess_state *s)
995 {
996 unsigned long flags;
997
998 spin_lock_irqsave(&s->lock, flags);
999 s->enable &= ~DAC_RUNNING;
1000 apu_set_register(s, 0, 0, apu_get_register(s, 0, 0)&0xFF0F);
1001 apu_set_register(s, 1, 0, apu_get_register(s, 1, 0)&0xFF0F);
1002 adc_active&=~2;
1003 // if(!adc_active)
1004 // stop_bob(s);
1005 spin_unlock_irqrestore(&s->lock, flags);
1006 }
1007
1008 static void start_dac(struct ess_state *s)
1009 {
1010 unsigned long flags;
1011
1012 spin_lock_irqsave(&s->lock, flags);
1013 if ((s->dma_dac.mapped || s->dma_dac.count > 0) && s->dma_dac.ready) {
1014 s->enable |= DAC_RUNNING;
1015
1016 apu_set_register(s, 0, 0,
1017 (apu_get_register(s, 0, 0)&0xFF0F)|s->apu_mode[0]);
1018
1019 if(s->fmt & ESS_CFMT_STEREO)
1020 apu_set_register(s, 1, 0,
1021 (apu_get_register(s, 1, 0)&0xFF0F)|s->apu_mode[1]);
1022 }
1023 // if(!adc_active)
1024 // start_bob(s);
1025 adc_active|=2;
1026 spin_unlock_irqrestore(&s->lock, flags);
1027 }
1028
1029 static void start_adc(struct ess_state *s)
1030 {
1031 unsigned long flags;
1032
1033 spin_lock_irqsave(&s->lock, flags);
1034 if ((s->dma_adc.mapped || s->dma_adc.count < (signed)(s->dma_adc.dmasize - 2*s->dma_adc.fragsize))
1035 && s->dma_adc.ready) {
1036 s->enable |= ADC_RUNNING;
1037 apu_set_register(s, 2, 0,
1038 (apu_get_register(s, 2, 0)&0xFF0F)|s->apu_mode[2]);
1039 apu_set_register(s, 3, 0,
1040 (apu_get_register(s, 3, 0)&0xFF0F)|s->apu_mode[3]);
1041 }
1042 // if(!adc_active)
1043 // start_bob(s);
1044 adc_active|=1;
1045 spin_unlock_irqrestore(&s->lock, flags);
1046 }
1047
1048 /* --------------------------------------------------------------------- */
1049
1050 #define DMABUF_DEFAULTORDER (15-PAGE_SHIFT)
1051 #define DMABUF_MINORDER 1
1052
1053 static void dealloc_dmabuf(struct dmabuf *db)
1054 {
1055 unsigned long map, mapend;
1056
1057 if (db->rawbuf) {
1058 /* undo marking the pages as reserved */
1059 mapend = MAP_NR(db->rawbuf + (PAGE_SIZE << db->buforder) - 1);
1060 for (map = MAP_NR(db->rawbuf); map <= mapend; map++)
1061 clear_bit(PG_reserved, &mem_map[map].flags);
1062 free_pages((unsigned long)db->rawbuf, db->buforder);
1063 }
1064 db->rawbuf = NULL;
1065 db->mapped = db->ready = 0;
1066 }
1067
1068
1069 static int prog_dmabuf(struct ess_state *s, unsigned rec)
1070 {
1071 struct dmabuf *db = rec ? &s->dma_adc : &s->dma_dac;
1072 unsigned rate = rec ? s->rateadc : s->ratedac;
1073 int order;
1074 unsigned bytepersec;
1075 unsigned bufs;
1076 unsigned long map, mapend;
1077 unsigned char fmt;
1078 unsigned long flags;
1079
1080 spin_lock_irqsave(&s->lock, flags);
1081 fmt = s->fmt;
1082 if (rec) {
1083 s->enable &= ~ESS_ENABLE_RE;
1084 fmt >>= ESS_CFMT_CSHIFT;
1085 } else {
1086 s->enable &= ~ESS_ENABLE_PE;
1087 fmt >>= ESS_CFMT_ASHIFT;
1088 }
1089 spin_unlock_irqrestore(&s->lock, flags);
1090
1091 db->hwptr = db->swptr = db->total_bytes = db->count = db->error = db->endcleared = 0;
1092
1093 if (!db->rawbuf) {
1094 db->ready = db->mapped = 0;
1095
1096 /* alloc as big a chunk as we can */
1097 for (order = DMABUF_DEFAULTORDER; order >= DMABUF_MINORDER && !db->rawbuf; order--)
1098 db->rawbuf = (void *)__get_free_pages(GFP_KERNEL|GFP_DMA, order);
1099
1100 if (!db->rawbuf)
1101 return -ENOMEM;
1102
1103 db->buforder = order;
1104
1105 if ((virt_to_bus(db->rawbuf) ^ (virt_to_bus(db->rawbuf) + (PAGE_SIZE << db->buforder) - 1)) & ~0xffff)
1106 printk(KERN_DEBUG "maestro: DMA buffer crosses 64k boundary: busaddr 0x%lx size %ld\n",
1107 virt_to_bus(db->rawbuf), PAGE_SIZE << db->buforder);
1108
1109 if ((virt_to_bus(db->rawbuf) + (PAGE_SIZE << db->buforder) - 1) & ~0xffffff)
1110 printk(KERN_DEBUG "maestro: DMA buffer beyond 16MB: busaddr 0x%lx size %ld\n",
1111 virt_to_bus(db->rawbuf), PAGE_SIZE << db->buforder);
1112
1113 /* now mark the pages as reserved; otherwise remap_page_range doesn't do what we want */
1114 mapend = MAP_NR(db->rawbuf + (PAGE_SIZE << db->buforder) - 1);
1115 for (map = MAP_NR(db->rawbuf); map <= mapend; map++)
1116 set_bit(PG_reserved, &mem_map[map].flags);
1117 }
1118 bytepersec = rate << sample_shift[fmt];
1119 bufs = PAGE_SIZE << db->buforder;
1120 if (db->ossfragshift) {
1121 if ((1000 << db->ossfragshift) < bytepersec)
1122 db->fragshift = ld2(bytepersec/1000);
1123 else
1124 db->fragshift = db->ossfragshift;
1125 } else {
1126 db->fragshift = ld2(bytepersec/100/(db->subdivision ? db->subdivision : 1));
1127 if (db->fragshift < 3)
1128 db->fragshift = 3;
1129 }
1130 db->numfrag = bufs >> db->fragshift;
1131 while (db->numfrag < 4 && db->fragshift > 3) {
1132 db->fragshift--;
1133 db->numfrag = bufs >> db->fragshift;
1134 }
1135 db->fragsize = 1 << db->fragshift;
1136 if (db->ossmaxfrags >= 4 && db->ossmaxfrags < db->numfrag)
1137 db->numfrag = db->ossmaxfrags;
1138 db->fragsamples = db->fragsize >> sample_shift[fmt];
1139 db->dmasize = db->numfrag << db->fragshift;
1140 memset(db->rawbuf, (fmt & ESS_CFMT_16BIT) ? 0 : 0x80, db->dmasize);
1141 spin_lock_irqsave(&s->lock, flags);
1142 if (rec) {
1143 set_dmac(s, virt_to_bus(db->rawbuf), db->numfrag << db->fragshift);
1144 /* program enhanced mode registers */
1145 /* FILL */
1146 } else {
1147 //set_dmaa(s, virt_to_bus(db->rawbuf), db->numfrag << db->fragshift);
1148 /* program enhanced mode registers */
1149 /* FILL */
1150 //set_dac_rate(s, s->ratedac); // redundant
1151 ess_play_setup(s, fmt, s->ratedac,
1152 db->rawbuf, db->numfrag << db->fragshift);
1153 }
1154 spin_unlock_irqrestore(&s->lock, flags);
1155 db->ready = 1;
1156 return 0;
1157 }
1158
1159 extern __inline__ void clear_advance(struct ess_state *s)
1160 {
1161 unsigned char c = (s->fmt & (ESS_CFMT_16BIT << ESS_CFMT_ASHIFT)) ? 0 : 0x80;
1162 unsigned char *buf = s->dma_dac.rawbuf;
1163 unsigned bsize = s->dma_dac.dmasize;
1164 unsigned bptr = s->dma_dac.swptr;
1165 unsigned len = s->dma_dac.fragsize;
1166
1167 if (bptr + len > bsize) {
1168 unsigned x = bsize - bptr;
1169 memset(buf + bptr, c, x);
1170 /* account for wrapping? */
1171 bptr = 0;
1172 len -= x;
1173 }
1174 memset(buf + bptr, c, len);
1175 }
1176
1177 /* call with spinlock held! */
1178 static void ess_update_ptr(struct ess_state *s)
1179 {
1180 unsigned hwptr;
1181 int diff;
1182
1183 /* update ADC pointer */
1184 if (s->dma_adc.ready) {
1185 M_printk("adc ready.. \n");
1186 hwptr = (/*s->dma_adc.dmasize - */get_dmac(s)) % s->dma_adc.dmasize;
1187 diff = (s->dma_adc.dmasize + hwptr - s->dma_adc.hwptr) % s->dma_adc.dmasize;
1188 s->dma_adc.hwptr = hwptr;
1189 s->dma_adc.total_bytes += diff;
1190 s->dma_adc.count += diff;
1191 if (s->dma_adc.count >= (signed)s->dma_adc.fragsize)
1192 wake_up(&s->dma_adc.wait);
1193 if (!s->dma_adc.mapped) {
1194 if (s->dma_adc.count > (signed)(s->dma_adc.dmasize - ((3 * s->dma_adc.fragsize) >> 1))) {
1195 s->enable &= ~ESS_ENABLE_RE;
1196 /* FILL ME */
1197 // wrindir(s, SV_CIENABLE, s->enable);
1198 stop_adc(s);
1199 s->dma_adc.error++;
1200 }
1201 }
1202 }
1203 /* update DAC pointer */
1204 if (s->dma_dac.ready) {
1205 hwptr = (/*s->dma_dac.dmasize -*/ get_dmaa(s)) % s->dma_dac.dmasize;
1206 diff = (s->dma_dac.dmasize + hwptr - s->dma_dac.hwptr) % s->dma_dac.dmasize;
1207 /* M_printk("updating dac: hwptr: %d diff: %d\n",hwptr,diff);*/
1208 s->dma_dac.hwptr = hwptr;
1209 s->dma_dac.total_bytes += diff;
1210 if (s->dma_dac.mapped) {
1211 s->dma_dac.count += diff;
1212 if (s->dma_dac.count >= (signed)s->dma_dac.fragsize)
1213 wake_up(&s->dma_dac.wait);
1214 } else {
1215 s->dma_dac.count -= diff;
1216 if (s->dma_dac.count <= 0) {
1217 s->enable &= ~ESS_ENABLE_PE;
1218 /* FILL ME */
1219 // wrindir(s, SV_CIENABLE, s->enable);
1220
1221 stop_dac(s);
1222 s->dma_dac.error++;
1223 } else if (s->dma_dac.count <= (signed)s->dma_dac.fragsize && !s->dma_dac.endcleared) {
1224 clear_advance(s);
1225 s->dma_dac.endcleared = 1;
1226 }
1227 if (s->dma_dac.count + (signed)s->dma_dac.fragsize <= (signed)s->dma_dac.dmasize)
1228 wake_up(&s->dma_dac.wait);
1229 }
1230 }
1231 }
1232
1233 static void ess_interrupt(int irq, void *dev_id, struct pt_regs *regs)
1234 {
1235 struct ess_state *s;
1236 struct ess_card *c = (struct ess_card *)dev_id;
1237 int i;
1238 u32 event;
1239
1240 event = inb(c->iobase+0x1A);
1241
1242 outw(inw(c->iobase+4)&1, c->iobase+4);
1243
1244 /* M_printk("maestro int: %x\n",event);*/
1245
1246 if(event&(1<<6))
1247 {
1248 /* XXX if we have a hw volume control int enable
1249 all the ints? doesn't make sense.. */
1250 event = inw(c->iobase+0x18);
1251 outb(0xFF, c->iobase+0x1A);
1252 }
1253 else
1254 {
1255 /* else ack 'em all, i imagine */
1256 outb(0xFF, c->iobase+0x1A);
1257 }
1258
1259 /*
1260 * Update the pointers for all APU's we are running.
1261 */
1262 for(i=0;i<8;i++)
1263 {
1264 s=&c->channels[i];
1265 if(s->dev_audio == -1)
1266 break;
1267 spin_lock(&s->lock);
1268 ess_update_ptr(s);
1269 spin_unlock(&s->lock);
1270 }
1271 }
1272
1273
1274 /* --------------------------------------------------------------------- */
1275
1276 static const char invalid_magic[] = KERN_CRIT "maestro: invalid magic value in %s\n";
1277
1278 #define VALIDATE_MAGIC(FOO,MAG) \
1279 ({ \
1280 if (!(FOO) || (FOO)->magic != MAG) { \
1281 printk(invalid_magic,__FUNCTION__); \
1282 return -ENXIO; \
1283 } \
1284 })
1285
1286 #define VALIDATE_STATE(a) VALIDATE_MAGIC(a,ESS_STATE_MAGIC)
1287 #define VALIDATE_CARD(a) VALIDATE_MAGIC(a,ESS_CARD_MAGIC)
1288
1289 /* --------------------------------------------------------------------- */
1290
1291 /* ac97 mixer routines. */
1292
1293 #define AC97_STEREO_MASK (SOUND_MASK_VOLUME|\
1294 SOUND_MASK_PCM|SOUND_MASK_LINE|SOUND_MASK_CD|\
1295 SOUND_MASK_VIDEO|SOUND_MASK_LINE1|SOUND_MASK_IGAIN)
1296
1297 #define AC97_SUPPORTED_MASK (AC97_STEREO_MASK | \
1298 SOUND_MASK_BASS|SOUND_MASK_TREBLE|SOUND_MASK_MIC|\
1299 SOUND_MASK_SPEAKER)
1300
1301 #define AC97_RECORD_MASK (SOUND_MASK_MIC|\
1302 SOUND_MASK_CD| SOUND_MASK_VIDEO| SOUND_MASK_LINE1| SOUND_MASK_LINE|\
1303 SOUND_MASK_PHONEIN)
1304
1305 #define supported_mixer(CARD,FOO) ( CARD->mix.supported_mixers & (1<<FOO) )
1306
1307 static struct ac97_mixer_hw {
1308 unsigned char offset;
1309 int scale;
1310 } ac97_hw[SOUND_MIXER_NRDEVICES]= {
1311 [SOUND_MIXER_VOLUME] = {0x02,63},
1312 [SOUND_MIXER_BASS] = {0x08,15},
1313 [SOUND_MIXER_TREBLE] = {0x08,15},
1314 [SOUND_MIXER_SPEAKER] = {0x0a,15},
1315 [SOUND_MIXER_MIC] = {0x0e,31},
1316 [SOUND_MIXER_LINE] = {0x10,31},
1317 [SOUND_MIXER_CD] = {0x12,31},
1318 [SOUND_MIXER_VIDEO] = {0x14,31},
1319 [SOUND_MIXER_LINE1] = {0x16,31},
1320 [SOUND_MIXER_PCM] = {0x18,31},
1321 [SOUND_MIXER_IGAIN] = {0x1c,31}
1322 };
1323
1324 /* reads the given OSS mixer from the ac97
1325 the caller must have insured that the ac97 knows
1326 about that given mixer, and should be holding a
1327 spinlock for the card */
1328 static int ac97_read_mixer(struct ess_card *card, int mixer)
1329 {
1330 u16 val;
1331 int ret=0;
1332 struct ac97_mixer_hw *mh = &ac97_hw[mixer];
1333
1334 val = maestro_ac97_get(card->iobase , mh->offset);
1335
1336 if(AC97_STEREO_MASK & (1<<mixer)) {
1337 /* nice stereo mixers .. */
1338 int left,right;
1339
1340 left = (val >> 8) & 0x7f;
1341 right = val & 0x7f;
1342
1343 right = 100 - ((right * 100) / mh->scale);
1344 left = 100 - ((left * 100) / mh->scale);
1345 ret = left | (right << 8);
1346 } else if (mixer == SOUND_MIXER_SPEAKER) {
1347 ret = 100 - ((((val & 0x1e)>>1) * 100) / mh->scale);
1348 } else if (mixer == SOUND_MIXER_MIC) {
1349 ret = 100 - (((val & 0x1f) * 100) / mh->scale);
1350 /* the low bit is optional in the tone sliders and masking
1351 it lets is avoid the 0xf 'bypass'.. */
1352 } else if (mixer == SOUND_MIXER_BASS) {
1353 ret = 100 - ((((val >> 8) & 0xe) * 100) / mh->scale);
1354 } else if (mixer == SOUND_MIXER_TREBLE) {
1355 ret = 100 - (((val & 0xe) * 100) / mh->scale);
1356 }
1357
1358 M_printk("read mixer %d (0x%x) %x -> %x\n",mixer,mh->offset,val,ret);
1359
1360 return ret;
1361 }
1362
1363 /* write the OSS encoded volume to the given OSS encoded mixer,
1364 again caller's job to make sure all is well in arg land,
1365 call with spinlock held */
1366 static void ac97_write_mixer(struct ess_card *card,int mixer, int vol)
1367 {
1368 u16 val=0;
1369 unsigned left, right;
1370 struct ac97_mixer_hw *mh = &ac97_hw[mixer];
1371
1372 /* cleanse input a little */
1373 right = ((vol >> 8) & 0x7f) ;
1374 left = (vol & 0x7f) ;
1375
1376 if(right > 100) right = 100;
1377 if(left > 100) left = 100;
1378
1379 M_printk("wrote mixer %d (0x%x) %d,%d",mixer,mh->offset,left,right);
1380
1381 if(AC97_STEREO_MASK & (1<<mixer)) {
1382 /* stereo mixers */
1383
1384 right = ((100 - right) * mh->scale) / 100;
1385 left = ((100 - left) * mh->scale) / 100;
1386
1387 val = (left << 8) | right;
1388 } else if (mixer == SOUND_MIXER_SPEAKER) {
1389 val = (((100 - left) * mh->scale) / 100) << 1;
1390 } else if (mixer == SOUND_MIXER_MIC) {
1391 val = maestro_ac97_get(card->iobase , mh->offset) & ~0x001f;
1392 val |= (((100 - left) * mh->scale) / 100);
1393 /* the low bit is optional in the tone sliders and masking
1394 it lets is avoid the 0xf 'bypass'.. */
1395 } else if (mixer == SOUND_MIXER_BASS) {
1396 val = maestro_ac97_get(card->iobase , mh->offset) & ~0x0f00;
1397 val |= ((((100 - left) * mh->scale) / 100) << 8) & 0xe0;
1398 } else if (mixer == SOUND_MIXER_TREBLE) {
1399 val = maestro_ac97_get(card->iobase , mh->offset) & ~0x000f;
1400 val |= (((100 - left) * mh->scale) / 100) & 0xe;
1401 }
1402
1403 maestro_ac97_set(card->iobase , mh->offset, val);
1404
1405 M_printk(" -> %x\n",val);
1406 }
1407
1408 enum ac97_recsettings {
1409 AC97_REC_MIC=0,
1410 AC97_REC_CD,
1411 AC97_REC_VIDEO,
1412 AC97_REC_AUX,
1413 AC97_REC_LINE,
1414 AC97_REC_STEREO, /* combination of all enabled outputs.. */
1415 AC97_REC_MONO, /*.. or the mono equivalent */
1416 AC97_REC_PHONE
1417 };
1418 static unsigned int ac97_rm2oss[] = {
1419 [AC97_REC_MIC] = SOUND_MASK_MIC,
1420 [AC97_REC_CD] = SOUND_MASK_CD,
1421 [AC97_REC_VIDEO] = SOUND_MASK_VIDEO,
1422 [AC97_REC_AUX] = SOUND_MASK_LINE1,
1423 [AC97_REC_LINE] = SOUND_MASK_LINE,
1424 [AC97_REC_PHONE] = SOUND_MASK_PHONEIN
1425 };
1426
1427 /* indexed by bit position, XXX dependant on OSS header internals */
1428 static unsigned int ac97_oss_rm[] = {
1429 [SOUND_MIXER_MIC] = AC97_REC_MIC,
1430 [SOUND_MIXER_CD] = AC97_REC_CD,
1431 [SOUND_MIXER_VIDEO] = AC97_REC_VIDEO,
1432 [SOUND_MIXER_LINE1] = AC97_REC_AUX,
1433 [SOUND_MIXER_LINE] = AC97_REC_LINE,
1434 [SOUND_MIXER_PHONEIN] = AC97_REC_PHONE
1435 };
1436
1437 /* read or write the recmask
1438 the ac97 can really have left and right recording
1439 inputs independantly set, but OSS doesn't seem to
1440 want us to express that to the user.
1441 the caller guarantees that we have a supported bit set,
1442 and they must be holding the card's spinlock */
1443 static int ac97_recmask_io(struct ess_card *card, int rw, int mask)
1444 {
1445 unsigned int val;
1446
1447 if (rw) {
1448 /* read it from the card */
1449 val = maestro_ac97_get(card->iobase, 0x1a) & 0x7;
1450 return ac97_rm2oss[val];
1451 }
1452
1453 /* else, write the first set in the mask as the
1454 output */
1455
1456 val = ffs(mask);
1457 val = ac97_oss_rm[val-1];
1458 val |= val << 8; /* set both channels */
1459
1460 maestro_ac97_set(card->iobase,0x1a,val);
1461
1462 return 0;
1463 };
1464
1465 static int ac97_mixer_ioctl(struct ess_card *card, unsigned int cmd, unsigned long arg)
1466 {
1467 unsigned long flags;
1468 int i, val=0;
1469 struct ess_state *s = &card->channels[0];
1470
1471 VALIDATE_CARD(card);
1472 if (cmd == SOUND_MIXER_INFO) {
1473 mixer_info info;
1474 strncpy(info.id, card_names[card->card_type], sizeof(info.id));
1475 strncpy(info.name,card_names[card->card_type],sizeof(info.name));
1476 info.modify_counter = card->mix.modcnt;
1477 if (copy_to_user((void *)arg, &info, sizeof(info)))
1478 return -EFAULT;
1479 return 0;
1480 }
1481 if (cmd == SOUND_OLD_MIXER_INFO) {
1482 _old_mixer_info info;
1483 strncpy(info.id, card_names[card->card_type], sizeof(info.id));
1484 strncpy(info.name,card_names[card->card_type],sizeof(info.name));
1485 if (copy_to_user((void *)arg, &info, sizeof(info)))
1486 return -EFAULT;
1487 return 0;
1488 }
1489 if (cmd == OSS_GETVERSION)
1490 return put_user(SOUND_VERSION, (int *)arg);
1491
1492 if (_IOC_TYPE(cmd) != 'M' || _IOC_SIZE(cmd) != sizeof(int))
1493 return -EINVAL;
1494
1495 if (_IOC_DIR(cmd) == _IOC_READ) {
1496 switch (_IOC_NR(cmd)) {
1497 case SOUND_MIXER_RECSRC: /* give them the current record source */
1498 spin_lock_irqsave(&s->lock, flags);
1499 val = card->mix.recmask_io(card,1,0);
1500 spin_unlock_irqrestore(&s->lock, flags);
1501 break;
1502
1503 case SOUND_MIXER_DEVMASK: /* give them the supported mixers */
1504 val = card->mix.supported_mixers;
1505 break;
1506
1507 case SOUND_MIXER_RECMASK: /* Arg contains a bit for each supported recording source */
1508 val = card->mix.record_sources;
1509 break;
1510
1511 case SOUND_MIXER_STEREODEVS: /* Mixer channels supporting stereo */
1512 val = card->mix.stereo_mixers;
1513 break;
1514
1515 case SOUND_MIXER_CAPS:
1516 val = SOUND_CAP_EXCL_INPUT;
1517 break;
1518
1519 default: /* read a specific mixer */
1520 i = _IOC_NR(cmd);
1521
1522 if ( ! supported_mixer(card,i))
1523 return -EINVAL;
1524
1525 spin_lock_irqsave(&s->lock, flags);
1526 val = card->mix.read_mixer(card,i);
1527 spin_unlock_irqrestore(&s->lock, flags);
1528
1529 break;
1530 }
1531 return put_user(val,(int *)arg);
1532 }
1533
1534 if (_IOC_DIR(cmd) != (_IOC_WRITE|_IOC_READ))
1535 return -EINVAL;
1536
1537 card->mix.modcnt++;
1538
1539 get_user_ret(val, (int *)arg, -EFAULT);
1540
1541 switch (_IOC_NR(cmd)) {
1542 case SOUND_MIXER_RECSRC: /* Arg contains a bit for each recording source */
1543
1544 if(! (val &= card->mix.record_sources)) return -EINVAL;
1545
1546 spin_lock_irqsave(&s->lock, flags);
1547 card->mix.recmask_io(card,0,val);
1548 spin_unlock_irqrestore(&s->lock, flags);
1549 return 0;
1550
1551 default:
1552 i = _IOC_NR(cmd);
1553
1554 if ( ! supported_mixer(card,i))
1555 return -EINVAL;
1556
1557 spin_lock_irqsave(&s->lock, flags);
1558 card->mix.write_mixer(card,i,val);
1559 spin_unlock_irqrestore(&s->lock, flags);
1560
1561 return 0;
1562 }
1563 }
1564
1565 /* --------------------------------------------------------------------- */
1566
1567 static loff_t ess_llseek(struct file *file, loff_t offset, int origin)
1568 {
1569 return -ESPIPE;
1570 }
1571
1572 /* --------------------------------------------------------------------- */
1573
1574 static int ess_open_mixdev(struct inode *inode, struct file *file)
1575 {
1576 int minor = MINOR(inode->i_rdev);
1577 struct ess_card *card = devs;
1578
1579 while (card && card->dev_mixer != minor)
1580 card = card->next;
1581 if (!card)
1582 return -ENODEV;
1583
1584 file->private_data = card;
1585 MOD_INC_USE_COUNT;
1586 return 0;
1587 }
1588
1589 static int ess_release_mixdev(struct inode *inode, struct file *file)
1590 {
1591 struct ess_card *card = (struct ess_card *)file->private_data;
1592
1593 VALIDATE_CARD(card);
1594
1595 MOD_DEC_USE_COUNT;
1596 return 0;
1597 }
1598
1599 static int ess_ioctl_mixdev(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg)
1600 {
1601 struct ess_card *card = (struct ess_card *)file->private_data;
1602
1603 VALIDATE_CARD(card);
1604
1605 return ac97_mixer_ioctl(card, cmd, arg);
1606 }
1607
1608 static /*const*/ struct file_operations ess_mixer_fops = {
1609 &ess_llseek,
1610 NULL, /* read */
1611 NULL, /* write */
1612 NULL, /* readdir */
1613 NULL, /* poll */
1614 &ess_ioctl_mixdev,
1615 NULL, /* mmap */
1616 &ess_open_mixdev,
1617 NULL, /* flush */
1618 &ess_release_mixdev,
1619 NULL, /* fsync */
1620 NULL, /* fasync */
1621 NULL, /* check_media_change */
1622 NULL, /* revalidate */
1623 NULL, /* lock */
1624 };
1625
1626 /* --------------------------------------------------------------------- */
1627
1628 static int drain_dac(struct ess_state *s, int nonblock)
1629 {
1630 DECLARE_WAITQUEUE(wait,current);
1631 unsigned long flags;
1632 int count, tmo;
1633
1634 if (s->dma_dac.mapped || !s->dma_dac.ready)
1635 return 0;
1636 current->state = TASK_INTERRUPTIBLE;
1637 add_wait_queue(&s->dma_dac.wait, &wait);
1638 for (;;) {
1639 spin_lock_irqsave(&s->lock, flags);
1640 count = s->dma_dac.count;
1641 spin_unlock_irqrestore(&s->lock, flags);
1642 if (count <= 0)
1643 break;
1644 if (signal_pending(current))
1645 break;
1646 if (nonblock) {
1647 remove_wait_queue(&s->dma_dac.wait, &wait);
1648 current->state = TASK_RUNNING;
1649 return -EBUSY;
1650 }
1651 tmo = (count * HZ) / s->ratedac;
1652 tmo >>= sample_shift[(s->fmt >> ESS_CFMT_ASHIFT) & ESS_CFMT_MASK];
1653 if (!schedule_timeout(tmo ? : 1) && tmo)
1654 printk(KERN_DEBUG "maestro: dma timed out??\n");
1655 }
1656 remove_wait_queue(&s->dma_dac.wait, &wait);
1657 current->state = TASK_RUNNING;
1658 if (signal_pending(current))
1659 return -ERESTARTSYS;
1660 return 0;
1661 }
1662
1663 /* --------------------------------------------------------------------- */
1664
1665 static ssize_t ess_read(struct file *file, char *buffer, size_t count, loff_t *ppos)
1666 {
1667 struct ess_state *s = (struct ess_state *)file->private_data;
1668 ssize_t ret;
1669 unsigned long flags;
1670 unsigned swptr;
1671 /* for damned dual players */
1672 int cnt;
1673
1674 VALIDATE_STATE(s);
1675 if (ppos != &file->f_pos)
1676 return -ESPIPE;
1677 if (s->dma_adc.mapped)
1678 return -ENXIO;
1679 if (!s->dma_adc.ready && (ret = prog_dmabuf(s, 1)))
1680 return ret;
1681 if (!access_ok(VERIFY_WRITE, buffer, count))
1682 return -EFAULT;
1683 ret = 0;
1684 #if 0
1685 spin_lock_irqsave(&s->lock, flags);
1686 ess_update_ptr(s);
1687 spin_unlock_irqrestore(&s->lock, flags);
1688 #endif
1689 while (count > 0) {
1690 spin_lock_irqsave(&s->lock, flags);
1691 swptr = s->dma_adc.swptr;
1692 cnt = s->dma_adc.dmasize-swptr;
1693 if (s->dma_adc.count < cnt)
1694 cnt = s->dma_adc.count;
1695 spin_unlock_irqrestore(&s->lock, flags);
1696 if (cnt > count)
1697 cnt = count;
1698 if (cnt <= 0) {
1699 start_adc(s);
1700 if (file->f_flags & O_NONBLOCK)
1701 return ret ? ret : -EAGAIN;
1702 if (!interruptible_sleep_on_timeout(&s->dma_adc.wait, HZ)) {
1703 printk(KERN_DEBUG "maestro: read: chip lockup? dmasz %u fragsz %u count %i hwptr %u swptr %u\n",
1704 s->dma_adc.dmasize, s->dma_adc.fragsize, s->dma_adc.count,
1705 s->dma_adc.hwptr, s->dma_adc.swptr);
1706 stop_adc(s);
1707 spin_lock_irqsave(&s->lock, flags);
1708 set_dmac(s, virt_to_bus(s->dma_adc.rawbuf), s->dma_adc.numfrag << s->dma_adc.fragshift);
1709 /* program enhanced mode registers */
1710 /* FILL ME */
1711 // wrindir(s, SV_CIDMACBASECOUNT1, (s->dma_adc.fragsamples-1) >> 8);
1712 // wrindir(s, SV_CIDMACBASECOUNT0, s->dma_adc.fragsamples-1);
1713 s->dma_adc.count = s->dma_adc.hwptr = s->dma_adc.swptr = 0;
1714 spin_unlock_irqrestore(&s->lock, flags);
1715 }
1716 if (signal_pending(current))
1717 return ret ? ret : -ERESTARTSYS;
1718 continue;
1719 }
1720 if (copy_to_user(buffer, s->dma_adc.rawbuf + swptr, cnt))
1721 return ret ? ret : -EFAULT;
1722 swptr = (swptr + cnt) % s->dma_adc.dmasize;
1723 spin_lock_irqsave(&s->lock, flags);
1724 s->dma_adc.swptr = swptr;
1725 s->dma_adc.count -= cnt;
1726 spin_unlock_irqrestore(&s->lock, flags);
1727 count -= cnt;
1728 buffer += cnt;
1729 ret += cnt;
1730 start_adc(s);
1731 }
1732
1733 return ret;
1734 }
1735
1736 /* god this is gross..*/
1737 int split_stereo(unsigned char *real_buffer,unsigned char *tmp_buffer, int offset,
1738 int count, int bufsize, int mode)
1739 {
1740 /* oh, bother. stereo decoding APU's don't work in 16bit so we
1741 use dual linear decoders. which means we have to hack up stereo
1742 buffer's we're given. yuck.
1743
1744 and we have to be able to work a byte at a time..*/
1745
1746 unsigned char *so,*left,*right;
1747 int i;
1748
1749 so = tmp_buffer;
1750 left = real_buffer + offset;
1751 right = real_buffer + bufsize/2 + offset;
1752
1753 M_printk("writing %d to %p and %p from %p:%d bufs: %d\n",count/2, left,right,real_buffer,offset,bufsize);
1754
1755 if(mode & ESS_CFMT_16BIT) {
1756 for(i=count/4; i ; i--) {
1757 *(right++) = (*(so+2));
1758 *(right++) = (*(so+3));
1759 *(left++) = (*so);
1760 *(left++) = (*(so+1));
1761 so+=4;
1762 }
1763 } else {
1764 for(i=count/2; i ; i--) {
1765 *(right++) = (*(so+1));
1766 *(left++) = (*so);
1767 so+=2;
1768 }
1769 }
1770
1771 return 0;
1772 }
1773
1774 static ssize_t ess_write(struct file *file, const char *buffer, size_t count, loff_t *ppos)
1775 {
1776 struct ess_state *s = (struct ess_state *)file->private_data;
1777 ssize_t ret;
1778 unsigned long flags;
1779 unsigned swptr;
1780 unsigned char *splitbuf = NULL;
1781 int cnt;
1782
1783 VALIDATE_STATE(s);
1784 if (ppos != &file->f_pos)
1785 return -ESPIPE;
1786 if (s->dma_dac.mapped)
1787 return -ENXIO;
1788 if (!s->dma_dac.ready && (ret = prog_dmabuf(s, 0)))
1789 return ret;
1790 if (!access_ok(VERIFY_READ, buffer, count))
1791 return -EFAULT;
1792 /* I wish we could be more clever than this */
1793 if (!(splitbuf = kmalloc(count,GFP_KERNEL)))
1794 return -ENOMEM;
1795 ret = 0;
1796 #if 0
1797 spin_lock_irqsave(&s->lock, flags);
1798 ess_update_ptr(s);
1799 spin_unlock_irqrestore(&s->lock, flags);
1800 #endif
1801 while (count > 0) {
1802 spin_lock_irqsave(&s->lock, flags);
1803
1804 if (s->dma_dac.count < 0) {
1805 s->dma_dac.count = 0;
1806 s->dma_dac.swptr = s->dma_dac.hwptr;
1807 }
1808 swptr = s->dma_dac.swptr;
1809
1810 if(s->fmt & ESS_CFMT_STEREO) {
1811 /* in stereo we have the 'dual' buffers.. */
1812 cnt = ((s->dma_dac.dmasize/2)-swptr)*2;
1813 } else {
1814 cnt = s->dma_dac.dmasize-swptr;
1815 }
1816 if (s->dma_dac.count + cnt > s->dma_dac.dmasize)
1817 cnt = s->dma_dac.dmasize - s->dma_dac.count;
1818
1819 spin_unlock_irqrestore(&s->lock, flags);
1820
1821 if (cnt > count)
1822 cnt = count;
1823
1824 /* our goofball stereo splitter can only deal in mults of 4 */
1825 if (cnt > 0)
1826 cnt &= ~3;
1827
1828 if (cnt <= 0) {
1829 /* buffer is full, wait for it to be played */
1830 start_dac(s);
1831 if (file->f_flags & O_NONBLOCK) {
1832 if(!ret) ret = -EAGAIN;
1833 goto return_free;
1834 }
1835 if (!interruptible_sleep_on_timeout(&s->dma_dac.wait, HZ)) {
1836 printk(KERN_DEBUG "maestro: write: chip lockup? dmasz %u fragsz %u count %i hwptr %u swptr %u\n",
1837 s->dma_dac.dmasize, s->dma_dac.fragsize, s->dma_dac.count,
1838 s->dma_dac.hwptr, s->dma_dac.swptr);
1839 stop_dac(s);
1840 spin_lock_irqsave(&s->lock, flags);
1841 set_dmaa(s, virt_to_bus(s->dma_dac.rawbuf), s->dma_dac.numfrag << s->dma_dac.fragshift);
1842 /* program enhanced mode registers */
1843 // wrindir(s, SV_CIDMAABASECOUNT1, (s->dma_dac.fragsamples-1) >> 8);
1844 // wrindir(s, SV_CIDMAABASECOUNT0, s->dma_dac.fragsamples-1);
1845 /* FILL ME */
1846 s->dma_dac.count = s->dma_dac.hwptr = s->dma_dac.swptr = 0;
1847 spin_unlock_irqrestore(&s->lock, flags);
1848 }
1849 if (signal_pending(current)) {
1850 if (!ret) ret = -ERESTARTSYS;
1851 goto return_free;
1852 }
1853 continue;
1854 }
1855 if(s->fmt & ESS_CFMT_STEREO) {
1856 if (copy_from_user(splitbuf, buffer, cnt)) {
1857 if (!ret) ret = -EFAULT;
1858 goto return_free;
1859 }
1860 split_stereo(s->dma_dac.rawbuf,splitbuf,swptr,cnt,s->dma_dac.dmasize,s->fmt);
1861 } else {
1862 if (copy_from_user(s->dma_dac.rawbuf + swptr, buffer, cnt)) {
1863 if (!ret) ret = -EFAULT;
1864 goto return_free;
1865 }
1866 }
1867
1868 if(s->fmt & ESS_CFMT_STEREO) {
1869 /* again with the weird pointer magic*/
1870 swptr = (swptr + (cnt/2)) % (s->dma_dac.dmasize/2);
1871 } else {
1872 swptr = (swptr + cnt) % s->dma_dac.dmasize;
1873 }
1874 spin_lock_irqsave(&s->lock, flags);
1875 s->dma_dac.swptr = swptr;
1876 s->dma_dac.count += cnt;
1877 s->dma_dac.endcleared = 0;
1878 spin_unlock_irqrestore(&s->lock, flags);
1879 count -= cnt;
1880 buffer += cnt;
1881 ret += cnt;
1882 start_dac(s);
1883 }
1884 return_free:
1885 if (splitbuf) kfree(splitbuf);
1886 return ret;
1887 }
1888
1889 static unsigned int ess_poll(struct file *file, struct poll_table_struct *wait)
1890 {
1891 struct ess_state *s = (struct ess_state *)file->private_data;
1892 unsigned long flags;
1893 unsigned int mask = 0;
1894
1895 VALIDATE_STATE(s);
1896 if (file->f_mode & FMODE_WRITE)
1897 poll_wait(file, &s->dma_dac.wait, wait);
1898 if (file->f_mode & FMODE_READ)
1899 poll_wait(file, &s->dma_adc.wait, wait);
1900 spin_lock_irqsave(&s->lock, flags);
1901 ess_update_ptr(s);
1902 if (file->f_mode & FMODE_READ) {
1903 if (s->dma_adc.count >= (signed)s->dma_adc.fragsize)
1904 mask |= POLLIN | POLLRDNORM;
1905 }
1906 if (file->f_mode & FMODE_WRITE) {
1907 if (s->dma_dac.mapped) {
1908 if (s->dma_dac.count >= (signed)s->dma_dac.fragsize)
1909 mask |= POLLOUT | POLLWRNORM;
1910 } else {
1911 if ((signed)s->dma_dac.dmasize >= s->dma_dac.count + (signed)s->dma_dac.fragsize)
1912 mask |= POLLOUT | POLLWRNORM;
1913 }
1914 }
1915 spin_unlock_irqrestore(&s->lock, flags);
1916 return mask;
1917 }
1918
1919 /* this needs to be fixed to deal with the dualing apus/buffers */
1920 #if 0
1921 static int ess_mmap(struct file *file, struct vm_area_struct *vma)
1922 {
1923 struct ess_state *s = (struct ess_state *)file->private_data;
1924 struct dmabuf *db;
1925 int ret;
1926 unsigned long size;
1927
1928 VALIDATE_STATE(s);
1929 if (vma->vm_flags & VM_WRITE) {
1930 if ((ret = prog_dmabuf(s, 1)) != 0)
1931 return ret;
1932 db = &s->dma_dac;
1933 } else if (vma->vm_flags & VM_READ) {
1934 if ((ret = prog_dmabuf(s, 0)) != 0)
1935 return ret;
1936 db = &s->dma_adc;
1937 } else
1938 return -EINVAL;
1939 if (vma->vm_offset != 0)
1940 return -EINVAL;
1941 size = vma->vm_end - vma->vm_start;
1942 if (size > (PAGE_SIZE << db->buforder))
1943 return -EINVAL;
1944 if (remap_page_range(vma->vm_start, virt_to_phys(db->rawbuf), size, vma->vm_page_prot))
1945 return -EAGAIN;
1946 db->mapped = 1;
1947 return 0;
1948 }
1949 #endif
1950
1951 static int ess_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg)
1952 {
1953 struct ess_state *s = (struct ess_state *)file->private_data;
1954 unsigned long flags;
1955 audio_buf_info abinfo;
1956 count_info cinfo;
1957 int val, mapped, ret;
1958 unsigned char fmtm, fmtd;
1959
1960 VALIDATE_STATE(s);
1961 mapped = ((file->f_mode & FMODE_WRITE) && s->dma_dac.mapped) ||
1962 ((file->f_mode & FMODE_READ) && s->dma_adc.mapped);
1963 switch (cmd) {
1964 case OSS_GETVERSION:
1965 return put_user(SOUND_VERSION, (int *)arg);
1966
1967 case SNDCTL_DSP_SYNC:
1968 if (file->f_mode & FMODE_WRITE)
1969 return drain_dac(s, 0/*file->f_flags & O_NONBLOCK*/);
1970 return 0;
1971
1972 case SNDCTL_DSP_SETDUPLEX:
1973 return 0;
1974
1975 case SNDCTL_DSP_GETCAPS:
1976 return put_user(0/*DSP_CAP_DUPLEX | DSP_CAP_REALTIME | DSP_CAP_TRIGGER | DSP_CAP_MMAP*/, (int *)arg);
1977
1978 case SNDCTL_DSP_RESET:
1979 if (file->f_mode & FMODE_WRITE) {
1980 stop_dac(s);
1981 synchronize_irq();
1982 s->dma_dac.swptr = s->dma_dac.hwptr = s->dma_dac.count = s->dma_dac.total_bytes = 0;
1983 }
1984 if (file->f_mode & FMODE_READ) {
1985 stop_adc(s);
1986 synchronize_irq();
1987 s->dma_adc.swptr = s->dma_adc.hwptr = s->dma_adc.count = s->dma_adc.total_bytes = 0;
1988 }
1989 return 0;
1990
1991 case SNDCTL_DSP_SPEED:
1992 get_user_ret(val, (int *)arg, -EFAULT);
1993 if (val >= 0) {
1994 if (file->f_mode & FMODE_READ) {
1995 stop_adc(s);
1996 s->dma_adc.ready = 0;
1997 set_adc_rate(s, val);
1998 }
1999 if (file->f_mode & FMODE_WRITE) {
2000 stop_dac(s);
2001 s->dma_dac.ready = 0;
2002 set_dac_rate(s, val);
2003 }
2004 }
2005 return put_user((file->f_mode & FMODE_READ) ? s->rateadc : s->ratedac, (int *)arg);
2006
2007 case SNDCTL_DSP_STEREO:
2008 get_user_ret(val, (int *)arg, -EFAULT);
2009 fmtd = 0;
2010 fmtm = ~0;
2011 if (file->f_mode & FMODE_READ) {
2012 stop_adc(s);
2013 s->dma_adc.ready = 0;
2014 if (val)
2015 fmtd |= ESS_CFMT_STEREO << ESS_CFMT_CSHIFT;
2016 else
2017 fmtm &= ~(ESS_CFMT_STEREO << ESS_CFMT_CSHIFT);
2018 }
2019 if (file->f_mode & FMODE_WRITE) {
2020 stop_dac(s);
2021 s->dma_dac.ready = 0;
2022 if (val)
2023 fmtd |= ESS_CFMT_STEREO << ESS_CFMT_ASHIFT;
2024 else
2025 fmtm &= ~(ESS_CFMT_STEREO << ESS_CFMT_ASHIFT);
2026 }
2027 set_fmt(s, fmtm, fmtd);
2028 return 0;
2029
2030 case SNDCTL_DSP_CHANNELS:
2031 get_user_ret(val, (int *)arg, -EFAULT);
2032 if (val != 0) {
2033 fmtd = 0;
2034 fmtm = ~0;
2035 if (file->f_mode & FMODE_READ) {
2036 stop_adc(s);
2037 s->dma_adc.ready = 0;
2038 if (val >= 2)
2039 fmtd |= ESS_CFMT_STEREO << ESS_CFMT_CSHIFT;
2040 else
2041 fmtm &= ~(ESS_CFMT_STEREO << ESS_CFMT_CSHIFT);
2042 }
2043 if (file->f_mode & FMODE_WRITE) {
2044 stop_dac(s);
2045 s->dma_dac.ready = 0;
2046 if (val >= 2)
2047 fmtd |= ESS_CFMT_STEREO << ESS_CFMT_ASHIFT;
2048 else
2049 fmtm &= ~(ESS_CFMT_STEREO << ESS_CFMT_ASHIFT);
2050 }
2051 set_fmt(s, fmtm, fmtd);
2052 }
2053 return put_user((s->fmt & ((file->f_mode & FMODE_READ) ? (ESS_CFMT_STEREO << ESS_CFMT_CSHIFT)
2054 : (ESS_CFMT_STEREO << ESS_CFMT_ASHIFT))) ? 2 : 1, (int *)arg);
2055
2056 case SNDCTL_DSP_GETFMTS: /* Returns a mask */
2057 return put_user(AFMT_S8|AFMT_S16_LE, (int *)arg);
2058
2059 case SNDCTL_DSP_SETFMT: /* Selects ONE fmt*/
2060 get_user_ret(val, (int *)arg, -EFAULT);
2061 if (val != AFMT_QUERY) {
2062 fmtd = 0;
2063 fmtm = ~0;
2064 if (file->f_mode & FMODE_READ) {
2065 stop_adc(s);
2066 s->dma_adc.ready = 0;
2067 if (val == AFMT_S16_LE)
2068 fmtd |= ESS_CFMT_16BIT << ESS_CFMT_CSHIFT;
2069 else
2070 fmtm &= ~(ESS_CFMT_16BIT << ESS_CFMT_CSHIFT);
2071 }
2072 if (file->f_mode & FMODE_WRITE) {
2073 stop_dac(s);
2074 s->dma_dac.ready = 0;
2075 if (val == AFMT_S16_LE)
2076 fmtd |= ESS_CFMT_16BIT << ESS_CFMT_ASHIFT;
2077 else
2078 fmtm &= ~(ESS_CFMT_16BIT << ESS_CFMT_ASHIFT);
2079 }
2080 set_fmt(s, fmtm, fmtd);
2081 }
2082 return put_user((s->fmt & ((file->f_mode & FMODE_READ) ?
2083 (ESS_CFMT_16BIT << ESS_CFMT_CSHIFT)
2084 : (ESS_CFMT_16BIT << ESS_CFMT_ASHIFT))) ?
2085 AFMT_S16_LE :
2086 AFMT_S8,
2087 (int *)arg);
2088
2089 case SNDCTL_DSP_POST:
2090 return 0;
2091
2092 case SNDCTL_DSP_GETTRIGGER:
2093 val = 0;
2094 if (file->f_mode & FMODE_READ && s->enable & ESS_ENABLE_RE)
2095 val |= PCM_ENABLE_INPUT;
2096 if (file->f_mode & FMODE_WRITE && s->enable & ESS_ENABLE_PE)
2097 val |= PCM_ENABLE_OUTPUT;
2098 return put_user(val, (int *)arg);
2099
2100 case SNDCTL_DSP_SETTRIGGER:
2101 get_user_ret(val, (int *)arg, -EFAULT);
2102 if (file->f_mode & FMODE_READ) {
2103 if (val & PCM_ENABLE_INPUT) {
2104 if (!s->dma_adc.ready && (ret = prog_dmabuf(s, 1)))
2105 return ret;
2106 start_adc(s);
2107 } else
2108 stop_adc(s);
2109 }
2110 if (file->f_mode & FMODE_WRITE) {
2111 if (val & PCM_ENABLE_OUTPUT) {
2112 if (!s->dma_dac.ready && (ret = prog_dmabuf(s, 0)))
2113 return ret;
2114 start_dac(s);
2115 } else
2116 stop_dac(s);
2117 }
2118 return 0;
2119
2120 case SNDCTL_DSP_GETOSPACE:
2121 if (!(file->f_mode & FMODE_WRITE))
2122 return -EINVAL;
2123 if (!(s->enable & ESS_ENABLE_PE) && (val = prog_dmabuf(s, 0)) != 0)
2124 return val;
2125 spin_lock_irqsave(&s->lock, flags);
2126 ess_update_ptr(s);
2127 abinfo.fragsize = s->dma_dac.fragsize;
2128 abinfo.bytes = s->dma_dac.dmasize - s->dma_dac.count;
2129 abinfo.fragstotal = s->dma_dac.numfrag;
2130 abinfo.fragments = abinfo.bytes >> s->dma_dac.fragshift;
2131 spin_unlock_irqrestore(&s->lock, flags);
2132 return copy_to_user((void *)arg, &abinfo, sizeof(abinfo)) ? -EFAULT : 0;
2133
2134 case SNDCTL_DSP_GETISPACE:
2135 if (!(file->f_mode & FMODE_READ))
2136 return -EINVAL;
2137 if (!(s->enable & ESS_ENABLE_RE) && (val = prog_dmabuf(s, 1)) != 0)
2138 return val;
2139 spin_lock_irqsave(&s->lock, flags);
2140 ess_update_ptr(s);
2141 abinfo.fragsize = s->dma_adc.fragsize;
2142 abinfo.bytes = s->dma_adc.count;
2143 abinfo.fragstotal = s->dma_adc.numfrag;
2144 abinfo.fragments = abinfo.bytes >> s->dma_adc.fragshift;
2145 spin_unlock_irqrestore(&s->lock, flags);
2146 return copy_to_user((void *)arg, &abinfo, sizeof(abinfo)) ? -EFAULT : 0;
2147
2148 case SNDCTL_DSP_NONBLOCK:
2149 file->f_flags |= O_NONBLOCK;
2150 return 0;
2151
2152 case SNDCTL_DSP_GETODELAY:
2153 if (!(file->f_mode & FMODE_WRITE))
2154 return -EINVAL;
2155 spin_lock_irqsave(&s->lock, flags);
2156 ess_update_ptr(s);
2157 val = s->dma_dac.count;
2158 spin_unlock_irqrestore(&s->lock, flags);
2159 return put_user(val, (int *)arg);
2160
2161 case SNDCTL_DSP_GETIPTR:
2162 if (!(file->f_mode & FMODE_READ))
2163 return -EINVAL;
2164 spin_lock_irqsave(&s->lock, flags);
2165 ess_update_ptr(s);
2166 cinfo.bytes = s->dma_adc.total_bytes;
2167 cinfo.blocks = s->dma_adc.count >> s->dma_adc.fragshift;
2168 cinfo.ptr = s->dma_adc.hwptr;
2169 if (s->dma_adc.mapped)
2170 s->dma_adc.count &= s->dma_adc.fragsize-1;
2171 spin_unlock_irqrestore(&s->lock, flags);
2172 return copy_to_user((void *)arg, &cinfo, sizeof(cinfo));
2173
2174 case SNDCTL_DSP_GETOPTR:
2175 if (!(file->f_mode & FMODE_WRITE))
2176 return -EINVAL;
2177 spin_lock_irqsave(&s->lock, flags);
2178 ess_update_ptr(s);
2179 cinfo.bytes = s->dma_dac.total_bytes;
2180 cinfo.blocks = s->dma_dac.count >> s->dma_dac.fragshift;
2181 cinfo.ptr = s->dma_dac.hwptr;
2182 if (s->dma_dac.mapped)
2183 s->dma_dac.count &= s->dma_dac.fragsize-1;
2184 spin_unlock_irqrestore(&s->lock, flags);
2185 return copy_to_user((void *)arg, &cinfo, sizeof(cinfo));
2186
2187 case SNDCTL_DSP_GETBLKSIZE:
2188 if (file->f_mode & FMODE_WRITE) {
2189 if ((val = prog_dmabuf(s, 0)))
2190 return val;
2191 return put_user(s->dma_dac.fragsize, (int *)arg);
2192 }
2193 if ((val = prog_dmabuf(s, 1)))
2194 return val;
2195 return put_user(s->dma_adc.fragsize, (int *)arg);
2196
2197 case SNDCTL_DSP_SETFRAGMENT:
2198 get_user_ret(val, (int *)arg, -EFAULT);
2199 if (file->f_mode & FMODE_READ) {
2200 s->dma_adc.ossfragshift = val & 0xffff;
2201 s->dma_adc.ossmaxfrags = (val >> 16) & 0xffff;
2202 if (s->dma_adc.ossfragshift < 4)
2203 s->dma_adc.ossfragshift = 4;
2204 if (s->dma_adc.ossfragshift > 15)
2205 s->dma_adc.ossfragshift = 15;
2206 if (s->dma_adc.ossmaxfrags < 4)
2207 s->dma_adc.ossmaxfrags = 4;
2208 }
2209 if (file->f_mode & FMODE_WRITE) {
2210 s->dma_dac.ossfragshift = val & 0xffff;
2211 s->dma_dac.ossmaxfrags = (val >> 16) & 0xffff;
2212 if (s->dma_dac.ossfragshift < 4)
2213 s->dma_dac.ossfragshift = 4;
2214 if (s->dma_dac.ossfragshift > 15)
2215 s->dma_dac.ossfragshift = 15;
2216 if (s->dma_dac.ossmaxfrags < 4)
2217 s->dma_dac.ossmaxfrags = 4;
2218 }
2219 return 0;
2220
2221 case SNDCTL_DSP_SUBDIVIDE:
2222 if ((file->f_mode & FMODE_READ && s->dma_adc.subdivision) ||
2223 (file->f_mode & FMODE_WRITE && s->dma_dac.subdivision))
2224 return -EINVAL;
2225 get_user_ret(val, (int *)arg, -EFAULT);
2226 if (val != 1 && val != 2 && val != 4)
2227 return -EINVAL;
2228 if (file->f_mode & FMODE_READ)
2229 s->dma_adc.subdivision = val;
2230 if (file->f_mode & FMODE_WRITE)
2231 s->dma_dac.subdivision = val;
2232 return 0;
2233
2234 case SOUND_PCM_READ_RATE:
2235 return put_user((file->f_mode & FMODE_READ) ? s->rateadc : s->ratedac, (int *)arg);
2236
2237 case SOUND_PCM_READ_CHANNELS:
2238 return put_user((s->fmt & ((file->f_mode & FMODE_READ) ? (ESS_CFMT_STEREO << ESS_CFMT_CSHIFT)
2239 : (ESS_CFMT_STEREO << ESS_CFMT_ASHIFT))) ? 2 : 1, (int *)arg);
2240
2241 case SOUND_PCM_READ_BITS:
2242 return put_user((s->fmt & ((file->f_mode & FMODE_READ) ? (ESS_CFMT_16BIT << ESS_CFMT_CSHIFT)
2243 : (ESS_CFMT_16BIT << ESS_CFMT_ASHIFT))) ? 16 : 8, (int *)arg);
2244
2245 case SOUND_PCM_WRITE_FILTER:
2246 case SNDCTL_DSP_SETSYNCRO:
2247 case SOUND_PCM_READ_FILTER:
2248 return -EINVAL;
2249
2250 }
2251 // return mixer_ioctl(s, cmd, arg);
2252 return -EINVAL;
2253 }
2254
2255 static int ess_open(struct inode *inode, struct file *file)
2256 {
2257 int minor = MINOR(inode->i_rdev);
2258 struct ess_card *c = devs;
2259 struct ess_state *s = NULL, *sp;
2260 int i;
2261 unsigned char fmtm = ~0, fmts = 0;
2262
2263 /*
2264 * Scan the cards and find the channel. We only
2265 * do this at open time so it is ok
2266 */
2267
2268 while (c!=NULL)
2269 {
2270 for(i=0;i<8;i++)
2271 {
2272 sp=&c->channels[i];
2273 if(sp->dev_audio < 0)
2274 continue;
2275 if((sp->dev_audio ^ minor) & ~0xf)
2276 continue;
2277 s=sp;
2278 }
2279 c=c->next;
2280 }
2281
2282 if (!s)
2283 return -ENODEV;
2284
2285 VALIDATE_STATE(s);
2286 file->private_data = s;
2287 /* wait for device to become free */
2288 down(&s->open_sem);
2289 while (s->open_mode & file->f_mode) {
2290 if (file->f_flags & O_NONBLOCK) {
2291 up(&s->open_sem);
2292 return -EWOULDBLOCK;
2293 }
2294 up(&s->open_sem);
2295 interruptible_sleep_on(&s->open_wait);
2296 if (signal_pending(current))
2297 return -ERESTARTSYS;
2298 down(&s->open_sem);
2299 }
2300 if (file->f_mode & FMODE_READ) {
2301 fmtm &= ~((ESS_CFMT_STEREO | ESS_CFMT_16BIT) << ESS_CFMT_CSHIFT);
2302 if ((minor & 0xf) == SND_DEV_DSP16)
2303 fmts |= ESS_CFMT_16BIT << ESS_CFMT_CSHIFT;
2304 s->dma_adc.ossfragshift = s->dma_adc.ossmaxfrags = s->dma_adc.subdivision = 0;
2305 set_adc_rate(s, 8000);
2306 }
2307 if (file->f_mode & FMODE_WRITE) {
2308 fmtm &= ~((ESS_CFMT_STEREO | ESS_CFMT_16BIT) << ESS_CFMT_ASHIFT);
2309 if ((minor & 0xf) == SND_DEV_DSP16)
2310 fmts |= ESS_CFMT_16BIT << ESS_CFMT_ASHIFT;
2311 s->dma_dac.ossfragshift = s->dma_dac.ossmaxfrags = s->dma_dac.subdivision = 0;
2312 set_dac_rate(s, 8000);
2313 }
2314 set_fmt(s, fmtm, fmts);
2315 s->open_mode |= file->f_mode & (FMODE_READ | FMODE_WRITE);
2316 start_bob(s);
2317 up(&s->open_sem);
2318 MOD_INC_USE_COUNT;
2319 return 0;
2320 }
2321
2322 static int ess_release(struct inode *inode, struct file *file)
2323 {
2324 struct ess_state *s = (struct ess_state *)file->private_data;
2325
2326 VALIDATE_STATE(s);
2327 if (file->f_mode & FMODE_WRITE)
2328 drain_dac(s, file->f_flags & O_NONBLOCK);
2329 down(&s->open_sem);
2330 if (file->f_mode & FMODE_WRITE) {
2331 stop_dac(s);
2332 dealloc_dmabuf(&s->dma_dac);
2333 }
2334 if (file->f_mode & FMODE_READ) {
2335 stop_adc(s);
2336 dealloc_dmabuf(&s->dma_adc);
2337 }
2338 s->open_mode &= (~file->f_mode) & (FMODE_READ|FMODE_WRITE);
2339 stop_bob(s);
2340 up(&s->open_sem);
2341 wake_up(&s->open_wait);
2342 MOD_DEC_USE_COUNT;
2343 return 0;
2344 }
2345
2346 static /*const*/ struct file_operations ess_audio_fops = {
2347 &ess_llseek,
2348 &ess_read,
2349 &ess_write,
2350 NULL, /* readdir */
2351 &ess_poll,
2352 &ess_ioctl,
2353 NULL, /* XXX &ess_mmap, */
2354 &ess_open,
2355 NULL, /* flush */
2356 &ess_release,
2357 NULL, /* fsync */
2358 NULL, /* fasync */
2359 NULL, /* check_media_change */
2360 NULL, /* revalidate */
2361 NULL, /* lock */
2362 };
2363
2364
2365 /* --------------------------------------------------------------------- */
2366
2367 /* XXX get rid of this
2368 * maximum number of devices
2369 */
2370 #define NR_DEVICE 4
2371
2372 /* --------------------------------------------------------------------- */
2373
2374 static int maestro_install(struct pci_dev *pcidev, int card_type, int index)
2375 {
2376 u16 w;
2377 u32 n;
2378 int iobase;
2379 int i;
2380 struct ess_card *card;
2381 struct ess_state *ess;
2382 int apu;
2383 int num = 0;
2384
2385 iobase = pcidev->resource[0].start;
2386
2387 card = kmalloc(sizeof(struct ess_card), GFP_KERNEL);
2388 if(card == NULL)
2389 {
2390 printk(KERN_WARNING "maestro: out of memory\n");
2391 return 0;
2392 }
2393
2394 memset(card, 0, sizeof(*card));
2395
2396 card->iobase = iobase;
2397 card->card_type = card_type;
2398 card->irq = pcidev->irq;
2399 card->next = devs;
2400 card->magic = ESS_CARD_MAGIC;
2401 devs = card;
2402
2403 /* init our 8 groups of 4 apus */
2404 for(i=0;i<8;i++)
2405 {
2406 struct ess_state *s=&card->channels[i];
2407
2408 s->card = card;
2409 init_waitqueue_head(&s->dma_adc.wait);
2410 init_waitqueue_head(&s->dma_dac.wait);
2411 init_waitqueue_head(&s->open_wait);
2412 init_MUTEX(&s->open_sem);
2413 s->magic = ESS_STATE_MAGIC;
2414
2415 s->apu[0] = 4*i;
2416 s->apu[1] = (4*i)+1;
2417 s->apu[2] = (4*i)+2;
2418 s->apu[3] = (4*i)+3;
2419
2420 if(s->dma_adc.ready || s->dma_dac.ready || s->dma_adc.rawbuf)
2421 printk("BOTCH!\n");
2422 /* register devices */
2423 if ((s->dev_audio = register_sound_dsp(&ess_audio_fops, -1)) < 0)
2424 break;
2425 }
2426
2427 num = i;
2428
2429 /* clear the rest if we ran out of slots to register */
2430 for(;i<8;i++)
2431 {
2432 struct ess_state *s=&card->channels[i];
2433 s->dev_audio = -1;
2434 }
2435
2436 ess = &card->channels[0];
2437
2438 /*
2439 * Ok card ready. Begin setup proper
2440 */
2441
2442 printk(KERN_INFO "maestro: Configuring %s at 0x%04X\n", card_names[card_type], iobase);
2443
2444 /*
2445 * Disable ACPI
2446 */
2447
2448 pci_write_config_dword(pcidev, 0x54, 0x00000000);
2449 pci_write_config_dword(pcidev, 0x56, 0x00000000);
2450
2451 /*
2452 * Use TDMA for now. TDMA works on all boards, so while its
2453 * not the most efficient its the simplest.
2454 */
2455
2456 pci_read_config_word(pcidev, 0x50, &w);
2457
2458 /* Clear DMA bits */
2459 w&=~(1<<10|1<<9|1<<8);
2460
2461 /* TDMA on */
2462 w|=(1<<8);
2463
2464 /* XXX do we care about these two ? */
2465 /*
2466 * MPU at 330
2467 */
2468
2469 w&=~((1<<4)|(1<<3));
2470
2471 /*
2472 * SB at 0x220
2473 */
2474
2475 w&=~(1<<2);
2476
2477 #if 0 /* huh? its sub decode.. */
2478
2479 /*
2480 * Reserved write as 0
2481 */
2482
2483 w&=~(1<<1);
2484 #endif
2485
2486 /*
2487 * Some of these are undocumented bits
2488 */
2489
2490 w&=~(1<<13)|(1<<14); /* PIC Snoop mode bits */
2491 w&=~(1<<11); /* Safeguard off */
2492 w|= (1<<7); /* Posted write */
2493 w|= (1<<6); /* ISA timing on */
2494 w&=~(1<<1); /* Subtractive decode off */
2495 /* XXX huh? claims to be reserved.. */
2496 w&=~(1<<5); /* Don't swap left/right */
2497
2498 pci_write_config_word(pcidev, 0x50, w);
2499
2500 pci_read_config_word(pcidev, 0x52, &w);
2501 w&=~(1<<15); /* Turn off internal clock multiplier */
2502 /* XXX how do we know which to use? */
2503 w&=~(1<<14); /* External clock */
2504
2505 w&=~(1<<7); /* HWV off */
2506 w&=~(1<<6); /* Debounce off */
2507 w&=~(1<<5); /* GPIO 4:5 */
2508 w&=~(1<<4); /* Disconnect from the CHI */
2509 w&=~(1<<3); /* IDMA off (undocumented) */
2510 w&=~(1<<2); /* MIDI fix off (undoc) */
2511 w&=~(1<<1); /* reserved, always write 0 */
2512 w&=~(1<<0); /* IRQ to ISA off (undoc) */
2513 pci_write_config_word(pcidev, 0x52, w);
2514
2515 /*
2516 * DDMA off
2517 */
2518
2519 pci_read_config_word(pcidev, 0x60, &w);
2520 w&=~(1<<0);
2521 pci_write_config_word(pcidev, 0x60, w);
2522
2523 /*
2524 * Legacy mode
2525 */
2526
2527 pci_read_config_word(pcidev, 0x40, &w);
2528 w|=(1<<15); /* legacy decode off */
2529 w&=~(1<<14); /* Disable SIRQ */
2530 w&=~(0x1f); /* disable mpu irq/io, game port, fm, SB */
2531
2532 pci_write_config_word(pcidev, 0x40, w);
2533
2534 sound_reset(iobase);
2535
2536 /*
2537 * Reset the CODEC
2538 */
2539
2540 maestro_ac97_reset(iobase);
2541
2542 /*
2543 * Ring Bus Setup
2544 */
2545
2546 n=inl(iobase+0x34);
2547 n&=~0xF000;
2548 n|=12<<12; /* Direct Sound, Stereo */
2549
2550 n=inl(iobase+0x34);
2551 n&=~0x0F00; /* Modem off */
2552 outl(n, iobase+0x34);
2553
2554 n=inl(iobase+0x34);
2555 n&=~0x00F0;
2556 n|=9<<4; /* DAC, Stereo */
2557 outl(n, iobase+0x34);
2558
2559 n=inl(iobase+0x34);
2560 n&=~0x000F; /* ASSP off */
2561 outl(n, iobase+0x34);
2562
2563
2564 n=inl(iobase+0x34);
2565 n|=(1<<29); /* Enable ring bus */
2566 outl(n, iobase+0x34);
2567
2568
2569 n=inl(iobase+0x34);
2570 n|=(1<<28); /* Enable serial bus */
2571 outl(n, iobase+0x34);
2572
2573 n=inl(iobase+0x34);
2574 n&=~0x00F00000; /* MIC off */
2575 outl(n, iobase+0x34);
2576
2577 n=inl(iobase+0x34);
2578 n&=~0x000F0000; /* I2S off */
2579 outl(n, iobase+0x34);
2580
2581 w=inw(iobase+0x18);
2582 w&=~(1<<7); /* ClkRun off */
2583 outw(w, iobase+0x18);
2584
2585 w=inw(iobase+0x18);
2586 w&=~(1<<6); /* Harpo off */
2587 outw(w, iobase+0x18);
2588
2589 w=inw(iobase+0x18);
2590 w&=~(1<<4); /* ASSP irq off */
2591 outw(w, iobase+0x18);
2592
2593 w=inw(iobase+0x18);
2594 w&=~(1<<3); /* ISDN irq off */
2595 outw(w, iobase+0x18);
2596
2597 w=inw(iobase+0x18);
2598 w|=(1<<2); /* Direct Sound IRQ on */
2599 outw(w, iobase+0x18);
2600
2601 w=inw(iobase+0x18);
2602 w&=~(1<<1); /* MPU401 IRQ off */
2603 outw(w, iobase+0x18);
2604
2605 w=inw(iobase+0x18);
2606 w|=(1<<0); /* SB IRQ on */
2607 outw(w, iobase+0x18);
2608
2609
2610 outb(0, iobase+0xA4);
2611 outb(3, iobase+0xA2);
2612 outb(0, iobase+0xA6);
2613
2614 for(apu=0;apu<16;apu++)
2615 {
2616 /* Write 0 into the buffer area 0x1E0->1EF */
2617 outw(0x01E0+apu, 0x10+iobase);
2618 outw(0x0000, 0x12+iobase);
2619
2620 /*
2621 * The 1.10 test program seem to write 0 into the buffer area
2622 * 0x1D0-0x1DF too.
2623 */
2624 outw(0x01D0+apu, 0x10+iobase);
2625 outw(0x0000, 0x12+iobase);
2626 }
2627
2628 #if 1
2629 wave_set_register(ess, IDR7_WAVE_ROMRAM,
2630 (wave_get_register(ess, IDR7_WAVE_ROMRAM)&0xFF00));
2631 wave_set_register(ess, IDR7_WAVE_ROMRAM,
2632 wave_get_register(ess, IDR7_WAVE_ROMRAM)|0x100);
2633 wave_set_register(ess, IDR7_WAVE_ROMRAM,
2634 wave_get_register(ess, IDR7_WAVE_ROMRAM)&~0x200);
2635 wave_set_register(ess, IDR7_WAVE_ROMRAM,
2636 wave_get_register(ess, IDR7_WAVE_ROMRAM)|~0x400);
2637 #else
2638 maestro_write(ess, IDR7_WAVE_ROMRAM,
2639 (maestro_read(ess, IDR7_WAVE_ROMRAM)&0xFF00));
2640 maestro_write(ess, IDR7_WAVE_ROMRAM,
2641 maestro_read(ess, IDR7_WAVE_ROMRAM)|0x100);
2642 maestro_write(ess, IDR7_WAVE_ROMRAM,
2643 maestro_read(ess, IDR7_WAVE_ROMRAM)&~0x200);
2644 maestro_write(ess, IDR7_WAVE_ROMRAM,
2645 maestro_read(ess, IDR7_WAVE_ROMRAM)|0x400);
2646 #endif
2647
2648 maestro_write(ess, IDR2_CRAM_DATA, 0x0000);
2649 maestro_write(ess, 0x08, 0xB004);
2650 /* Now back to the DirectSound stuff */
2651 maestro_write(ess, 0x09, 0x001B);
2652 maestro_write(ess, 0x0A, 0x8000);
2653 maestro_write(ess, 0x0B, 0x3F37);
2654 maestro_write(ess, 0x0C, 0x0098);
2655
2656 maestro_write(ess, 0x0C,
2657 (maestro_read(ess, 0x0C)&~0xF000)|0x8000);
2658 maestro_write(ess, 0x0C,
2659 (maestro_read(ess, 0x0C)&~0x0F00)|0x0500);
2660
2661 maestro_write(ess, 0x0D, 0x7632);
2662
2663 /* Wave cache control on - test off, sg off,
2664 enable, enable extra chans 1Mb */
2665
2666 outw(inw(0x14+iobase)|(1<<8),0x14+iobase);
2667 outw(inw(0x14+iobase)&0xFE03,0x14+iobase);
2668 outw((inw(0x14+iobase)&0xFFFC), 0x14+iobase);
2669 outw(inw(0x14+iobase)|(1<<7),0x14+iobase);
2670
2671 outw(0xA1A0, 0x14+iobase); /* 0300 ? */
2672
2673 if(maestro_ac97_get(iobase, 0x00)==0x0080)
2674 {
2675 maestro_pt101_init(iobase);
2676 }
2677 else
2678 {
2679 maestro_ac97_init(iobase);
2680 card->mix.supported_mixers = AC97_SUPPORTED_MASK;
2681 card->mix.stereo_mixers = AC97_STEREO_MASK;
2682 card->mix.record_sources = AC97_RECORD_MASK;
2683 card->mix.read_mixer = ac97_read_mixer;
2684 card->mix.write_mixer = ac97_write_mixer;
2685 card->mix.recmask_io = ac97_recmask_io;
2686
2687 if ((card->dev_mixer = register_sound_mixer(&ess_mixer_fops, -1)) < 0)
2688 printk("maestro: couldn't register mixer!\n");
2689 }
2690
2691 /* Now clear the channel data */
2692 for(apu=0;apu<64;apu++)
2693 {
2694 for(w=0;w<0x0E;w++)
2695 apu_set_register(ess, apu|ESS_CHAN_HARD, w, 0);
2696 }
2697
2698 if(request_irq(card->irq, ess_interrupt, SA_SHIRQ, card_names[card_type], card))
2699 {
2700 printk(KERN_ERR "maestro: unable to allocate irq %d,\n", card->irq);
2701 return 0;
2702 }
2703
2704 // ess_play_test(ess);
2705 printk("maestro: %d channels configured.\n", num);
2706 return 1;
2707 }
2708
2709 #ifdef MODULE
2710
2711 int __init init_module(void)
2712 #else
2713 int __init init_maestro(void)
2714 #endif
2715 {
2716 struct pci_dev *pcidev = NULL;
2717 int index = 0;
2718
2719 if (!pci_present()) /* No PCI bus in this machine! */
2720 return -ENODEV;
2721 printk(KERN_INFO "maestro: version " DRIVER_VERSION " time " __TIME__ " " __DATE__ "\n");
2722
2723 pcidev = NULL;
2724
2725 /*
2726 * Find the ESS Maestro 2.
2727 */
2728
2729 while((pcidev = pci_find_device(PCI_VENDOR_ESS, PCI_DEVICE_ID_ESS_ESS1968, pcidev))!=NULL)
2730 {
2731 index+=maestro_install(pcidev, TYPE_MAESTRO2, index);
2732 if(index == NR_DEVICE)
2733 return index;
2734 }
2735
2736 /*
2737 * Find the ESS Maestro 2E
2738 */
2739
2740 while((pcidev = pci_find_device(PCI_VENDOR_ESS, PCI_DEVICE_ID_ESS_ESS1978, pcidev))!=NULL)
2741 {
2742 index+=maestro_install(pcidev, TYPE_MAESTRO2E, index);
2743 if(index == NR_DEVICE)
2744 return index;
2745 }
2746
2747 /*
2748 * ESS Maestro 1
2749 */
2750
2751 while((pcidev = pci_find_device(PCI_VENDOR_ESS_OLD, PCI_DEVICE_ID_ESS_ESS0100, pcidev))!=NULL)
2752 {
2753 index+=maestro_install(pcidev, TYPE_MAESTRO, index);
2754 if(index == NR_DEVICE)
2755 return index;
2756 }
2757 if(index==0)
2758 return -ENODEV;
2759 return 0;
2760 }
2761
2762 /* --------------------------------------------------------------------- */
2763
2764 #ifdef MODULE
2765
2766 MODULE_AUTHOR("Alan Cox <alan@redhat.com>");
2767 MODULE_DESCRIPTION("ESS Maestro Driver");
2768 #ifdef M_DEBUG
2769 MODULE_PARM(debug,"i");
2770 #endif
2771
2772 void cleanup_module(void)
2773 {
2774 struct ess_card *s;
2775
2776 while ((s = devs)) {
2777 int i;
2778 devs = devs->next;
2779 // ess_play_test(&s->channels[0]);
2780 #ifndef ESS_HW_TIMER
2781 kill_bob(&s->channels[0]);
2782 #else
2783 stop_bob(&s->channels[0]);
2784 #endif
2785 // outb(~0, s->ioenh + SV_CODEC_INTMASK); /* disable ints */
2786 // synchronize_irq();
2787 // inb(s->ioenh + SV_CODEC_STATUS); /* ack interrupts */
2788 // wrindir(s, SV_CIENABLE, 0); /* disable DMAA and DMAC */
2789 //outb(0, s->iodmaa + SV_DMA_RESET);
2790 //outb(0, s->iodmac + SV_DMA_RESET);
2791 free_irq(s->irq, s);
2792 unregister_sound_mixer(s->dev_mixer);
2793 for(i=0;i<8;i++)
2794 {
2795 struct ess_state *ess = &s->channels[i];
2796 if(ess->dev_audio != -1)
2797 unregister_sound_dsp(ess->dev_audio);
2798 }
2799 kfree(s);
2800 }
2801 M_printk("maestro: unloading\n");
2802 }
2803
2804 #endif /* MODULE */
2805
2806 #if 0
2807 /*============================================================================
2808 * ex-code that we're not using anymore..
2809 *============================================================================
2810 */
2811 /*
2812 * The ASSP is fortunately not double indexed
2813 */
2814
2815 static void assp_set_register(int ioaddr, u32 reg, u32 value)
2816 {
2817 unsigned long flags;
2818
2819 save_flags(flags);
2820 cli();
2821 outl(reg, ioaddr+0x80);
2822 outl(value, ioaddr+0x84);
2823 restore_flags(flags);
2824 }
2825
2826 static u32 assp_get_register(int ioaddr, u32 reg)
2827 {
2828 unsigned long flags;
2829 u32 value;
2830
2831 save_flags(flags);
2832 cli();
2833 outl(reg, ioaddr+0x80);
2834 value=inl(ioaddr+0x84);
2835 restore_flags(flags);
2836
2837 return value;
2838 }
2839
2840 /* the ASP is basically a DSP that one can dma instructions
2841 into. it can do things like surround encoding or
2842 fm synth in sb emul mode. It is highly proprietary
2843 and the ESS dudes are none too excited about telling
2844 us about it. so screw it, we'll just turn it off and
2845 not bother with it. Its not needed for apu/dac work. */
2846
2847
2848 static void asp_load(int ioaddr, u16 l, u16 h, u16 *data, int len)
2849 {
2850 int i;
2851 outw(l, ioaddr+0x80);
2852 outw(h, ioaddr+0x82);
2853 for(i=0;i<len;i++)
2854 outw(*data++, ioaddr+0x84);
2855 }
2856
2857 static void asp_memset(int ioaddr, u16 l, u16 h, u16 v, int len)
2858 {
2859 int i;
2860 outw(l, ioaddr+0x80);
2861 outw(h, ioaddr+0x82);
2862 for(i=0;i<len;i++)
2863 outw(v, ioaddr+0x84);
2864 }
2865
2866 /*
2867 * Load a code table into the ASP.
2868 */
2869
2870 #define ASSP_LOAD_PROGRAM 0x02
2871 #define ASSP_LOAD_DATA 0x03
2872
2873 static void load_tables(int iobase)
2874 {
2875 outb(0x00, ESS_SETUP_A4+iobase); /* start ASSP programming */
2876
2877 asp_load(iobase, 0x0, ASSP_LOAD_PROGRAM, asp_block_0,
2878 sizeof(asp_block_0)/2);
2879
2880 asp_load(iobase, 0x0800, ASSP_LOAD_PROGRAM,
2881 asp_block_1, sizeof(asp_block_1)/2);
2882
2883 asp_memset(iobase, 0x1000, ASSP_LOAD_DATA, 0, 1024);
2884
2885 /*
2886 * At page 25 of the Maestro-2E data sheet, Table 7, there is a layout of the
2887 * ASSP memory mapping that describe the 0x2000-0x23FF as a data area.
2888 * The 1.10 version of the test code load 0x3B4 words of data into this area.
2889 * I have grabbed the data with hexdump and inserted them into this code.
2890 */
2891 asp_load(iobase, 0x2000, ASSP_LOAD_DATA, asp_block_4,
2892 sizeof(asp_block_4)/2);
2893
2894 asp_memset(iobase, 0x11BC, ASSP_LOAD_DATA, 0x18, 36);
2895
2896 asp_load(iobase, 0x13DC, ASSP_LOAD_DATA, asp_block_2,
2897 sizeof(asp_block_2)/2);
2898
2899 asp_load(iobase, 0x1300, ASSP_LOAD_DATA, asp_block_3,
2900 sizeof(asp_block_3)/2);
2901
2902 outb(0x41, ESS_SETUP_A4+iobase); /* stop programming and run ASSP */
2903 }
2904 /*
2905 * Do not use the main maestro_reset. it is known
2906 * to leave certain chips in an unstable state.
2907 * best to just reset the direct sound (apus) and
2908 * assp pieces seperately.
2909 */
2910
2911 static void maestro_reset(int ioaddr)
2912 {
2913 outw(0x8000, 0x18+ioaddr);
2914 udelay(10);
2915 outw(0x0000, 0x18+ioaddr);
2916 udelay(10);
2917 }
2918 #endif
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