arch/sparc64/math-emu/math.c

   1 /* $Id: math.c,v 1.10 1999/08/13 16:02:06 jj Exp $
   2  * arch/sparc64/math-emu/math.c
   3  *
   4  * Copyright (C) 1997,1999 Jakub Jelinek (jj@ultra.linux.cz)
   5  * Copyright (C) 1999 David S. Miller (davem@redhat.com)
   6  *
   7  * Emulation routines originate from soft-fp package, which is part
   8  * of glibc and has appropriate copyrights in it.
   9  */
  10
  11 #include <linux/types.h>
  12 #include <linux/sched.h>
  13
  14 #include <asm/fpumacro.h>
  15 #include <asm/ptrace.h>
  16 #include <asm/uaccess.h>
  17
  18 #include "sfp-util.h"
  19 #include "soft-fp.h"
  20 #include "single.h"
  21 #include "double.h"
  22 #include "quad.h"
  23
  24 /* QUAD - ftt == 3 */
  25 #define FMOVQ   0x003
  26 #define FNEGQ   0x007
  27 #define FABSQ   0x00b
  28 #define FSQRTQ  0x02b
  29 #define FADDQ   0x043
  30 #define FSUBQ   0x047
  31 #define FMULQ   0x04b
  32 #define FDIVQ   0x04f
  33 #define FDMULQ  0x06e
  34 #define FQTOX   0x083
  35 #define FXTOQ   0x08c
  36 #define FQTOS   0x0c7
  37 #define FQTOD   0x0cb
  38 #define FITOQ   0x0cc
  39 #define FSTOQ   0x0cd
  40 #define FDTOQ   0x0ce
  41 #define FQTOI   0x0d3
  42 /* SUBNORMAL - ftt == 2 */
  43 #define FSQRTS  0x029
  44 #define FSQRTD  0x02a
  45 #define FADDS   0x041
  46 #define FADDD   0x042
  47 #define FSUBS   0x045
  48 #define FSUBD   0x046
  49 #define FMULS   0x049
  50 #define FMULD   0x04a
  51 #define FDIVS   0x04d
  52 #define FDIVD   0x04e
  53 #define FSMULD  0x069
  54 #define FSTOX   0x081
  55 #define FDTOX   0x082
  56 #define FDTOS   0x0c6
  57 #define FSTOD   0x0c9
  58 #define FSTOI   0x0d1
  59 #define FDTOI   0x0d2
  60 /* FPOP2 */
  61 #define FCMPQ   0x053
  62 #define FCMPEQ  0x057
  63 #define FMOVQ0  0x003
  64 #define FMOVQ1  0x043
  65 #define FMOVQ2  0x083
  66 #define FMOVQ3  0x0c3
  67 #define FMOVQI  0x103
  68 #define FMOVQX  0x183
  69 #define FMOVQZ  0x027
  70 #define FMOVQLE 0x047
  71 #define FMOVQLZ 0x067
  72 #define FMOVQNZ 0x0a7
  73 #define FMOVQGZ 0x0c7
  74 #define FMOVQGE 0x0e7
  75
  76 #define FSR_TEM_SHIFT   23UL
  77 #define FSR_TEM_MASK    (0x1fUL << FSR_TEM_SHIFT)
  78 #define FSR_AEXC_SHIFT  5UL
  79 #define FSR_AEXC_MASK   (0x1fUL << FSR_AEXC_SHIFT)
  80 #define FSR_CEXC_SHIFT  0UL
  81 #define FSR_CEXC_MASK   (0x1fUL << FSR_CEXC_SHIFT)
  82
  83 /* All routines returning an exception to raise should detect
  84  * such exceptions _before_ rounding to be consistant with
  85  * the behavior of the hardware in the implemented cases
  86  * (and thus with the recommendations in the V9 architecture
  87  * manual).
  88  *
  89  * We return 0 if a SIGFPE should be sent, 1 otherwise.
  90  */
  91 static inline int record_exception(struct pt_regs *regs, int eflag)
  92 {
  93         u64 fsr = current->thread.xfsr[0];
  94         int would_trap;
  95
  96         /* Determine if this exception would have generated a trap. */
  97         would_trap = (fsr & ((long)eflag << FSR_TEM_SHIFT)) != 0UL;
  98
  99         /* If trapping, we only want to signal one bit. */
 100         if(would_trap != 0) {
 101                 eflag &= ((fsr & FSR_TEM_MASK) >> FSR_TEM_SHIFT);
 102                 if((eflag & (eflag - 1)) != 0) {
 103                         if(eflag & FP_EX_INVALID)
 104                                 eflag = FP_EX_INVALID;
 105                         else if(eflag & FP_EX_OVERFLOW)
 106                                 eflag = FP_EX_OVERFLOW;
 107                         else if(eflag & FP_EX_UNDERFLOW)
 108                                 eflag = FP_EX_UNDERFLOW;
 109                         else if(eflag & FP_EX_DIVZERO)
 110                                 eflag = FP_EX_DIVZERO;
 111                         else if(eflag & FP_EX_INEXACT)
 112                                 eflag = FP_EX_INEXACT;
 113                 }
 114         }
 115
 116         /* Set CEXC, here is the rule:
 117          *
 118          *    In general all FPU ops will set one and only one
 119          *    bit in the CEXC field, this is always the case
 120          *    when the IEEE exception trap is enabled in TEM.
 121          */
 122         fsr &= ~(FSR_CEXC_MASK);
 123         fsr |= ((long)eflag << FSR_CEXC_SHIFT);
 124
 125         /* Set the AEXC field, rule is:
 126          *
 127          *    If a trap would not be generated, the
 128          *    CEXC just generated is OR'd into the
 129          *    existing value of AEXC.
 130          */
 131         if(would_trap == 0)
 132                 fsr |= ((long)eflag << FSR_AEXC_SHIFT);
 133
 134         /* If trapping, indicate fault trap type IEEE. */
 135         if(would_trap != 0)
 136                 fsr |= (1UL << 14);
 137
 138         current->thread.xfsr[0] = fsr;
 139
 140         /* If we will not trap, advance the program counter over
 141          * the instruction being handled.
 142          */
 143         if(would_trap == 0) {
 144                 regs->tpc = regs->tnpc;
 145                 regs->tnpc += 4;
 146         }
 147
 148         return (would_trap ? 0 : 1);
 149 }
 150
 151 typedef union {
 152         u32 s;
 153         u64 d;
 154         u64 q[2];
 155 } *argp;
 156
 157 int do_mathemu(struct pt_regs *regs, struct fpustate *f)
 158 {
 159         unsigned long pc = regs->tpc;
 160         unsigned long tstate = regs->tstate;
 161         u32 insn = 0;
 162         int type = 0;
 163         /* ftt tells which ftt it may happen in, r is rd, b is rs2 and a is rs1. The *u arg tells
 164            whether the argument should be packed/unpacked (0 - do not unpack/pack, 1 - unpack/pack)
 165            non-u args tells the size of the argument (0 - no argument, 1 - single, 2 - double, 3 - quad */
 166 #define TYPE(ftt, r, ru, b, bu, a, au) type = (au << 2) | (a << 0) | (bu << 5) | (b << 3) | (ru << 8) | (r << 6) | (ftt << 9)
 167         int freg;
 168         static u64 zero[2] = { 0L, 0L };
 169         int flags;
 170         FP_DECL_EX;
 171         FP_DECL_S(SA); FP_DECL_S(SB); FP_DECL_S(SR);
 172         FP_DECL_D(DA); FP_DECL_D(DB); FP_DECL_D(DR);
 173         FP_DECL_Q(QA); FP_DECL_Q(QB); FP_DECL_Q(QR);
 174         int IR;
 175         long XR, xfsr;
 176
 177         if(tstate & TSTATE_PRIV)
 178                 die_if_kernel("FPQuad from kernel", regs);
 179         if(current->thread.flags & SPARC_FLAG_32BIT)
 180                 pc = (u32)pc;
 181         if (get_user(insn, (u32 *)pc) != -EFAULT) {
 182                 if ((insn & 0xc1f80000) == 0x81a00000) /* FPOP1 */ {
 183                         switch ((insn >> 5) & 0x1ff) {
 184                         /* QUAD - ftt == 3 */
 185                         case FMOVQ:
 186                         case FNEGQ:
 187                         case FABSQ: TYPE(3,3,0,3,0,0,0); break;
 188                         case FSQRTQ: TYPE(3,3,1,3,1,0,0); break;
 189                         case FADDQ:
 190                         case FSUBQ:
 191                         case FMULQ:
 192                         case FDIVQ: TYPE(3,3,1,3,1,3,1); break;
 193                         case FDMULQ: TYPE(3,3,1,2,1,2,1); break;
 194                         case FQTOX: TYPE(3,2,0,3,1,0,0); break;
 195                         case FXTOQ: TYPE(3,3,1,2,0,0,0); break;
 196                         case FQTOS: TYPE(3,1,1,3,1,0,0); break;
 197                         case FQTOD: TYPE(3,2,1,3,1,0,0); break;
 198                         case FITOQ: TYPE(3,3,1,1,0,0,0); break;
 199                         case FSTOQ: TYPE(3,3,1,1,1,0,0); break;
 200                         case FDTOQ: TYPE(3,3,1,2,1,0,0); break;
 201                         case FQTOI: TYPE(3,1,0,3,1,0,0); break;
 202                         /* SUBNORMAL - ftt == 2 */
 203                         case FSQRTS: TYPE(2,1,1,1,1,0,0); break;
 204                         case FSQRTD: TYPE(2,2,1,2,1,0,0); break;
 205                         case FADDD:
 206                         case FSUBD:
 207                         case FMULD:
 208                         case FDIVD: TYPE(2,2,1,2,1,2,1); break;
 209                         case FADDS:
 210                         case FSUBS:
 211                         case FMULS:
 212                         case FDIVS: TYPE(2,1,1,1,1,1,1); break;
 213                         case FSMULD: TYPE(2,2,1,1,1,1,1); break;
 214                         case FSTOX: TYPE(2,2,0,1,1,0,0); break;
 215                         case FDTOX: TYPE(2,2,0,2,1,0,0); break;
 216                         case FDTOS: TYPE(2,1,1,2,1,0,0); break;
 217                         case FSTOD: TYPE(2,2,1,1,1,0,0); break;
 218                         case FSTOI: TYPE(2,1,0,1,1,0,0); break;
 219                         case FDTOI: TYPE(2,1,0,2,1,0,0); break;
 220                         }
 221                 }
 222                 else if ((insn & 0xc1f80000) == 0x81a80000) /* FPOP2 */ {
 223                         IR = 2;
 224                         switch ((insn >> 5) & 0x1ff) {
 225                         case FCMPQ: TYPE(3,0,0,3,1,3,1); break;
 226                         case FCMPEQ: TYPE(3,0,0,3,1,3,1); break;
 227                         /* Now the conditional fmovq support */
 228                         case FMOVQ0:
 229                         case FMOVQ1:
 230                         case FMOVQ2:
 231                         case FMOVQ3:
 232                                 /* fmovq %fccX, %fY, %fZ */
 233                                 if (!((insn >> 11) & 3))
 234                                         XR = current->thread.xfsr[0] >> 10;
 235                                 else
 236                                         XR = current->thread.xfsr[0] >> (30 + ((insn >> 10) & 0x6));
 237                                 XR &= 3;
 238                                 IR = 0;
 239                                 switch ((insn >> 14) & 0x7) {
 240                                 /* case 0: IR = 0; break; */                    /* Never */
 241                                 case 1: if (XR) IR = 1; break;                  /* Not Equal */
 242                                 case 2: if (XR == 1 || XR == 2) IR = 1; break;  /* Less or Greater */
 243                                 case 3: if (XR & 1) IR = 1; break;              /* Unordered or Less */
 244                                 case 4: if (XR == 1) IR = 1; break;             /* Less */
 245                                 case 5: if (XR & 2) IR = 1; break;              /* Unordered or Greater */
 246                                 case 6: if (XR == 2) IR = 1; break;             /* Greater */
 247                                 case 7: if (XR == 3) IR = 1; break;             /* Unordered */
 248                                 }
 249                                 if ((insn >> 14) & 8)
 250                                         IR ^= 1;
 251                                 break;
 252                         case FMOVQI:
 253                         case FMOVQX:
 254                                 /* fmovq %[ix]cc, %fY, %fZ */
 255                                 XR = regs->tstate >> 32;
 256                                 if ((insn >> 5) & 0x80)
 257                                         XR >>= 4;
 258                                 XR &= 0xf;
 259                                 IR = 0;
 260                                 freg = ((XR >> 2) ^ XR) & 2;
 261                                 switch ((insn >> 14) & 0x7) {
 262                                 /* case 0: IR = 0; break; */                    /* Never */
 263                                 case 1: if (XR & 4) IR = 1; break;              /* Equal */
 264                                 case 2: if ((XR & 4) || freg) IR = 1; break;    /* Less or Equal */
 265                                 case 3: if (freg) IR = 1; break;                /* Less */
 266                                 case 4: if (XR & 5) IR = 1; break;              /* Less or Equal Unsigned */
 267                                 case 5: if (XR & 1) IR = 1; break;              /* Carry Set */
 268                                 case 6: if (XR & 8) IR = 1; break;              /* Negative */
 269                                 case 7: if (XR & 2) IR = 1; break;              /* Overflow Set */
 270                                 }
 271                                 if ((insn >> 14) & 8)
 272                                         IR ^= 1;
 273                                 break;
 274                         case FMOVQZ:
 275                         case FMOVQLE:
 276                         case FMOVQLZ:
 277                         case FMOVQNZ:
 278                         case FMOVQGZ:
 279                         case FMOVQGE:
 280                                 freg = (insn >> 14) & 0x1f;
 281                                 if (!freg)
 282                                         XR = 0;
 283                                 else if (freg < 16)
 284                                         XR = regs->u_regs[freg];
 285                                 else if (current->thread.flags & SPARC_FLAG_32BIT) {
 286                                         struct reg_window32 *win32;
 287                                         flushw_user ();
 288                                         win32 = (struct reg_window32 *)((unsigned long)((u32)regs->u_regs[UREG_FP]));
 289                                         get_user(XR, &win32->locals[freg - 16]);
 290                                 } else {
 291                                         struct reg_window *win;
 292                                         flushw_user ();
 293                                         win = (struct reg_window *)(regs->u_regs[UREG_FP] + STACK_BIAS);
 294                                         get_user(XR, &win->locals[freg - 16]);
 295                                 }
 296                                 IR = 0;
 297                                 switch ((insn >> 10) & 3) {
 298                                 case 1: if (!XR) IR = 1; break;                 /* Register Zero */
 299                                 case 2: if (XR <= 0) IR = 1; break;             /* Register Less Than or Equal to Zero */
 300                                 case 3: if (XR < 0) IR = 1; break;              /* Register Less Than Zero */
 301                                 }
 302                                 if ((insn >> 10) & 4)
 303                                         IR ^= 1;
 304                                 break;
 305                         }
 306                         if (IR == 0) {
 307                                 /* The fmov test was false. Do a nop instead */
 308                                 current->thread.xfsr[0] &= ~(FSR_CEXC_MASK);
 309                                 regs->tpc = regs->tnpc;
 310                                 regs->tnpc += 4;
 311                                 return 1;
 312                         } else if (IR == 1) {
 313                                 /* Change the instruction into plain fmovq */
 314                                 insn = (insn & 0x3e00001f) | 0x81a00060;
 315                                 TYPE(3,3,0,3,0,0,0);
 316                         }
 317                 }
 318         }
 319         if (type) {
 320                 argp rs1 = NULL, rs2 = NULL, rd = NULL;
 321
 322                 freg = (current->thread.xfsr[0] >> 14) & 0xf;
 323                 if (freg != (type >> 9))
 324                         goto err;
 325                 current->thread.xfsr[0] &= ~0x1c000;
 326                 freg = ((insn >> 14) & 0x1f);
 327                 switch (type & 0x3) {
 328                 case 3: if (freg & 2) {
 329                                 current->thread.xfsr[0] |= (6 << 14) /* invalid_fp_register */;
 330                                 goto err;
 331                         }
 332                 case 2: freg = ((freg & 1) << 5) | (freg & 0x1e);
 333                 case 1: rs1 = (argp)&f->regs[freg];
 334                         flags = (freg < 32) ? FPRS_DL : FPRS_DU;
 335                         if (!(current->thread.fpsaved[0] & flags))
 336                                 rs1 = (argp)&zero;
 337                         break;
 338                 }
 339                 switch (type & 0x7) {
 340                 case 7: FP_UNPACK_QP (QA, rs1); break;
 341                 case 6: FP_UNPACK_DP (DA, rs1); break;
 342                 case 5: FP_UNPACK_SP (SA, rs1); break;
 343                 }
 344                 freg = (insn & 0x1f);
 345                 switch ((type >> 3) & 0x3) {
 346                 case 3: if (freg & 2) {
 347                                 current->thread.xfsr[0] |= (6 << 14) /* invalid_fp_register */;
 348                                 goto err;
 349                         }
 350                 case 2: freg = ((freg & 1) << 5) | (freg & 0x1e);
 351                 case 1: rs2 = (argp)&f->regs[freg];
 352                         flags = (freg < 32) ? FPRS_DL : FPRS_DU;
 353                         if (!(current->thread.fpsaved[0] & flags))
 354                                 rs2 = (argp)&zero;
 355                         break;
 356                 }
 357                 switch ((type >> 3) & 0x7) {
 358                 case 7: FP_UNPACK_QP (QB, rs2); break;
 359                 case 6: FP_UNPACK_DP (DB, rs2); break;
 360                 case 5: FP_UNPACK_SP (SB, rs2); break;
 361                 }
 362                 freg = ((insn >> 25) & 0x1f);
 363                 switch ((type >> 6) & 0x3) {
 364                 case 3: if (freg & 2) {
 365                                 current->thread.xfsr[0] |= (6 << 14) /* invalid_fp_register */;
 366                                 goto err;
 367                         }
 368                 case 2: freg = ((freg & 1) << 5) | (freg & 0x1e);
 369                 case 1: rd = (argp)&f->regs[freg];
 370                         flags = (freg < 32) ? FPRS_DL : FPRS_DU;
 371                         if (!(current->thread.fpsaved[0] & FPRS_FEF)) {
 372                                 current->thread.fpsaved[0] = FPRS_FEF;
 373                                 current->thread.gsr[0] = 0;
 374                         }
 375                         if (!(current->thread.fpsaved[0] & flags)) {
 376                                 if (freg < 32)
 377                                         memset(f->regs, 0, 32*sizeof(u32));
 378                                 else
 379                                         memset(f->regs+32, 0, 32*sizeof(u32));
 380                         }
 381                         current->thread.fpsaved[0] |= flags;
 382                         break;
 383                 }
 384                 switch ((insn >> 5) & 0x1ff) {
 385                 /* + */
 386                 case FADDS: FP_ADD_S (SR, SA, SB); break;
 387                 case FADDD: FP_ADD_D (DR, DA, DB); break;
 388                 case FADDQ: FP_ADD_Q (QR, QA, QB); break;
 389                 /* - */
 390                 case FSUBS: FP_SUB_S (SR, SA, SB); break;
 391                 case FSUBD: FP_SUB_D (DR, DA, DB); break;
 392                 case FSUBQ: FP_SUB_Q (QR, QA, QB); break;
 393                 /* * */
 394                 case FMULS: FP_MUL_S (SR, SA, SB); break;
 395                 case FSMULD: FP_CONV (D, S, 1, 1, DA, SA);
 396                              FP_CONV (D, S, 1, 1, DB, SB);
 397                 case FMULD: FP_MUL_D (DR, DA, DB); break;
 398                 case FDMULQ: FP_CONV (Q, D, 2, 1, QA, DA);
 399                              FP_CONV (Q, D, 2, 1, QB, DB);
 400                 case FMULQ: FP_MUL_Q (QR, QA, QB); break;
 401                 /* / */
 402                 case FDIVS: FP_DIV_S (SR, SA, SB); break;
 403                 case FDIVD: FP_DIV_D (DR, DA, DB); break;
 404                 case FDIVQ: FP_DIV_Q (QR, QA, QB); break;
 405                 /* sqrt */
 406                 case FSQRTS: FP_SQRT_S (SR, SB); break;
 407                 case FSQRTD: FP_SQRT_D (DR, DB); break;
 408                 case FSQRTQ: FP_SQRT_Q (QR, QB); break;
 409                 /* mov */
 410                 case FMOVQ: rd->q[0] = rs2->q[0]; rd->q[1] = rs2->q[1]; break;
 411                 case FABSQ: rd->q[0] = rs2->q[0] & 0x7fffffffffffffffUL; rd->q[1] = rs2->q[1]; break;
 412                 case FNEGQ: rd->q[0] = rs2->q[0] ^ 0x8000000000000000UL; rd->q[1] = rs2->q[1]; break;
 413                 /* float to int */
 414                 case FSTOI: FP_TO_INT_S (IR, SB, 32, 1); break;
 415                 case FDTOI: FP_TO_INT_D (IR, DB, 32, 1); break;
 416                 case FQTOI: FP_TO_INT_Q (IR, QB, 32, 1); break;
 417                 case FSTOX: FP_TO_INT_S (XR, SB, 64, 1); break;
 418                 case FDTOX: FP_TO_INT_D (XR, DB, 64, 1); break;
 419                 case FQTOX: FP_TO_INT_Q (XR, QB, 64, 1); break;
 420                 /* int to float */
 421                 case FITOQ: IR = rs2->s; FP_FROM_INT_Q (QR, IR, 32, int); break;
 422                 case FXTOQ: XR = rs2->d; FP_FROM_INT_Q (QR, XR, 64, long); break;
 423                 /* float to float */
 424                 case FSTOD: FP_CONV (D, S, 1, 1, DR, SB); break;
 425                 case FSTOQ: FP_CONV (Q, S, 2, 1, QR, SB); break;
 426                 case FDTOQ: FP_CONV (Q, D, 2, 1, QR, DB); break;
 427                 case FDTOS: FP_CONV (S, D, 1, 1, SR, DB); break;
 428                 case FQTOS: FP_CONV (S, Q, 1, 2, SR, QB); break;
 429                 case FQTOD: FP_CONV (D, Q, 1, 2, DR, QB); break;
 430                 /* comparison */
 431                 case FCMPQ:
 432                 case FCMPEQ:
 433                         FP_CMP_Q(XR, QB, QA, 3);
 434                         if (XR == 3 &&
 435                             (((insn >> 5) & 0x1ff) == FCMPEQ ||
 436                              FP_ISSIGNAN_Q(QA) ||
 437                              FP_ISSIGNAN_Q(QB)))
 438                                 FP_SET_EXCEPTION (FP_EX_INVALID);
 439                 }
 440                 if (!FP_INHIBIT_RESULTS) {
 441                         switch ((type >> 6) & 0x7) {
 442                         case 0: xfsr = current->thread.xfsr[0];
 443                                 if (XR == -1) XR = 2;
 444                                 switch (freg & 3) {
 445                                 /* fcc0, 1, 2, 3 */
 446                                 case 0: xfsr &= ~0xc00; xfsr |= (XR << 10); break;
 447                                 case 1: xfsr &= ~0x300000000UL; xfsr |= (XR << 32); break;
 448                                 case 2: xfsr &= ~0xc00000000UL; xfsr |= (XR << 34); break;
 449                                 case 3: xfsr &= ~0x3000000000UL; xfsr |= (XR << 36); break;
 450                                 }
 451                                 current->thread.xfsr[0] = xfsr;
 452                                 break;
 453                         case 1: rd->s = IR; break;
 454                         case 2: rd->d = XR; break;
 455                         case 5: FP_PACK_SP (rd, SR); break;
 456                         case 6: FP_PACK_DP (rd, DR); break;
 457                         case 7: FP_PACK_QP (rd, QR); break;
 458                         }
 459                 }
 460
 461                 if(_fex != 0)
 462                         return record_exception(regs, _fex);
 463
 464                 /* Success and no exceptions detected. */
 465                 current->thread.xfsr[0] &= ~(FSR_CEXC_MASK);
 466                 regs->tpc = regs->tnpc;
 467                 regs->tnpc += 4;
 468                 return 1;
 469         }
 470 err:    return 0;
 471 }