arch/ppc/kernel/chrp_pci.c

   1 /*
   2  * CHRP pci routines.
   3  */
   4
   5 #include <linux/kernel.h>
   6 #include <linux/pci.h>
   7 #include <linux/delay.h>
   8 #include <linux/string.h>
   9 #include <linux/init.h>
  10 #include <linux/openpic.h>
  11 #include <linux/ide.h>
  12
  13 #include <asm/io.h>
  14 #include <asm/pgtable.h>
  15 #include <asm/irq.h>
  16 #include <asm/hydra.h>
  17 #include <asm/prom.h>
  18 #include <asm/gg2.h>
  19 #include <asm/ide.h>
  20 #include <asm/machdep.h>
  21
  22 #include "pci.h"
  23
  24 /* LongTrail */
  25 #define pci_config_addr(bus, dev, offset) \
  26 (GG2_PCI_CONFIG_BASE | ((bus)<<16) | ((dev)<<8) | (offset))
  27
  28 volatile struct Hydra *Hydra = NULL;
  29
  30 /*
  31  * The VLSI Golden Gate II has only 512K of PCI configuration space, so we
  32  * limit the bus number to 3 bits
  33  */
  34
  35 int gg2_pcibios_read_config_byte(unsigned char bus, unsigned char dev_fn,
  36                                  unsigned char offset, unsigned char *val)
  37 {
  38         if (bus > 7) {
  39                 *val = 0xff;
  40                 return PCIBIOS_DEVICE_NOT_FOUND;
  41         }
  42         *val = in_8((unsigned char *)pci_config_addr(bus, dev_fn, offset));
  43         return PCIBIOS_SUCCESSFUL;
  44 }
  45
  46 int gg2_pcibios_read_config_word(unsigned char bus, unsigned char dev_fn,
  47                                  unsigned char offset, unsigned short *val)
  48 {
  49         if (bus > 7) {
  50                 *val = 0xffff;
  51                 return PCIBIOS_DEVICE_NOT_FOUND;
  52         }
  53         *val = in_le16((unsigned short *)pci_config_addr(bus, dev_fn, offset));
  54         return PCIBIOS_SUCCESSFUL;
  55 }
  56
  57
  58 int gg2_pcibios_read_config_dword(unsigned char bus, unsigned char dev_fn,
  59                                   unsigned char offset, unsigned int *val)
  60 {
  61         if (bus > 7) {
  62                 *val = 0xffffffff;
  63                 return PCIBIOS_DEVICE_NOT_FOUND;
  64         }
  65         *val = in_le32((unsigned int *)pci_config_addr(bus, dev_fn, offset));
  66         return PCIBIOS_SUCCESSFUL;
  67 }
  68
  69 int gg2_pcibios_write_config_byte(unsigned char bus, unsigned char dev_fn,
  70                                   unsigned char offset, unsigned char val)
  71 {
  72         if (bus > 7)
  73                 return PCIBIOS_DEVICE_NOT_FOUND;
  74         out_8((unsigned char *)pci_config_addr(bus, dev_fn, offset), val);
  75         return PCIBIOS_SUCCESSFUL;
  76 }
  77
  78 int gg2_pcibios_write_config_word(unsigned char bus, unsigned char dev_fn,
  79                                   unsigned char offset, unsigned short val)
  80 {
  81         if (bus > 7)
  82                 return PCIBIOS_DEVICE_NOT_FOUND;
  83         out_le16((unsigned short *)pci_config_addr(bus, dev_fn, offset), val);
  84         return PCIBIOS_SUCCESSFUL;
  85 }
  86
  87 int gg2_pcibios_write_config_dword(unsigned char bus, unsigned char dev_fn,
  88                                    unsigned char offset, unsigned int val)
  89 {
  90         if (bus > 7)
  91                 return PCIBIOS_DEVICE_NOT_FOUND;
  92         out_le32((unsigned int *)pci_config_addr(bus, dev_fn, offset), val);
  93         return PCIBIOS_SUCCESSFUL;
  94 }
  95
  96 #define python_config_address(bus) (unsigned *)((0xfef00000+0xf8000)-(bus*0x100000))
  97 #define python_config_data(bus) ((0xfef00000+0xf8010)-(bus*0x100000))
  98 #define PYTHON_CFA(b, d, o)     (0x80 | ((b<<6) << 8) | ((d) << 16) \
  99                                  | (((o) & ~3) << 24))
 100 unsigned int python_busnr = 0;
 101
 102 int python_pcibios_read_config_byte(unsigned char bus, unsigned char dev_fn,
 103                                     unsigned char offset, unsigned char *val)
 104 {
 105         if (bus > python_busnr) {
 106                 *val = 0xff;
 107                 return PCIBIOS_DEVICE_NOT_FOUND;
 108         }
 109         out_be32( python_config_address( bus ), PYTHON_CFA(bus,dev_fn,offset));
 110         *val = in_8((unsigned char *)python_config_data(bus) + (offset&3));
 111         return PCIBIOS_SUCCESSFUL;
 112 }
 113
 114 int python_pcibios_read_config_word(unsigned char bus, unsigned char dev_fn,
 115                                     unsigned char offset, unsigned short *val)
 116 {
 117         if (bus > python_busnr) {
 118                 *val = 0xffff;
 119                 return PCIBIOS_DEVICE_NOT_FOUND;
 120         }
 121         out_be32( python_config_address( bus ), PYTHON_CFA(bus,dev_fn,offset));
 122         *val = in_le16((unsigned short *)(python_config_data(bus) + (offset&3)));
 123         return PCIBIOS_SUCCESSFUL;
 124 }
 125
 126
 127 int python_pcibios_read_config_dword(unsigned char bus, unsigned char dev_fn,
 128                                      unsigned char offset, unsigned int *val)
 129 {
 130         if (bus > python_busnr) {
 131                 *val = 0xffffffff;
 132                 return PCIBIOS_DEVICE_NOT_FOUND;
 133         }
 134         out_be32( python_config_address( bus ), PYTHON_CFA(bus,dev_fn,offset));
 135         *val = in_le32((unsigned *)python_config_data(bus));
 136         return PCIBIOS_SUCCESSFUL;
 137 }
 138
 139 int python_pcibios_write_config_byte(unsigned char bus, unsigned char dev_fn,
 140                                      unsigned char offset, unsigned char val)
 141 {
 142         if (bus > python_busnr)
 143                 return PCIBIOS_DEVICE_NOT_FOUND;
 144         out_be32( python_config_address( bus ), PYTHON_CFA(bus,dev_fn,offset));
 145         out_8((volatile unsigned char *)python_config_data(bus) + (offset&3), val);
 146         return PCIBIOS_SUCCESSFUL;
 147 }
 148
 149 int python_pcibios_write_config_word(unsigned char bus, unsigned char dev_fn,
 150                                      unsigned char offset, unsigned short val)
 151 {
 152         if (bus > python_busnr)
 153                 return PCIBIOS_DEVICE_NOT_FOUND;
 154         out_be32( python_config_address( bus ), PYTHON_CFA(bus,dev_fn,offset));
 155         out_le16((volatile unsigned short *)python_config_data(bus) + (offset&3),
 156                  val);
 157         return PCIBIOS_SUCCESSFUL;
 158 }
 159
 160 int python_pcibios_write_config_dword(unsigned char bus, unsigned char dev_fn,
 161                                       unsigned char offset, unsigned int val)
 162 {
 163         if (bus > python_busnr)
 164                 return PCIBIOS_DEVICE_NOT_FOUND;
 165         out_be32( python_config_address( bus ), PYTHON_CFA(bus,dev_fn,offset));
 166         out_le32((unsigned *)python_config_data(bus) + (offset&3), val);
 167         return PCIBIOS_SUCCESSFUL;
 168 }
 169
 170
 171 int rtas_pcibios_read_config_byte(unsigned char bus, unsigned char dev_fn,
 172                                     unsigned char offset, unsigned char *val)
 173 {
 174         unsigned long addr = (offset&0xff) | ((dev_fn&0xff)<<8) | ((bus & 0xff)<<16);
 175         if ( call_rtas( "read-pci-config", 2, 2, (ulong *)&val, addr, 1 ) != 0 )
 176                 return PCIBIOS_DEVICE_NOT_FOUND;
 177         return PCIBIOS_SUCCESSFUL;
 178 }
 179
 180 int rtas_pcibios_read_config_word(unsigned char bus, unsigned char dev_fn,
 181                                     unsigned char offset, unsigned short *val)
 182 {
 183         unsigned long addr = (offset&0xff) | ((dev_fn&0xff)<<8) | ((bus & 0xff)<<16);
 184         if ( call_rtas( "read-pci-config", 2, 2, (ulong *)&val, addr, 2 ) != 0 )
 185                 return PCIBIOS_DEVICE_NOT_FOUND;
 186         return PCIBIOS_SUCCESSFUL;
 187 }
 188
 189
 190 int rtas_pcibios_read_config_dword(unsigned char bus, unsigned char dev_fn,
 191                                      unsigned char offset, unsigned int *val)
 192 {
 193         unsigned long addr = (offset&0xff) | ((dev_fn&0xff)<<8) | ((bus & 0xff)<<16);
 194         if ( call_rtas( "read-pci-config", 2, 2, (ulong *)&val, addr, 4 ) != 0 )
 195                 return PCIBIOS_DEVICE_NOT_FOUND;
 196         return PCIBIOS_SUCCESSFUL;
 197 }
 198
 199 int rtas_pcibios_write_config_byte(unsigned char bus, unsigned char dev_fn,
 200                                      unsigned char offset, unsigned char val)
 201 {
 202         unsigned long addr = (offset&0xff) | ((dev_fn&0xff)<<8) | ((bus & 0xff)<<16);
 203         if ( call_rtas( "write-pci-config", 3, 1, NULL, addr, 1, (ulong)val ) != 0 )
 204                 return PCIBIOS_DEVICE_NOT_FOUND;
 205         return PCIBIOS_SUCCESSFUL;
 206 }
 207
 208 int rtas_pcibios_write_config_word(unsigned char bus, unsigned char dev_fn,
 209                                      unsigned char offset, unsigned short val)
 210 {
 211         unsigned long addr = (offset&0xff) | ((dev_fn&0xff)<<8) | ((bus & 0xff)<<16);
 212         if ( call_rtas( "write-pci-config", 3, 1, NULL, addr, 2, (ulong)val ) != 0 )
 213                 return PCIBIOS_DEVICE_NOT_FOUND;
 214         return PCIBIOS_SUCCESSFUL;
 215 }
 216
 217 int rtas_pcibios_write_config_dword(unsigned char bus, unsigned char dev_fn,
 218                                       unsigned char offset, unsigned int val)
 219 {
 220         unsigned long addr = (offset&0xff) | ((dev_fn&0xff)<<8) | ((bus & 0xff)<<16);
 221         if ( call_rtas( "write-pci-config", 3, 1, NULL, addr, 4, (ulong)val ) != 0 )
 222                 return PCIBIOS_DEVICE_NOT_FOUND;
 223         return PCIBIOS_SUCCESSFUL;
 224 }
 225
 226     /*
 227      *  Temporary fixes for PCI devices. These should be replaced by OF query
 228      *  code -- Geert
 229      */
 230
 231 static u_char hydra_openpic_initsenses[] __initdata = {
 232     1,  /* HYDRA_INT_SIO */
 233     0,  /* HYDRA_INT_SCSI_DMA */
 234     0,  /* HYDRA_INT_SCCA_TX_DMA */
 235     0,  /* HYDRA_INT_SCCA_RX_DMA */
 236     0,  /* HYDRA_INT_SCCB_TX_DMA */
 237     0,  /* HYDRA_INT_SCCB_RX_DMA */
 238     1,  /* HYDRA_INT_SCSI */
 239     1,  /* HYDRA_INT_SCCA */
 240     1,  /* HYDRA_INT_SCCB */
 241     1,  /* HYDRA_INT_VIA */
 242     1,  /* HYDRA_INT_ADB */
 243     0,  /* HYDRA_INT_ADB_NMI */
 244         /* all others are 1 (= default) */
 245 };
 246
 247 int __init
 248 hydra_init(void)
 249 {
 250         struct device_node *np;
 251
 252         np = find_devices("mac-io");
 253         if (np == NULL || np->n_addrs == 0) {
 254                 printk(KERN_WARNING "Warning: no mac-io found\n");
 255                 return 0;
 256         }
 257         Hydra = ioremap(np->addrs[0].address, np->addrs[0].size);
 258         printk("Hydra Mac I/O at %x\n", np->addrs[0].address);
 259         out_le32(&Hydra->Feature_Control, (HYDRA_FC_SCC_CELL_EN |
 260                                            HYDRA_FC_SCSI_CELL_EN |
 261                                            HYDRA_FC_SCCA_ENABLE |
 262                                            HYDRA_FC_SCCB_ENABLE |
 263                                            HYDRA_FC_ARB_BYPASS |
 264                                            HYDRA_FC_MPIC_ENABLE |
 265                                            HYDRA_FC_SLOW_SCC_PCLK |
 266                                            HYDRA_FC_MPIC_IS_MASTER));
 267         OpenPIC = (volatile struct OpenPIC *)&Hydra->OpenPIC;
 268         OpenPIC_InitSenses = hydra_openpic_initsenses;
 269         OpenPIC_NumInitSenses = sizeof(hydra_openpic_initsenses);
 270         return 1;
 271 }
 272
 273 void __init
 274 chrp_pcibios_fixup(void)
 275 {
 276         struct pci_dev *dev;
 277
 278         /* some of IBM chrps have > 1 bus */
 279         if ( !strncmp("IBM", get_property(find_path_device("/"),
 280                                          "name", NULL),3) )
 281         {
 282
 283         }
 284
 285         /* PCI interrupts are controlled by the OpenPIC */
 286         for( dev=pci_devices ; dev; dev=dev->next )
 287         {
 288                 if ( dev->irq )
 289                         dev->irq = openpic_to_irq( dev->irq );
 290                 /* adjust the io_port for the NCR cards for busses other than 0 -- Cort */
 291                 if ( (dev->bus->number > 0) && (dev->vendor == PCI_VENDOR_ID_NCR) )
 292                         dev->resource[0].start += (dev->bus->number*0x08000000);
 293                 /* these need to be absolute addrs for OF and Matrox FB -- Cort */
 294                 if ( dev->vendor == PCI_VENDOR_ID_MATROX )
 295                 {
 296                         if ( dev->resource[0].start < isa_mem_base )
 297                                 dev->resource[0].start += isa_mem_base;
 298                         if ( dev->resource[1].start < isa_mem_base )
 299                                 dev->resource[1].start += isa_mem_base;
 300                 }
 301                 /* the F50 identifies the amd as a trident */
 302                 if ( (dev->vendor == PCI_VENDOR_ID_TRIDENT) &&
 303                       (dev->class>>8 == PCI_CLASS_NETWORK_ETHERNET) )
 304                 {
 305                         dev->vendor = PCI_VENDOR_ID_AMD;
 306                         pcibios_write_config_word(dev->bus->number,
 307                           dev->devfn, PCI_VENDOR_ID, PCI_VENDOR_ID_AMD);
 308                 }
 309         }
 310 }
 311
 312 decl_config_access_method(grackle);
 313 decl_config_access_method(indirect);
 314 decl_config_access_method(rtas);
 315
 316 void __init
 317 chrp_setup_pci_ptrs(void)
 318 {
 319         struct device_node *py;
 320
 321         if ( !strncmp("MOT",
 322                       get_property(find_path_device("/"), "model", NULL),3) )
 323         {
 324                 pci_dram_offset = 0;
 325                 isa_mem_base = 0xf7000000;
 326                 isa_io_base = 0xfe000000;
 327                 set_config_access_method(grackle);
 328         }
 329         else
 330         {
 331                 if ( (py = find_compatible_devices( "pci", "IBM,python" )) )
 332                 {
 333                         /* find out how many pythons */
 334                         while ( (py = py->next) ) python_busnr++;
 335                         set_config_access_method(python);
 336                         /*
 337                          * We base these values on the machine type but should
 338                          * try to read them from the python controller itself.
 339                          * -- Cort
 340                          */
 341                         if ( !strncmp("IBM,7025-F50", get_property(find_path_device("/"), "name", NULL),12) )
 342                         {
 343                                 pci_dram_offset = 0x80000000;
 344                                 isa_mem_base = 0xa0000000;
 345                                 isa_io_base = 0x88000000;
 346                         } else if ( !strncmp("IBM,7043-260",
 347                            get_property(find_path_device("/"), "name", NULL),12) )
 348                         {
 349                                 pci_dram_offset = 0x0;
 350                                 isa_mem_base = 0xc0000000;
 351                                 isa_io_base = 0xf8000000;
 352                         }
 353                 }
 354                 else
 355                 {
 356                         if ( !strncmp("IBM,7043-150", get_property(find_path_device("/"), "name", NULL),12) ||
 357                              !strncmp("IBM,7046-155", get_property(find_path_device("/"), "name", NULL),12) )
 358                         {
 359                                 pci_dram_offset = 0;
 360                                 isa_mem_base = 0x80000000;
 361                                 isa_io_base = 0xfe000000;
 362                                 pci_config_address = (unsigned int *)0xfec00000;
 363                                 pci_config_data = (unsigned char *)0xfee00000;
 364                                 set_config_access_method(indirect);
 365                         }
 366                         else
 367                         {
 368                                 pci_dram_offset = 0;
 369                                 isa_mem_base = 0xf7000000;
 370                                 isa_io_base = 0xf8000000;
 371                                 set_config_access_method(gg2);
 372                         }
 373                 }
 374         }
 375
 376         ppc_md.pcibios_fixup = chrp_pcibios_fixup;
 377 }