arch/alpha/kernel/sys_sio.c

   1 /*
   2  *      linux/arch/alpha/kernel/sys_sio.c
   3  *
   4  *      Copyright (C) 1995 David A Rusling
   5  *      Copyright (C) 1996 Jay A Estabrook
   6  *      Copyright (C) 1998, 1999 Richard Henderson
   7  *
   8  * Code for all boards that route the PCI interrupts through the SIO
   9  * PCI/ISA bridge.  This includes Noname (AXPpci33), Multia (UDB),
  10  * Kenetics's Platform 2000, Avanti (AlphaStation), XL, and AlphaBook1.
  11  */
  12
  13 #include <linux/config.h>
  14 #include <linux/kernel.h>
  15 #include <linux/types.h>
  16 #include <linux/mm.h>
  17 #include <linux/sched.h>
  18 #include <linux/pci.h>
  19 #include <linux/init.h>
  20
  21 #include <asm/compiler.h>
  22 #include <asm/ptrace.h>
  23 #include <asm/system.h>
  24 #include <asm/dma.h>
  25 #include <asm/irq.h>
  26 #include <asm/mmu_context.h>
  27 #include <asm/io.h>
  28 #include <asm/pgtable.h>
  29 #include <asm/core_apecs.h>
  30 #include <asm/core_lca.h>
  31 #include <asm/pci.h>
  32
  33 #include "proto.h"
  34 #include "irq_impl.h"
  35 #include "pci_impl.h"
  36 #include "machvec_impl.h"
  37
  38 static void
  39 sio_update_irq_hw(unsigned long irq, unsigned long mask, int unmask_p)
  40 {
  41         if (irq >= 8)
  42                 outb(mask >> 8, 0xA1);
  43         else
  44                 outb(mask, 0x21);
  45 }
  46
  47 static void __init
  48 sio_init_irq(void)
  49 {
  50         STANDARD_INIT_IRQ_PROLOG;
  51
  52         if (alpha_using_srm)
  53                 alpha_mv.device_interrupt = srm_device_interrupt;
  54
  55         enable_irq(2);                  /* enable cascade */
  56 }
  57
  58 static inline void __init
  59 xl_init_arch(unsigned long *mem_start, unsigned long *mem_end)
  60 {
  61         struct pci_controler *hose;
  62
  63         /*
  64          * Set up the PCI->physical memory translation windows.  For
  65          * the XL we *must* use both windows, in order to maximize the
  66          * amount of physical memory that can be used to DMA from the
  67          * ISA bus, and still allow PCI bus devices access to all of
  68          * host memory.
  69          *
  70          * See <asm/apecs.h> for window bases and sizes.
  71          *
  72          * This restriction due to the true XL motherboards' 82379AB SIO
  73          * PCI<->ISA bridge chip which passes only 27 bits of address...
  74          */
  75
  76         *(vuip)APECS_IOC_PB1R = 1<<19 | (APECS_XL_DMA_WIN1_BASE & 0xfff00000U);
  77         *(vuip)APECS_IOC_PM1R = (APECS_XL_DMA_WIN1_SIZE - 1) & 0xfff00000U;
  78         *(vuip)APECS_IOC_TB1R = 0;
  79
  80         *(vuip)APECS_IOC_PB2R = 1<<19 | (APECS_XL_DMA_WIN2_BASE & 0xfff00000U);
  81         *(vuip)APECS_IOC_PM2R = (APECS_XL_DMA_WIN2_SIZE - 1) & 0xfff00000U;
  82         *(vuip)APECS_IOC_TB2R = 0;
  83
  84         /*
  85          * Finally, clear the HAXR2 register, which gets used for PCI
  86          * Config Space accesses. That is the way we want to use it,
  87          * and we do not want to depend on what ARC or SRM might have
  88          * left behind...
  89          */
  90
  91         *(vuip)APECS_IOC_HAXR2 = 0; mb();
  92
  93         /*
  94          * Create our single hose.
  95          */
  96
  97         hose = alloc_pci_controler(mem_start);
  98         hose->io_space = &ioport_resource;
  99         hose->mem_space = &iomem_resource;
 100         hose->config_space = LCA_CONF;
 101         hose->index = 0;
 102 }
 103
 104 static inline void __init
 105 alphabook1_init_arch(unsigned long *mem_start, unsigned long *mem_end)
 106 {
 107         /* The AlphaBook1 has LCD video fixed at 800x600,
 108            37 rows and 100 cols. */
 109         screen_info.orig_y = 37;
 110         screen_info.orig_video_cols = 100;
 111         screen_info.orig_video_lines = 37;
 112
 113         lca_init_arch(mem_start, mem_end);
 114 }
 115
 116
 117 /*
 118  * sio_route_tab selects irq routing in PCI/ISA bridge so that:
 119  *              PIRQ0 -> irq 15
 120  *              PIRQ1 -> irq  9
 121  *              PIRQ2 -> irq 10
 122  *              PIRQ3 -> irq 11
 123  *
 124  * This probably ought to be configurable via MILO.  For
 125  * example, sound boards seem to like using IRQ 9.
 126  *
 127  * This is NOT how we should do it. PIRQ0-X should have
 128  * their own IRQ's, the way intel uses the IO-APIC irq's.
 129  */
 130
 131 static void __init
 132 sio_pci_route(void)
 133 {
 134         pcibios_write_config_dword(0, PCI_DEVFN(7, 0), 0x60,
 135                                    alpha_mv.sys.sio.route_tab);
 136 }
 137
 138 static unsigned int __init
 139 sio_collect_irq_levels(void)
 140 {
 141         unsigned int level_bits = 0;
 142         struct pci_dev *dev;
 143
 144         /* Iterate through the devices, collecting IRQ levels.  */
 145         for (dev = pci_devices; dev; dev = dev->next) {
 146                 if ((dev->class >> 16 == PCI_BASE_CLASS_BRIDGE) &&
 147                     (dev->class >> 8 != PCI_CLASS_BRIDGE_PCMCIA))
 148                         continue;
 149
 150                 if (dev->irq)
 151                         level_bits |= (1 << dev->irq);
 152         }
 153         return level_bits;
 154 }
 155
 156 static void __init
 157 sio_fixup_irq_levels(unsigned int level_bits)
 158 {
 159         unsigned int old_level_bits;
 160
 161         /*
 162          * Now, make all PCI interrupts level sensitive.  Notice:
 163          * these registers must be accessed byte-wise.  inw()/outw()
 164          * don't work.
 165          *
 166          * Make sure to turn off any level bits set for IRQs 9,10,11,15,
 167          *  so that the only bits getting set are for devices actually found.
 168          * Note that we do preserve the remainder of the bits, which we hope
 169          *  will be set correctly by ARC/SRM.
 170          *
 171          * Note: we at least preserve any level-set bits on AlphaBook1
 172          */
 173         old_level_bits = inb(0x4d0) | (inb(0x4d1) << 8);
 174
 175         level_bits |= (old_level_bits & 0x71ff);
 176
 177         outb((level_bits >> 0) & 0xff, 0x4d0);
 178         outb((level_bits >> 8) & 0xff, 0x4d1);
 179 }
 180
 181 static inline int __init
 182 noname_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
 183 {
 184         /*
 185          * The Noname board has 5 PCI slots with each of the 4
 186          * interrupt pins routed to different pins on the PCI/ISA
 187          * bridge (PIRQ0-PIRQ3).  The table below is based on
 188          * information available at:
 189          *
 190          *   http://ftp.digital.com/pub/DEC/axppci/ref_interrupts.txt
 191          *
 192          * I have no information on the Avanti interrupt routing, but
 193          * the routing seems to be identical to the Noname except
 194          * that the Avanti has an additional slot whose routing I'm
 195          * unsure of.
 196          *
 197          * pirq_tab[0] is a fake entry to deal with old PCI boards
 198          * that have the interrupt pin number hardwired to 0 (meaning
 199          * that they use the default INTA line, if they are interrupt
 200          * driven at all).
 201          */
 202         static char irq_tab[][5] __initlocaldata = {
 203                 /*INT A   B   C   D */
 204                 { 3,  3,  3,  3,  3}, /* idsel  6 (53c810) */
 205                 {-1, -1, -1, -1, -1}, /* idsel  7 (SIO: PCI/ISA bridge) */
 206                 { 2,  2, -1, -1, -1}, /* idsel  8 (Hack: slot closest ISA) */
 207                 {-1, -1, -1, -1, -1}, /* idsel  9 (unused) */
 208                 {-1, -1, -1, -1, -1}, /* idsel 10 (unused) */
 209                 { 0,  0,  2,  1,  0}, /* idsel 11 KN25_PCI_SLOT0 */
 210                 { 1,  1,  0,  2,  1}, /* idsel 12 KN25_PCI_SLOT1 */
 211                 { 2,  2,  1,  0,  2}, /* idsel 13 KN25_PCI_SLOT2 */
 212                 { 0,  0,  0,  0,  0}, /* idsel 14 AS255 TULIP */
 213         };
 214         const long min_idsel = 6, max_idsel = 14, irqs_per_slot = 5;
 215         int irq = COMMON_TABLE_LOOKUP, tmp;
 216         tmp = __kernel_extbl(alpha_mv.sys.sio.route_tab, irq);
 217         return irq >= 0 ? tmp : -1;
 218 }
 219
 220 static inline int __init
 221 p2k_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
 222 {
 223         static char irq_tab[][5] __initlocaldata = {
 224                 /*INT A   B   C   D */
 225                 { 0,  0, -1, -1, -1}, /* idsel  6 (53c810) */
 226                 {-1, -1, -1, -1, -1}, /* idsel  7 (SIO: PCI/ISA bridge) */
 227                 { 1,  1,  2,  3,  0}, /* idsel  8 (slot A) */
 228                 { 2,  2,  3,  0,  1}, /* idsel  9 (slot B) */
 229                 {-1, -1, -1, -1, -1}, /* idsel 10 (unused) */
 230                 {-1, -1, -1, -1, -1}, /* idsel 11 (unused) */
 231                 { 3,  3, -1, -1, -1}, /* idsel 12 (CMD0646) */
 232         };
 233         const long min_idsel = 6, max_idsel = 12, irqs_per_slot = 5;
 234         int irq = COMMON_TABLE_LOOKUP, tmp;
 235         tmp = __kernel_extbl(alpha_mv.sys.sio.route_tab, irq);
 236         return irq >= 0 ? tmp : -1;
 237 }
 238
 239 static inline void __init
 240 noname_init_pci(void)
 241 {
 242         sio_pci_route();
 243         common_init_pci();
 244         sio_fixup_irq_levels(sio_collect_irq_levels());
 245         ns87312_enable_ide(0x26e);
 246 }
 247
 248 static inline void __init
 249 alphabook1_init_pci(void)
 250 {
 251         struct pci_dev *dev;
 252         unsigned char orig, config;
 253
 254         sio_pci_route();
 255         common_init_pci();
 256
 257         /*
 258          * On the AlphaBook1, the PCMCIA chip (Cirrus 6729)
 259          * is sensitive to PCI bus bursts, so we must DISABLE
 260          * burst mode for the NCR 8xx SCSI... :-(
 261          *
 262          * Note that the NCR810 SCSI driver must preserve the
 263          * setting of the bit in order for this to work.  At the
 264          * moment (2.0.29), ncr53c8xx.c does NOT do this, but
 265          * 53c7,8xx.c DOES.
 266          */
 267
 268         dev = NULL;
 269         while ((dev = pci_find_device(PCI_VENDOR_ID_NCR, PCI_ANY_ID, dev))) {
 270                 if (dev->device == PCI_DEVICE_ID_NCR_53C810
 271                     || dev->device == PCI_DEVICE_ID_NCR_53C815
 272                     || dev->device == PCI_DEVICE_ID_NCR_53C820
 273                     || dev->device == PCI_DEVICE_ID_NCR_53C825) {
 274                         unsigned long io_port;
 275                         unsigned char ctest4;
 276
 277                         io_port = dev->resource[0].start;
 278                         ctest4 = inb(io_port+0x21);
 279                         if (!(ctest4 & 0x80)) {
 280                                 printk("AlphaBook1 NCR init: setting"
 281                                        " burst disable\n");
 282                                 outb(ctest4 | 0x80, io_port+0x21);
 283                         }
 284                 }
 285         }
 286
 287         /* Do not set *ANY* level triggers for AlphaBook1. */
 288         sio_fixup_irq_levels(0);
 289
 290         /* Make sure that register PR1 indicates 1Mb mem */
 291         outb(0x0f, 0x3ce); orig = inb(0x3cf);   /* read PR5  */
 292         outb(0x0f, 0x3ce); outb(0x05, 0x3cf);   /* unlock PR0-4 */
 293         outb(0x0b, 0x3ce); config = inb(0x3cf); /* read PR1 */
 294         if ((config & 0xc0) != 0xc0) {
 295                 printk("AlphaBook1 VGA init: setting 1Mb memory\n");
 296                 config |= 0xc0;
 297                 outb(0x0b, 0x3ce); outb(config, 0x3cf); /* write PR1 */
 298         }
 299         outb(0x0f, 0x3ce); outb(orig, 0x3cf); /* (re)lock PR0-4 */
 300 }
 301
 302
 303 /*
 304  * The System Vectors
 305  */
 306
 307 #if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_BOOK1)
 308 struct alpha_machine_vector alphabook1_mv __initmv = {
 309         vector_name:            "AlphaBook1",
 310         DO_EV4_MMU,
 311         DO_DEFAULT_RTC,
 312         DO_LCA_IO,
 313         DO_LCA_BUS,
 314         machine_check:          lca_machine_check,
 315         max_dma_address:        ALPHA_MAX_DMA_ADDRESS,
 316         min_io_address:         DEFAULT_IO_BASE,
 317         min_mem_address:        APECS_AND_LCA_DEFAULT_MEM_BASE,
 318
 319         nr_irqs:                16,
 320         irq_probe_mask:         _PROBE_MASK(16),
 321         update_irq_hw:          sio_update_irq_hw,
 322         ack_irq:                common_ack_irq,
 323         device_interrupt:       isa_device_interrupt,
 324
 325         init_arch:              alphabook1_init_arch,
 326         init_irq:               sio_init_irq,
 327         init_pit:               common_init_pit,
 328         init_pci:               alphabook1_init_pci,
 329         kill_arch:              common_kill_arch,
 330         pci_map_irq:            noname_map_irq,
 331         pci_swizzle:            common_swizzle,
 332
 333         sys: { sio: {
 334                 /* NCR810 SCSI is 14, PCMCIA controller is 15.  */
 335                 route_tab:      0x0e0f0a0a,
 336         }}
 337 };
 338 ALIAS_MV(alphabook1)
 339 #endif
 340
 341 #if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_AVANTI)
 342 struct alpha_machine_vector avanti_mv __initmv = {
 343         vector_name:            "Avanti",
 344         DO_EV4_MMU,
 345         DO_DEFAULT_RTC,
 346         DO_APECS_IO,
 347         DO_APECS_BUS,
 348         machine_check:          apecs_machine_check,
 349         max_dma_address:        ALPHA_MAX_DMA_ADDRESS,
 350         min_io_address:         DEFAULT_IO_BASE,
 351         min_mem_address:        APECS_AND_LCA_DEFAULT_MEM_BASE,
 352
 353         nr_irqs:                16,
 354         irq_probe_mask:         _PROBE_MASK(16),
 355         update_irq_hw:          sio_update_irq_hw,
 356         ack_irq:                common_ack_irq,
 357         device_interrupt:       isa_device_interrupt,
 358
 359         init_arch:              apecs_init_arch,
 360         init_irq:               sio_init_irq,
 361         init_pit:               common_init_pit,
 362         init_pci:               noname_init_pci,
 363         kill_arch:              common_kill_arch,
 364         pci_map_irq:            noname_map_irq,
 365         pci_swizzle:            common_swizzle,
 366
 367         sys: { sio: {
 368                 route_tab:      0x0b0a0e0f,
 369         }}
 370 };
 371 ALIAS_MV(avanti)
 372 #endif
 373
 374 #if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_NONAME)
 375 struct alpha_machine_vector noname_mv __initmv = {
 376         vector_name:            "Noname",
 377         DO_EV4_MMU,
 378         DO_DEFAULT_RTC,
 379         DO_LCA_IO,
 380         DO_LCA_BUS,
 381         machine_check:          lca_machine_check,
 382         max_dma_address:        ALPHA_MAX_DMA_ADDRESS,
 383         min_io_address:         DEFAULT_IO_BASE,
 384         min_mem_address:        APECS_AND_LCA_DEFAULT_MEM_BASE,
 385
 386         nr_irqs:                16,
 387         irq_probe_mask:         _PROBE_MASK(16),
 388         update_irq_hw:          sio_update_irq_hw,
 389         ack_irq:                common_ack_irq,
 390         device_interrupt:       srm_device_interrupt,
 391
 392         init_arch:              lca_init_arch,
 393         init_irq:               sio_init_irq,
 394         init_pit:               common_init_pit,
 395         init_pci:               noname_init_pci,
 396         kill_arch:              common_kill_arch,
 397         pci_map_irq:            noname_map_irq,
 398         pci_swizzle:            common_swizzle,
 399
 400         sys: { sio: {
 401                 /* For UDB, the only available PCI slot must not map to IRQ 9,
 402                    since that's the builtin MSS sound chip. That PCI slot
 403                    will map to PIRQ1 (for INTA at least), so we give it IRQ 15
 404                    instead.
 405
 406                    Unfortunately we have to do this for NONAME as well, since
 407                    they are co-indicated when the platform type "Noname" is
 408                    selected... :-(  */
 409
 410                 route_tab:      0x0b0a0f0d,
 411         }}
 412 };
 413 ALIAS_MV(noname)
 414 #endif
 415
 416 #if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_P2K)
 417 struct alpha_machine_vector p2k_mv __initmv = {
 418         vector_name:            "Platform2000",
 419         DO_EV4_MMU,
 420         DO_DEFAULT_RTC,
 421         DO_LCA_IO,
 422         DO_LCA_BUS,
 423         machine_check:          lca_machine_check,
 424         max_dma_address:        ALPHA_MAX_DMA_ADDRESS,
 425         min_io_address:         DEFAULT_IO_BASE,
 426         min_mem_address:        APECS_AND_LCA_DEFAULT_MEM_BASE,
 427
 428         nr_irqs:                16,
 429         irq_probe_mask:         P2K_PROBE_MASK,
 430         update_irq_hw:          sio_update_irq_hw,
 431         ack_irq:                common_ack_irq,
 432         device_interrupt:       srm_device_interrupt,
 433
 434         init_arch:              lca_init_arch,
 435         init_irq:               sio_init_irq,
 436         init_pit:               common_init_pit,
 437         init_pci:               noname_init_pci,
 438         kill_arch:              common_kill_arch,
 439         pci_map_irq:            p2k_map_irq,
 440         pci_swizzle:            common_swizzle,
 441
 442         sys: { sio: {
 443                 route_tab:      0x0b0a090f,
 444         }}
 445 };
 446 ALIAS_MV(p2k)
 447 #endif
 448
 449 #if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_XL)
 450 struct alpha_machine_vector xl_mv __initmv = {
 451         vector_name:            "XL",
 452         DO_EV4_MMU,
 453         DO_DEFAULT_RTC,
 454         DO_APECS_IO,
 455         BUS(apecs_xl),
 456         machine_check:          apecs_machine_check,
 457         max_dma_address:        ALPHA_XL_MAX_DMA_ADDRESS,
 458         min_io_address:         DEFAULT_IO_BASE,
 459         min_mem_address:        XL_DEFAULT_MEM_BASE,
 460
 461         nr_irqs:                16,
 462         irq_probe_mask:         _PROBE_MASK(16),
 463         update_irq_hw:          sio_update_irq_hw,
 464         ack_irq:                common_ack_irq,
 465         device_interrupt:       isa_device_interrupt,
 466
 467         init_arch:              xl_init_arch,
 468         init_irq:               sio_init_irq,
 469         init_pit:               common_init_pit,
 470         init_pci:               noname_init_pci,
 471         kill_arch:              common_kill_arch,
 472         pci_map_irq:            noname_map_irq,
 473         pci_swizzle:            common_swizzle,
 474
 475         sys: { sio: {
 476                 route_tab:      0x0b0a090f,
 477         }}
 478 };
 479 ALIAS_MV(xl)
 480 #endif