arch/alpha/kernel/core_pyxis.c

   1 /*
   2  *      linux/arch/alpha/kernel/core_pyxis.c
   3  *
   4  * Based on code written by David A Rusling (david.rusling@reo.mts.dec.com).
   5  *
   6  * Code common to all PYXIS core logic chips.
   7  */
   8
   9 #include <linux/config.h>
  10 #include <linux/kernel.h>
  11 #include <linux/types.h>
  12 #include <linux/pci.h>
  13 #include <linux/sched.h>
  14 #include <linux/init.h>
  15
  16 #include <asm/ptrace.h>
  17 #include <asm/system.h>
  18 #include <asm/pci.h>
  19
  20 #define __EXTERN_INLINE inline
  21 #include <asm/io.h>
  22 #include <asm/core_pyxis.h>
  23 #undef __EXTERN_INLINE
  24
  25 #include "proto.h"
  26 #include "pci_impl.h"
  27
  28
  29 /* NOTE: Herein are back-to-back mb instructions.  They are magic.
  30    One plausible explanation is that the I/O controller does not properly
  31    handle the system transaction.  Another involves timing.  Ho hum.  */
  32
  33 /*
  34  * BIOS32-style PCI interface:
  35  */
  36
  37 #define DEBUG_CONFIG 0
  38
  39 #if DEBUG_CONFIG
  40 # define DBG_CNF(args)  printk args
  41 #else
  42 # define DBG_CNF(args)
  43 #endif
  44
  45
  46 /*
  47  * Given a bus, device, and function number, compute resulting
  48  * configuration space address and setup the PYXIS_HAXR2 register
  49  * accordingly.  It is therefore not safe to have concurrent
  50  * invocations to configuration space access routines, but there
  51  * really shouldn't be any need for this.
  52  *
  53  * Type 0:
  54  *
  55  *  3 3|3 3 2 2|2 2 2 2|2 2 2 2|1 1 1 1|1 1 1 1|1 1
  56  *  3 2|1 0 9 8|7 6 5 4|3 2 1 0|9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0
  57  * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
  58  * | | |D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|F|F|F|R|R|R|R|R|R|0|0|
  59  * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
  60  *
  61  *      31:11   Device select bit.
  62  *      10:8    Function number
  63  *       7:2    Register number
  64  *
  65  * Type 1:
  66  *
  67  *  3 3|3 3 2 2|2 2 2 2|2 2 2 2|1 1 1 1|1 1 1 1|1 1
  68  *  3 2|1 0 9 8|7 6 5 4|3 2 1 0|9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0
  69  * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
  70  * | | | | | | | | | | |B|B|B|B|B|B|B|B|D|D|D|D|D|F|F|F|R|R|R|R|R|R|0|1|
  71  * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
  72  *
  73  *      31:24   reserved
  74  *      23:16   bus number (8 bits = 128 possible buses)
  75  *      15:11   Device number (5 bits)
  76  *      10:8    function number
  77  *       7:2    register number
  78  *
  79  * Notes:
  80  *      The function number selects which function of a multi-function device
  81  *      (e.g., SCSI and Ethernet).
  82  *
  83  *      The register selects a DWORD (32 bit) register offset.  Hence it
  84  *      doesn't get shifted by 2 bits as we want to "drop" the bottom two
  85  *      bits.
  86  */
  87
  88 static int
  89 mk_conf_addr(struct pci_dev *dev, int where, unsigned long *pci_addr,
  90              unsigned char *type1)
  91 {
  92         u8 bus = dev->bus->number;
  93         u8 device_fn = dev->devfn;
  94
  95         *type1 = (bus == 0) ? 0 : 1;
  96         *pci_addr = (bus << 16) | (device_fn << 8) | (where);
  97
  98         DBG_CNF(("mk_conf_addr(bus=%d ,device_fn=0x%x, where=0x%x,"
  99                  " returning address 0x%p\n"
 100                  bus, device_fn, where, *pci_addr));
 101
 102         return 0;
 103 }
 104
 105 static unsigned int
 106 conf_read(unsigned long addr, unsigned char type1)
 107 {
 108         unsigned long flags;
 109         unsigned int stat0, value, temp;
 110         unsigned int pyxis_cfg = 0;
 111
 112         __save_and_cli(flags);  /* avoid getting hit by machine check */
 113
 114         /* Reset status register to avoid losing errors.  */
 115         stat0 = *(vuip)PYXIS_ERR;
 116         *(vuip)PYXIS_ERR = stat0; mb();
 117         temp = *(vuip)PYXIS_ERR;  /* re-read to force write */
 118
 119         /* If Type1 access, must set PYXIS CFG.  */
 120         if (type1) {
 121                 pyxis_cfg = *(vuip)PYXIS_CFG;
 122                 *(vuip)PYXIS_CFG = (pyxis_cfg & ~3L) | 1; mb();
 123                 temp = *(vuip)PYXIS_CFG;  /* re-read to force write */
 124         }
 125
 126         mb();
 127         draina();
 128         mcheck_expected(0) = 1;
 129         mcheck_taken(0) = 0;
 130         mb();
 131
 132         /* Access configuration space.  */
 133         value = *(vuip)addr;
 134         mb();
 135         mb();  /* magic */
 136
 137         if (mcheck_taken(0)) {
 138                 mcheck_taken(0) = 0;
 139                 value = 0xffffffffU;
 140                 mb();
 141         }
 142         mcheck_expected(0) = 0;
 143         mb();
 144
 145         /* If Type1 access, must reset IOC CFG so normal IO space ops work.  */
 146         if (type1) {
 147                 *(vuip)PYXIS_CFG = pyxis_cfg & ~3L; mb();
 148                 temp = *(vuip)PYXIS_CFG;  /* re-read to force write */
 149         }
 150
 151         __restore_flags(flags);
 152
 153         DBG_CNF(("conf_read(addr=0x%lx, type1=%d) = %#x\n",
 154                  addr, type1, value));
 155
 156         return value;
 157 }
 158
 159 static void
 160 conf_write(unsigned long addr, unsigned int value, unsigned char type1)
 161 {
 162         unsigned long flags;
 163         unsigned int stat0, temp;
 164         unsigned int pyxis_cfg = 0;
 165
 166         __save_and_cli(flags);  /* avoid getting hit by machine check */
 167
 168         /* Reset status register to avoid losing errors.  */
 169         stat0 = *(vuip)PYXIS_ERR;
 170         *(vuip)PYXIS_ERR = stat0; mb();
 171         temp = *(vuip)PYXIS_ERR;  /* re-read to force write */
 172
 173         /* If Type1 access, must set PYXIS CFG.  */
 174         if (type1) {
 175                 pyxis_cfg = *(vuip)PYXIS_CFG;
 176                 *(vuip)PYXIS_CFG = (pyxis_cfg & ~3L) | 1; mb();
 177                 temp = *(vuip)PYXIS_CFG;  /* re-read to force write */
 178         }
 179
 180         mb();
 181         draina();
 182         mcheck_expected(0) = 1;
 183         mcheck_taken(0) = 0;
 184         mb();
 185
 186         /* Access configuration space.  */
 187         *(vuip)addr = value;
 188         mb();
 189         temp = *(vuip)addr; /* read back to force the write */
 190         mcheck_expected(0) = 0;
 191         mb();
 192
 193         /* If Type1 access, must reset IOC CFG so normal IO space ops work.  */
 194         if (type1) {
 195                 *(vuip)PYXIS_CFG = pyxis_cfg & ~3L; mb();
 196                 temp = *(vuip)PYXIS_CFG;  /* re-read to force write */
 197         }
 198
 199         __restore_flags(flags);
 200
 201         DBG_CNF(("conf_write(addr=%#lx, value=%#x, type1=%d)\n",
 202                  addr, value, type1));
 203 }
 204
 205 static int
 206 pyxis_read_config_byte(struct pci_dev *dev, int where, u8 *value)
 207 {
 208         unsigned long addr, pci_addr;
 209         unsigned char type1;
 210
 211         if (mk_conf_addr(dev, where, &pci_addr, &type1))
 212                 return PCIBIOS_DEVICE_NOT_FOUND;
 213
 214         addr = (pci_addr << 5) + 0x00 + PYXIS_CONF;
 215         *value = conf_read(addr, type1) >> ((where & 3) * 8);
 216         return PCIBIOS_SUCCESSFUL;
 217 }
 218
 219 static int
 220 pyxis_read_config_word(struct pci_dev *dev, int where, u16 *value)
 221 {
 222         unsigned long addr, pci_addr;
 223         unsigned char type1;
 224
 225         if (mk_conf_addr(dev, where, &pci_addr, &type1))
 226                 return PCIBIOS_DEVICE_NOT_FOUND;
 227
 228         addr = (pci_addr << 5) + 0x08 + PYXIS_CONF;
 229         *value = conf_read(addr, type1) >> ((where & 3) * 8);
 230         return PCIBIOS_SUCCESSFUL;
 231 }
 232
 233 static int
 234 pyxis_read_config_dword(struct pci_dev *dev, int where, u32 *value)
 235 {
 236         unsigned long addr, pci_addr;
 237         unsigned char type1;
 238
 239         if (mk_conf_addr(dev, where, &pci_addr, &type1))
 240                 return PCIBIOS_DEVICE_NOT_FOUND;
 241
 242         addr = (pci_addr << 5) + 0x18 + PYXIS_CONF;
 243         *value = conf_read(addr, type1);
 244         return PCIBIOS_SUCCESSFUL;
 245 }
 246
 247 static int
 248 pyxis_write_config(struct pci_dev *dev, int where, u32 value, long mask)
 249 {
 250         unsigned long addr, pci_addr;
 251         unsigned char type1;
 252
 253         if (mk_conf_addr(dev, where, &pci_addr, &type1))
 254                 return PCIBIOS_DEVICE_NOT_FOUND;
 255
 256         addr = (pci_addr << 5) + mask + PYXIS_CONF;
 257         conf_write(addr, value << ((where & 3) * 8), type1);
 258         return PCIBIOS_SUCCESSFUL;
 259 }
 260
 261 static int
 262 pyxis_write_config_byte(struct pci_dev *dev, int where, u8 value)
 263 {
 264         return pyxis_write_config(dev, where, value, 0x00);
 265 }
 266
 267 static int
 268 pyxis_write_config_word(struct pci_dev *dev, int where, u16 value)
 269 {
 270         return pyxis_write_config(dev, where, value, 0x08);
 271 }
 272
 273 static int
 274 pyxis_write_config_dword(struct pci_dev *dev, int where, u32 value)
 275 {
 276         return pyxis_write_config(dev, where, value, 0x18);
 277 }
 278
 279 struct pci_ops pyxis_pci_ops =
 280 {
 281         read_byte:      pyxis_read_config_byte,
 282         read_word:      pyxis_read_config_word,
 283         read_dword:     pyxis_read_config_dword,
 284         write_byte:     pyxis_write_config_byte,
 285         write_word:     pyxis_write_config_word,
 286         write_dword:    pyxis_write_config_dword
 287 };
 288 \f
 289 void __init
 290 pyxis_init_arch(unsigned long *mem_start, unsigned long *mem_end)
 291 {
 292         struct pci_controler *hose;
 293         unsigned int temp;
 294
 295 #if 0
 296         printk("pyxis_init: PYXIS_ERR_MASK 0x%x\n", *(vuip)PYXIS_ERR_MASK);
 297         printk("pyxis_init: PYXIS_ERR 0x%x\n", *(vuip)PYXIS_ERR);
 298         printk("pyxis_init: PYXIS_INT_REQ 0x%lx\n", *(vulp)PYXIS_INT_REQ);
 299         printk("pyxis_init: PYXIS_INT_MASK 0x%lx\n", *(vulp)PYXIS_INT_MASK);
 300         printk("pyxis_init: PYXIS_INT_ROUTE 0x%lx\n", *(vulp)PYXIS_INT_ROUTE);
 301         printk("pyxis_init: PYXIS_INT_HILO 0x%lx\n", *(vulp)PYXIS_INT_HILO);
 302         printk("pyxis_init: PYXIS_INT_CNFG 0x%x\n", *(vuip)PYXIS_INT_CNFG);
 303         printk("pyxis_init: PYXIS_RT_COUNT 0x%lx\n", *(vulp)PYXIS_RT_COUNT);
 304 #endif
 305
 306         /*
 307          * Set up error reporting. Make sure CPU_PE is OFF in the mask.
 308          */
 309         temp = *(vuip)PYXIS_ERR_MASK;
 310         temp &= ~4;
 311         *(vuip)PYXIS_ERR_MASK = temp; mb();
 312         temp = *(vuip)PYXIS_ERR_MASK; /* re-read to force write */
 313
 314         temp = *(vuip)PYXIS_ERR ;
 315         temp |= 0x180;   /* master/target abort */
 316         *(vuip)PYXIS_ERR = temp; mb();
 317         temp = *(vuip)PYXIS_ERR; /* re-read to force write */
 318
 319         /*
 320          * Set up the PCI->physical memory translation windows.
 321          * For now, windows 2 and 3 are disabled.  In the future, we may
 322          * want to use them to do scatter/gather DMA.
 323          *
 324          * Window 0 goes at 2 GB and is 1 GB large.
 325          * Window 1 goes at 3 GB and is 1 GB large.
 326          */
 327
 328         *(vuip)PYXIS_W0_BASE = PYXIS_DMA_WIN0_BASE_DEFAULT | 1U;
 329         *(vuip)PYXIS_W0_MASK = (PYXIS_DMA_WIN0_SIZE_DEFAULT - 1) & 0xfff00000U;
 330         *(vuip)PYXIS_T0_BASE = PYXIS_DMA_WIN0_TRAN_DEFAULT >> 2;
 331
 332         *(vuip)PYXIS_W1_BASE = PYXIS_DMA_WIN1_BASE_DEFAULT | 1U;
 333         *(vuip)PYXIS_W1_MASK = (PYXIS_DMA_WIN1_SIZE_DEFAULT - 1) & 0xfff00000U;
 334         *(vuip)PYXIS_T1_BASE = PYXIS_DMA_WIN1_TRAN_DEFAULT >> 2;
 335
 336         *(vuip)PYXIS_W2_BASE = 0x0;
 337         *(vuip)PYXIS_W3_BASE = 0x0;
 338         mb();
 339
 340         /*
 341          * Next, clear the PYXIS_CFG register, which gets used
 342          *  for PCI Config Space accesses. That is the way
 343          *  we want to use it, and we do not want to depend on
 344          *  what ARC or SRM might have left behind...
 345          */
 346         {
 347                 unsigned int pyxis_cfg, temp;
 348                 pyxis_cfg = *(vuip)PYXIS_CFG; mb();
 349                 if (pyxis_cfg != 0) {
 350 #if 1
 351                         printk("PYXIS_init: CFG was 0x%x\n", pyxis_cfg);
 352 #endif
 353                         *(vuip)PYXIS_CFG = 0; mb();
 354                         temp = *(vuip)PYXIS_CFG;  /* re-read to force write */
 355                 }
 356         }
 357
 358         /* Zero the HAE.  */
 359         *(vuip)PYXIS_HAE_MEM = 0U; mb();
 360         *(vuip)PYXIS_HAE_MEM; /* re-read to force write */
 361         *(vuip)PYXIS_HAE_IO = 0; mb();
 362         *(vuip)PYXIS_HAE_IO;  /* re-read to force write */
 363
 364         /*
 365          * Finally, check that the PYXIS_CTRL1 has IOA_BEN set for
 366          * enabling byte/word PCI bus space(s) access.
 367          */
 368         {
 369                 unsigned int ctrl1;
 370                 ctrl1 = *(vuip) PYXIS_CTRL1;
 371                 if (!(ctrl1 & 1)) {
 372 #if 1
 373                         printk("PYXIS_init: enabling byte/word PCI space\n");
 374 #endif
 375                         *(vuip) PYXIS_CTRL1 = ctrl1 | 1; mb();
 376                         ctrl1 = *(vuip)PYXIS_CTRL1;  /* re-read */
 377                 }
 378         }
 379
 380         /*
 381          * Create our single hose.
 382          */
 383
 384         hose = alloc_pci_controler(mem_start);
 385         hose->io_space = &ioport_resource;
 386         hose->mem_space = &iomem_resource;
 387         hose->config_space = PYXIS_CONF;
 388         hose->index = 0;
 389 }
 390
 391 static inline void
 392 pyxis_pci_clr_err(void)
 393 {
 394         *(vuip)PYXIS_ERR;
 395         *(vuip)PYXIS_ERR = 0x0180;
 396         mb();
 397         *(vuip)PYXIS_ERR;  /* re-read to force write */
 398 }
 399
 400 void
 401 pyxis_machine_check(unsigned long vector, unsigned long la_ptr,
 402                     struct pt_regs * regs)
 403 {
 404         /* Clear the error before reporting anything.  */
 405         mb();
 406         mb();  /* magic */
 407         draina();
 408         pyxis_pci_clr_err();
 409         wrmces(0x7);
 410         mb();
 411
 412         process_mcheck_info(vector, la_ptr, regs, "PYXIS", mcheck_expected(0));
 413 }