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Import 2.3.49pre1
[davej-history.git] / drivers / video / rivafb.c
blobc48f7a08a5cc6a33ff2b0e755ab9e88d3bbb344d
1 /*
2 * linux/drivers/video/rivafb.c - nVidia RIVA 128/TNT/TNT2 fb driver
3 *
4 * Copyright 1999 Jeff Garzik <jgarzik@mandrakesoft.com>
5 *
6 * Contributors:
7 *
8 * ani joshi: Lots of debugging and cleanup work, really helped
9 * get the driver going
10 *
11 * Initial template from skeletonfb.c, created 28 Dec 1997 by Geert Uytterhoeven
12 * Includes riva_hw.c from nVidia, see copyright below.
13 * KGI code provided the basis for state storage, init, and mode switching.
14 *
15 * This file is subject to the terms and conditions of the GNU General Public
16 * License. See the file COPYING in the main directory of this archive
17 * for more details.
18 */
19
20 /* version number of this driver */
21 #define RIVAFB_VERSION "0.6.5"
22
23 #include <linux/config.h>
24 #include <linux/module.h>
25 #include <linux/kernel.h>
26 #include <linux/errno.h>
27 #include <linux/string.h>
28 #include <linux/mm.h>
29 #include <linux/selection.h>
30 #include <linux/tty.h>
31 #include <linux/malloc.h>
32 #include <linux/delay.h>
33 #include <linux/fb.h>
34 #include <linux/init.h>
35 #include <linux/pci.h>
36
37 #include <video/fbcon.h>
38
39 #include "riva_hw.h"
40 #include "nv4ref.h"
41 #include "nvreg.h"
42 #include "vga.h"
43 #include <video/fbcon-cfb4.h>
44 #include <video/fbcon-cfb8.h>
45 #include <video/fbcon-cfb16.h>
46 #include <video/fbcon-cfb32.h>
47
48 #ifndef CONFIG_PCI /* sanity check */
49 #error This driver requires PCI support.
50 #endif
51
52 /*****************************************************************
53 *
54 * various helpful macros and constants
55 *
56 */
57
58 /* #define RIVAFBDEBUG */
59 #ifdef RIVAFBDEBUG
60 #define DPRINTK(fmt, args...) printk(KERN_DEBUG "%s: " fmt, __FUNCTION__ , ## args)
61 #else
62 #define DPRINTK(fmt, args...)
63 #endif
64
65 #ifndef RIVA_NDEBUG
66 #define assert(expr) \
67 if(!(expr)) { \
68 printk( "Assertion failed! %s,%s,%s,line=%d\n",\
69 #expr,__FILE__,__FUNCTION__,__LINE__); \
70 *(int*)0 = 0; \
71 }
72 #else
73 #define assert(expr)
74 #endif
75
76 /* GGI compatibility macros */
77 #define io_out8 outb
78 #define io_in8 inb
79 #define FatalError panic
80 #define NUM_SEQ_REGS 0x05
81 #define NUM_CRT_REGS 0x41
82 #define NUM_GRC_REGS 0x09
83 #define NUM_ATC_REGS 0x15
84
85 /* max number of VGA controllers we scan for */
86 #define RIVA_MAX_VGA_CONTROLLERS 8
87
88 #define PFX "rivafb: "
89
90 #define CNVT_TOHW(val,width) ((((val)<<(width))+0x7FFF-(val))>>16)
91
92 /* macro that allows you to set overflow bits */
93 #define SetBitField(value,from,to) SetBF(to,GetBF(value,from))
94 #define SetBit(n) (1<<(n))
95 #define Set8Bits(value) ((value)&0xff)
96
97 struct riva_chip_info {
98 const char *name;
99 unsigned arch_rev;
100 unsigned short vendor;
101 unsigned short device;
102 };
103
104
105 static const struct riva_chip_info riva_pci_probe_list[] =
106 {
107 {"RIVA-128", 3, PCI_VENDOR_ID_NVIDIA_SGS, PCI_DEVICE_ID_NVIDIA_SGS_RIVA128},
108 {"RIVA-TNT", 4, PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_TNT},
109 {"RIVA-TNT2", 5, PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_TNT2},
110 {"RIVA-TNT2", 5, PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_UTNT2},
111 {"RIVA-TNT2", 5, PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_VTNT2},
112 {"RIVA-TNT2", 5, PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_ITNT2},
113 {NULL, 0, 0, 0}
114 };
115
116
117 /* holds the state of the VGA core and extended Riva hw state from riva_hw.c.
118 * From KGI originally. */
119 struct riva_regs {
120 u8 attr[0x15];
121 u8 crtc[0x41];
122 u8 gra[0x09];
123 u8 seq[0x05];
124 u8 misc_output;
125 RIVA_HW_STATE ext;
126 };
127
128
129 /*
130 * describes the state of a Riva board
131 */
132 struct rivafb_par {
133 struct riva_regs state; /* state of hw board */
134 __u32 visual; /* FB_VISUAL_xxx */
135 unsigned depth; /* bpp of current mode */
136 };
137
138 typedef struct {
139 unsigned char red, green, blue, transp;
140 } riva_cfb8_cmap_t;
141
142
143
144 struct rivafb_info;
145 struct rivafb_info {
146 struct fb_info info; /* kernel framebuffer info */
147
148 RIVA_HW_INST riva; /* interface to riva_hw.c */
149
150 const char *drvr_name; /* Riva hardware board type */
151
152 unsigned long ctrl_base_phys; /* physical control register base addr */
153 unsigned long fb_base_phys; /* physical framebuffer base addr */
154
155 caddr_t ctrl_base; /* virtual control register base addr */
156 caddr_t fb_base; /* virtual framebuffer base addr */
157
158 unsigned ram_amount; /* amount of RAM on card, in megabytes */
159 unsigned dclk_max; /* max DCLK */
160
161 struct riva_regs initial_state; /* initial startup video mode */
162
163 struct display disp;
164 int currcon;
165 struct display *currcon_display;
166
167 struct rivafb_info *next;
168
169 struct pci_dev *pd; /* pointer to board's pci info */
170 unsigned base0_region_size; /* size of control register region */
171 unsigned base1_region_size; /* size of framebuffer region */
172
173 #ifdef FBCON_HAS_CFB8
174 riva_cfb8_cmap_t palette[256]; /* VGA DAC palette cache */
175 #endif
176
177 #if defined(FBCON_HAS_CFB16) || defined(FBCON_HAS_CFB32)
178 union {
179 #ifdef FBCON_HAS_CFB16
180 u_int16_t cfb16[16];
181 #endif
182 #ifdef FBCON_HAS_CFB32
183 u_int32_t cfb32[16];
184 #endif
185 } con_cmap;
186 #endif /* FBCON_HAS_CFB16 | FBCON_HAS_CFB32 */
187 };
188
189 /* ------------------- global variables ------------------------ */
190
191
192 static struct rivafb_info *riva_boards = NULL;
193
194 /* command line data, set in rivafb_setup() */
195 static char fontname[40] __initdata = { 0 };
196 static char noaccel __initdata = 0; /* unused */
197 #ifndef MODULE
198 static const char *mode_option __initdata = NULL;
199 #endif
200
201
202 /* ------------------- prototypes ------------------------------ */
203
204 int rivafb_open (struct fb_info *info, int user);
205 int rivafb_release (struct fb_info *info, int user);
206 int rivafb_get_fix (struct fb_fix_screeninfo *fix, int con,
207 struct fb_info *info);
208 int rivafb_get_var (struct fb_var_screeninfo *var, int con,
209 struct fb_info *info);
210 int rivafb_set_var (struct fb_var_screeninfo *var, int con,
211 struct fb_info *info);
212 int rivafb_get_cmap (struct fb_cmap *cmap, int kspc, int con,
213 struct fb_info *info);
214 int rivafb_set_cmap (struct fb_cmap *cmap, int kspc, int con,
215 struct fb_info *info);
216 int rivafb_pan_display (struct fb_var_screeninfo *var, int con,
217 struct fb_info *info);
218 int rivafb_ioctl (struct inode *inode, struct file *file, unsigned int cmd,
219 unsigned long arg, int con, struct fb_info *info);
220 int rivafb_switch(int con, struct fb_info *info);
221 void rivafb_blank (int blank, struct fb_info *info);
222
223 static void riva_load_video_mode (struct rivafb_info *rivainfo,
224 struct fb_var_screeninfo *video_mode);
225 static int riva_getcolreg (unsigned regno, unsigned *red, unsigned *green,
226 unsigned *blue, unsigned *transp,
227 struct fb_info *info);
228 static int riva_setcolreg (unsigned regno, unsigned red, unsigned green,
229 unsigned blue, unsigned transp,
230 struct fb_info *info);
231 static int riva_get_cmap_len(const struct fb_var_screeninfo *var);
232
233 static u32 riva_pci_region_size (struct pci_dev *pd, unsigned baseaddr);
234
235 static void riva_pci_iounmap (struct rivafb_info *rinfo);
236 static int riva_pci_register (struct pci_dev *pd, const struct riva_chip_info *rci);
237 static int riva_pci_register_devices (void);
238 static int riva_set_fbinfo (struct rivafb_info *rinfo);
239
240 static
241 void riva_save_state(struct rivafb_info *rinfo, struct riva_regs *regs);
242 static
243 void riva_load_state(struct rivafb_info *rinfo, struct riva_regs *regs);
244 static
245 struct rivafb_info *riva_board_list_add(struct rivafb_info *board_list,
246 struct rivafb_info *new_node);
247
248 #if 0
249 static void riva_pci_region_init (struct pci_dev *pd, struct rivafb_info *rinfo);
250 #endif
251
252 static void riva_wclut (unsigned char regnum, unsigned char red,
253 unsigned char green, unsigned char blue);
254
255
256
257
258 /* kernel interface */
259 static struct fb_ops riva_fb_ops =
260 {
261 rivafb_open,
262 rivafb_release,
263 rivafb_get_fix,
264 rivafb_get_var,
265 rivafb_set_var,
266 rivafb_get_cmap,
267 rivafb_set_cmap,
268 rivafb_pan_display,
269 rivafb_ioctl
270 };
271
272
273
274
275 /* from GGI */
276 static const struct riva_regs reg_template =
277 {
278 { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, /* ATTR */
279 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F,
280 0x41, 0x01, 0x0F, 0x13, 0x00 },
281 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* CRT */
282 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00,
283 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE3, /* 0x10 */
284 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
285 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0x20 */
286 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
287 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0x30 */
288 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
289 0x00, /* 0x40 */
290 },
291 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x05, 0x0F, /* GRA */
292 0xFF },
293 { 0x03, 0x01, 0x0F, 0x00, 0x0E}, /* SEQ */
294 0xEB /* MISC */
295 };
296
297
298
299 /* ------------------- general utility functions -------------------------- */
300
301 /**
302 * riva_set_dispsw
303 * @rivainfo: pointer to internal driver struct for a given Riva card
304 *
305 * DESCRIPTION:
306 * Sets up console Low level operations depending on the current? color depth
307 * of the display
308 */
309
310 void riva_set_dispsw (struct rivafb_info *rinfo)
311 {
312 struct display *disp = &rinfo->disp;
313
314 DPRINTK ("ENTER\n");
315
316 assert (rinfo != NULL);
317
318 disp->dispsw_data = NULL;
319
320 switch (disp->var.bits_per_pixel) {
321 #ifdef FBCON_HAS_MFB
322 case 1:
323 disp->dispsw = &fbcon_mfb;
324 break;
325 #endif
326 #ifdef FBCON_HAS_CFB4
327 case 4:
328 disp->dispsw = &fbcon_cfb4;
329 break;
330 #endif
331 #ifdef FBCON_HAS_CFB8
332 case 8:
333 disp->dispsw = &fbcon_cfb8;
334 break;
335 #endif
336 #ifdef FBCON_HAS_CFB16
337 case 15:
338 case 16:
339 disp->dispsw = &fbcon_cfb16;
340 disp->dispsw_data = &rinfo->con_cmap.cfb16;
341 break;
342 #endif
343 #ifdef FBCON_HAS_CFB24
344 case 24:
345 disp->dispsw = &fbcon_cfb24;
346 disp->dispsw_data = rinfo->con_cmap.cfb24;
347 break;
348 #endif
349 #ifdef FBCON_HAS_CFB32
350 case 32:
351 disp->dispsw = &fbcon_cfb32;
352 disp->dispsw_data = rinfo->con_cmap.cfb32;
353 break;
354 #endif
355 default:
356 DPRINTK ("Setting fbcon_dummy renderer\n");
357 disp->dispsw = &fbcon_dummy;
358 }
359
360 DPRINTK ("EXIT\n");
361 }
362
363
364
365
366 static int riva_init_disp_var (struct rivafb_info *rinfo)
367 {
368 if (mode_option)
369 fb_find_mode(&rinfo->disp.var, &rinfo->info, mode_option,
370 NULL, 0, NULL, 8);
371 else
372 fb_find_mode(&rinfo->disp.var, &rinfo->info,
373 "640x480-8@60", NULL, 0, NULL, 8);
374 return 0;
375 }
376
377
378
379
380 static int __init riva_init_disp (struct rivafb_info *rinfo)
381 {
382 struct fb_info *info;
383 struct display *disp;
384
385 DPRINTK("ENTER\n");
386
387 assert (rinfo != NULL);
388
389 info = &rinfo->info;
390 disp = &rinfo->disp;
391
392 info->disp = disp;
393
394 #warning FIXME: assure that disp->cmap is completely filled out
395
396 disp->screen_base = rinfo->fb_base;
397 disp->visual = FB_VISUAL_PSEUDOCOLOR;
398 disp->type = FB_TYPE_PACKED_PIXELS;
399 disp->type_aux = 0;
400 disp->ypanstep = 1;
401 disp->ywrapstep = 0;
402 disp->next_line = disp->line_length =
403 (disp->var.xres_virtual * disp->var.bits_per_pixel) >> 3;
404 disp->can_soft_blank = 1;
405 disp->inverse = 0;
406
407 riva_set_dispsw(rinfo);
408
409 rinfo->currcon_display = disp;
410
411 if ((riva_init_disp_var (rinfo)) < 0) { /* must be done last */
412 DPRINTK("EXIT, returning -1\n");
413 return -1;
414 }
415
416 DPRINTK("EXIT, returning 0\n");
417 return 0;
418
419 }
420
421
422
423 static int __init riva_set_fbinfo (struct rivafb_info *rinfo)
424 {
425 struct fb_info *info;
426
427 assert (rinfo != NULL);
428
429 info = &rinfo->info;
430
431 strcpy (info->modename, rinfo->drvr_name);
432 info->node = -1;
433 info->flags = FBINFO_FLAG_DEFAULT;
434 info->fbops = &riva_fb_ops;
435
436 #warning FIXME: set monspecs to what???
437
438 info->display_fg = NULL; /* FIXME: correct? */
439 strncpy (info->fontname, fontname, sizeof (info->fontname));
440 info->fontname[sizeof (info->fontname) - 1] = 0;
441
442 info->changevar = NULL; /* FIXME: needed? */
443 info->switch_con = rivafb_switch;
444 info->updatevar = NULL; /* FIXME? */
445 info->blank = rivafb_blank;
446
447 if (riva_init_disp (rinfo) < 0) /* must be done last */
448 return -1;
449
450 return 0;
451 }
452
453
454
455
456 /* ----------------------------- PCI bus ----------------------------- */
457
458
459
460
461 /**
462 * riva_pci_region_size
463 * @pd: pointer to PCI device to be configured
464 *
465 * DESCRIPTION:
466 * Obtains from the PCI bus the size of the address space allocated to
467 * the given card's base address zero region.
468 */
469
470 static
471 u32 riva_pci_region_size (struct pci_dev *pd, unsigned baseaddr)
472 {
473 return pd->resource[baseaddr].end - pd->resource[baseaddr].start + 1;
474 }
475
476
477
478
479 #if 0
480
481 /**
482 * riva_pci_iomap
483 * @nv:
484 *
485 * DESCRIPTION:
486 */
487
488 static
489 void riva_pci_region_init (struct pci_dev *pd, struct rivafb_info *rinfo)
490 {
491 unsigned long addr;
492
493 assert (rinfo != NULL);
494 assert (pd != NULL);
495
496 rinfo->pd = pd;
497 rinfo->base0_region_size = riva_pci_region_size (pd, PCI_BASE_ADDRESS_0);
498 assert(rinfo->base0_region_size >= 0x00800000); /* from GGI */
499 rinfo->base1_region_size = riva_pci_region_size (pd, PCI_BASE_ADDRESS_1);
500 assert(rinfo->base0_region_size >= 0x01000000); /* from GGI */
501
502 /* Get the base addresses */
503 pcibios_read_config_dword(0, rinfo->pd->devfn, PCI_BASE_ADDRESS_0,
504 (unsigned int*)&addr);
505 #ifdef SHOULDUSETHAT
506 /* This function should return an int. */
507 if (!addr)
508 return -ENXIO;
509 #endif
510
511 rinfo->ctrl_base_phys = addr & PCI_BASE_ADDRESS_MEM_MASK;
512
513 pcibios_read_config_dword(0, rinfo->pd->devfn, PCI_BASE_ADDRESS_1,
514 (unsigned int*)&addr);
515
516 rinfo->fb_base_phys = addr & PCI_BASE_ADDRESS_MEM_MASK;
517
518 rinfo->ctrl_base = ioremap (rinfo->ctrl_base_phys, rinfo->base0_region_size);
519 assert (rinfo->ctrl_base != NULL);
520 rinfo->fb_base = ioremap (rinfo->fb_base_phys, rinfo->base1_region_size);
521 assert (rinfo->fb_base != NULL);
522
523 rinfo->riva.EnableIRQ = 0;
524 rinfo->riva.IO = (inb(0x3CC) & 0x01) ? 0x3D0 : 0x3B0;
525 rinfo->riva.PRAMDAC = (unsigned *)(rinfo->ctrl_base+0x00680000);
526 rinfo->riva.PFB = (unsigned *)(rinfo->ctrl_base+0x00100000);
527 rinfo->riva.PFIFO = (unsigned *)(rinfo->ctrl_base+0x00002000);
528 rinfo->riva.PGRAPH = (unsigned *)(rinfo->ctrl_base+0x00400000);
529 rinfo->riva.PEXTDEV = (unsigned *)(rinfo->ctrl_base+0x00101000);
530 rinfo->riva.PTIMER = (unsigned *)(rinfo->ctrl_base+0x00009000);
531 rinfo->riva.PMC = (unsigned *)(rinfo->ctrl_base+0x00000000);
532 rinfo->riva.FIFO = (unsigned *)(rinfo->ctrl_base+0x00800000);
533
534 switch (rinfo->riva.Architecture)
535 {
536 case 3:
537 rinfo->riva.PRAMIN = (unsigned *)(rinfo->ctrl_base+0x00C00000);
538 break;
539 case 4:
540 case 5:
541 rinfo->riva.PCRTC = (unsigned *)(rinfo->ctrl_base+0x00600000);
542 rinfo->riva.PRAMIN = (unsigned *)(rinfo->ctrl_base+0x00710000);
543 break;
544 }
545 }
546
547 #endif /* 0 */
548
549
550
551 /**
552 * riva_pci_iounmap
553 * @rinfo:
554 *
555 * DESCRIPTION:
556 */
557
558 static
559 void riva_pci_iounmap (struct rivafb_info *rinfo)
560 {
561 assert (rinfo != NULL);
562 assert (rinfo->ctrl_base_phys != 0x00000000);
563 assert (rinfo->ctrl_base != NULL);
564 assert (rinfo->fb_base_phys != 0x00000000);
565 assert (rinfo->fb_base != NULL);
566
567 iounmap (rinfo->ctrl_base);
568 iounmap (rinfo->fb_base);
569 }
570
571
572
573
574
575 static void __init riva_init_clut (struct rivafb_info *fb_info)
576 {
577 int j, k;
578
579 for (j = 0; j < 256; j++) {
580 if (j < 16) {
581 k = color_table[j];
582 fb_info->palette[j].red = default_red[k];
583 fb_info->palette[j].green = default_grn[k];
584 fb_info->palette[j].blue = default_blu[k];
585 } else {
586 fb_info->palette[j].red =
587 fb_info->palette[j].green =
588 fb_info->palette[j].blue = j;
589 }
590
591 riva_wclut (j,
592 fb_info->palette[j].red,
593 fb_info->palette[j].green,
594 fb_info->palette[j].blue);
595 }
596 }
597
598
599
600 static int __init riva_pci_register (struct pci_dev *pd,
601 const struct riva_chip_info *rci)
602 {
603 struct rivafb_info *rinfo;
604
605 assert (pd != NULL);
606 assert (rci != NULL);
607
608 rinfo = kmalloc (sizeof (struct rivafb_info), GFP_KERNEL);
609 assert (rinfo != NULL);
610 memset (rinfo, 0, sizeof (struct rivafb_info));
611
612 rinfo->drvr_name = rci->name;
613 rinfo->riva.Architecture = rci->arch_rev;
614
615 rinfo->pd = pd;
616 rinfo->base0_region_size = riva_pci_region_size (pd, 0);
617 rinfo->base1_region_size = riva_pci_region_size (pd, 1);
618
619 assert(rinfo->base0_region_size >= 0x00800000); /* from GGI */
620 assert(rinfo->base0_region_size >= 0x01000000); /* from GGI */
621
622 rinfo->ctrl_base_phys = rinfo->pd->resource[0].start;
623 rinfo->fb_base_phys = rinfo->pd->resource[1].start;
624
625 request_region(0x3C0, 32, "rivafb");
626
627 if (!request_mem_region(rinfo->ctrl_base_phys,
628 rinfo->base0_region_size, "rivafb") ||
629 !request_mem_region(rinfo->fb_base_phys, rinfo->base1_region_size,
630 "rivafb")) {
631 printk (KERN_ERR PFX "cannot reserve MMIO region\n");
632 return -ENXIO;
633 }
634
635 rinfo->ctrl_base = ioremap (rinfo->ctrl_base_phys,
636 rinfo->base0_region_size);
637 assert (rinfo->ctrl_base != NULL);
638
639 rinfo->fb_base = ioremap (rinfo->fb_base_phys,
640 rinfo->base1_region_size);
641 assert (rinfo->fb_base != NULL);
642
643 rinfo->riva.EnableIRQ = 0;
644 rinfo->riva.IO = (inb(0x3CC) & 0x01) ? 0x3D0 : 0x3B0;
645 rinfo->riva.PRAMDAC = (unsigned *)(rinfo->ctrl_base+0x00680000);
646 rinfo->riva.PFB = (unsigned *)(rinfo->ctrl_base+0x00100000);
647 rinfo->riva.PFIFO = (unsigned *)(rinfo->ctrl_base+0x00002000);
648 rinfo->riva.PGRAPH = (unsigned *)(rinfo->ctrl_base+0x00400000);
649 rinfo->riva.PEXTDEV = (unsigned *)(rinfo->ctrl_base+0x00101000);
650 rinfo->riva.PTIMER = (unsigned *)(rinfo->ctrl_base+0x00009000);
651 rinfo->riva.PMC = (unsigned *)(rinfo->ctrl_base+0x00000000);
652 rinfo->riva.FIFO = (unsigned *)(rinfo->ctrl_base+0x00800000);
653
654 switch (rinfo->riva.Architecture)
655 {
656 case 3:
657 rinfo->riva.PRAMIN = (unsigned *)(rinfo->ctrl_base+0x00C00000);
658 break;
659 case 4:
660 case 5:
661 rinfo->riva.PCRTC = (unsigned *)(rinfo->ctrl_base+0x00600000);
662 rinfo->riva.PRAMIN = (unsigned *)(rinfo->ctrl_base+0x00710000);
663 break;
664 }
665
666 RivaGetConfig(&rinfo->riva);
667
668 /* back to normal */
669
670 assert (rinfo->pd != NULL);
671
672 /* unlock io */
673 vga_io_wcrt (0x11, 0xFF); /* vgaHWunlock() + riva unlock (0x7F) */
674 outb(rinfo->riva.LockUnlockIO, rinfo->riva.LockUnlockIndex);
675 outb(rinfo->riva.LockUnlockIO + 1, 0x57);
676
677 memcpy (&rinfo->initial_state, &reg_template, sizeof (reg_template));
678 riva_save_state (rinfo, &rinfo->initial_state);
679
680 rinfo->ram_amount = rinfo->riva.RamAmountKBytes * 1024;
681 rinfo->dclk_max = rinfo->riva.MaxVClockFreqKHz * 1000;
682
683 riva_set_fbinfo (rinfo);
684
685 riva_init_clut (rinfo);
686
687 riva_load_video_mode (rinfo, &rinfo->disp.var);
688
689 if (register_framebuffer ((struct fb_info *) rinfo) < 0) {
690 printk(KERN_ERR PFX "error registering riva framebuffer\n");
691 kfree (rinfo);
692 return -1;
693 }
694
695 riva_boards = riva_board_list_add (riva_boards, rinfo);
696
697 printk("PCI Riva NV%d framebuffer ver %s (%s, %dMB @ 0x%lX)\n",
698 rinfo->riva.Architecture,
699 RIVAFB_VERSION,
700 rinfo->drvr_name,
701 rinfo->ram_amount / (1024 * 1024),
702 rinfo->fb_base_phys);
703
704 return 0;
705 }
706
707
708
709
710 static int __init riva_pci_register_devices (void)
711 {
712 struct pci_dev *pd;
713 const struct riva_chip_info *nci = &riva_pci_probe_list[0];
714
715 assert (nci != NULL);
716 while (nci->name != NULL) {
717 pd = pci_find_device (nci->vendor, nci->device, NULL);
718 while (pd != NULL) {
719 if (riva_pci_register (pd, nci) < 0)
720 return -1;
721
722 pd = pci_find_device (nci->vendor, nci->device, pd);
723 }
724
725 nci++;
726 }
727
728 return 0;
729 }
730
731
732
733 /*** riva_wclut - set CLUT entry ***/
734 static void riva_wclut (unsigned char regnum, unsigned char red,
735 unsigned char green, unsigned char blue)
736 {
737 unsigned int data = VGA_PEL_D;
738
739 /* address write mode register is not translated.. */
740 vga_io_w (VGA_PEL_IW, regnum);
741
742 vga_io_w (data, red);
743 vga_io_w (data, green);
744 vga_io_w (data, blue);
745 }
746
747
748
749 /* ------------ Hardware Independent Functions ------------ */
750
751 int __init rivafb_setup(char *options)
752 {
753 char *this_opt;
754
755 if (!options || !*options)
756 return 0;
757
758 for (this_opt = strtok(options, ","); this_opt;
759 this_opt = strtok(NULL, ",")) {
760 if (!strncmp(this_opt, "font:", 5)) {
761 char *p;
762 int i;
763
764 p = this_opt + 5;
765 for (i = 0; i < sizeof(fontname) - 1; i++)
766 if (!*p || *p == ' ' || *p == ',')
767 break;
768 memcpy(fontname, this_opt + 5, i);
769 fontname[i] = 0;
770 }
771
772 else if (!strncmp(this_opt, "noaccel", 7)) {
773 noaccel = 1;
774 }
775
776 else
777 mode_option = this_opt;
778 }
779 return 0;
780 }
781
782 /*
783 * Initialization
784 */
785
786 int __init rivafb_init (void)
787 {
788 if (riva_pci_register_devices () < 0)
789 return -ENXIO;
790
791 if (riva_boards == NULL)
792 return -ENODEV;
793
794 return 0;
795 }
796
797
798 /* ------------------------------------------------------------------------- */
799 /*
800 * Cleanup
801 */
802
803 void __exit rivafb_cleanup (struct fb_info *info)
804 {
805 #warning FIXME: is this all we need to do?
806
807 struct rivafb_info *tmp, *board = riva_boards;
808
809 while (board != NULL) {
810 riva_load_state (board, &board->initial_state);
811 riva_pci_iounmap (board);
812
813 unregister_framebuffer ((struct fb_info *) board);
814
815 tmp = board;
816 board = board->next;
817
818 kfree_s (tmp, sizeof (struct rivafb_info));
819 }
820
821 (void) info; /* unused function arg */
822 }
823
824
825
826
827 /*
828 * Frame buffer operations
829 */
830
831 int rivafb_open(struct fb_info *info, int user)
832 {
833 /* Nothing, only a usage count for the moment */
834 MOD_INC_USE_COUNT;
835 return 0;
836 }
837
838 int rivafb_release(struct fb_info *info, int user)
839 {
840 MOD_DEC_USE_COUNT;
841 return 0;
842 }
843
844
845 /**
846 * rivafb_get_fix
847 * @fix:
848 * @con:
849 * @info:
850 *
851 * DESCRIPTION:
852 */
853
854 int rivafb_get_fix (struct fb_fix_screeninfo *fix, int con,
855 struct fb_info *info)
856 {
857 struct rivafb_info *rivainfo = (struct rivafb_info *) info;
858 struct display *p;
859
860 DPRINTK ("ENTER\n");
861
862 assert (fix != NULL);
863 assert (info != NULL);
864 assert (rivainfo->drvr_name && rivainfo->drvr_name[0]);
865 assert (rivainfo->fb_base_phys > 0);
866 assert (rivainfo->ram_amount > 0);
867
868 p = (con < 0) ? rivainfo->info.disp : &fb_display[con];
869
870 memset (fix, 0, sizeof (struct fb_fix_screeninfo));
871 sprintf (fix->id, "Riva %s", rivainfo->drvr_name);
872
873 fix->smem_start = rivainfo->fb_base_phys;
874 fix->smem_len = rivainfo->ram_amount;
875
876 fix->type = p->type;
877 fix->type_aux = p->type_aux;
878 fix->visual = p->visual;
879
880 fix->xpanstep = 1;
881 fix->ypanstep = 1;
882 fix->ywrapstep = 0; /* FIXME: no ywrap for now */
883
884 fix->line_length = p->line_length;
885
886 #warning FIXME: set up MMIO region
887 fix->mmio_start = 0;
888 fix->mmio_len = 0;
889
890 #warning FIXME: reference riva acceleration fb.h constant here
891 fix->accel = FB_ACCEL_NONE;
892
893 DPRINTK ("EXIT, returning 0\n");
894
895 return 0;
896 }
897
898
899
900 /**
901 * rivafb_get_var
902 * @var:
903 * @con:
904 * @info:
905 *
906 * DESCRIPTION:
907 */
908
909 int rivafb_get_var (struct fb_var_screeninfo *var, int con,
910 struct fb_info *info)
911 {
912 struct rivafb_info *rivainfo = (struct rivafb_info *) info;
913
914 DPRINTK ("ENTER\n");
915
916 assert (info != NULL);
917 assert (var != NULL);
918
919 *var = (con < 0) ? rivainfo->disp.var : fb_display[con].var;
920
921 DPRINTK ("EXIT, returning 0\n");
922
923 return 0;
924 }
925
926
927
928 /**
929 * rivafb_set_var
930 * @var:
931 * @con:
932 * @info:
933 *
934 * DESCRIPTION:
935 */
936
937 int rivafb_set_var (struct fb_var_screeninfo *var, int con,
938 struct fb_info *info)
939 {
940 struct rivafb_info *rivainfo = (struct rivafb_info *) info;
941 struct display *dsp;
942 struct fb_var_screeninfo v;
943 int nom, den; /* translating from pixels->bytes */
944 int i;
945 unsigned chgvar = 0;
946 static struct {
947 int xres, yres;
948 } modes[] = {
949 { 1600, 1280 },
950 { 1280, 1024 },
951 { 1024, 768 },
952 { 800, 600 },
953 { 640, 480 },
954 { -1, -1 }
955 };
956
957 DPRINTK ("ENTER\n");
958
959 assert (info != NULL);
960 assert (var != NULL);
961
962 DPRINTK ("Requested: %dx%dx%d\n", var->xres, var->yres, var->bits_per_pixel);
963 DPRINTK (" virtual: %dx%d\n", var->xres_virtual, var->yres_virtual);
964 DPRINTK (" offset: (%d,%d)\n", var->xoffset, var->yoffset);
965 DPRINTK ("grayscale: %d\n", var->grayscale);
966
967 dsp = (con < 0) ? rivainfo->info.disp : &fb_display[con];
968 assert (dsp != NULL);
969
970 /* if var has changed, we should call changevar() later */
971 if (con >= 0) {
972 chgvar = ((dsp->var.xres != var->xres) ||
973 (dsp->var.yres != var->yres) ||
974 (dsp->var.xres_virtual != var->xres_virtual) ||
975 (dsp->var.yres_virtual != var->yres_virtual) ||
976 (dsp->var.bits_per_pixel != var->bits_per_pixel) ||
977 memcmp(&dsp->var.red, &var->red, sizeof(var->red)) ||
978 memcmp(&dsp->var.green, &var->green, sizeof(var->green)) ||
979 memcmp(&dsp->var.blue, &var->blue, sizeof(var->blue)));
980 }
981
982 memcpy (&v, var, sizeof (v));
983
984 switch (v.bits_per_pixel) {
985 #ifdef FBCON_HAS_MFB
986 case 1:
987 dsp->dispsw = &fbcon_mfb;
988 dsp->line_length = v.xres_virtual / 8;
989 dsp->visual = FB_VISUAL_MONO10;
990 nom = 4;
991 den = 8;
992 break;
993 #endif
994
995 #ifdef FBCON_HAS_CFB8
996 case 2 ... 8:
997 v.bits_per_pixel = 8;
998 dsp->dispsw = &fbcon_cfb8;
999 nom = 1;
1000 den = 1;
1001 dsp->line_length = v.xres_virtual;
1002 dsp->visual = FB_VISUAL_PSEUDOCOLOR;
1003 v.red.offset = 0;
1004 v.red.length = 6;
1005 v.green.offset = 0;
1006 v.green.length = 6;
1007 v.blue.offset = 0;
1008 v.blue.length = 6;
1009 break;
1010 #endif
1011
1012 #ifdef FBCON_HAS_CFB16
1013 case 9 ... 16:
1014 v.bits_per_pixel = 16;
1015 dsp->dispsw = &fbcon_cfb16;
1016 dsp->dispsw_data = &rivainfo->con_cmap.cfb16;
1017 nom = 2;
1018 den = 1;
1019 dsp->line_length = v.xres_virtual * 2;
1020 dsp->visual = FB_VISUAL_DIRECTCOLOR;
1021 #ifdef CONFIG_PREP
1022 v.red.offset = 2;
1023 v.green.offset = -3;
1024 v.blue.offset = 8;
1025 #else
1026 v.red.offset = 10;
1027 v.green.offset = 5;
1028 v.blue.offset = 0;
1029 #endif
1030 v.red.length = 5;
1031 v.green.length = 5;
1032 v.blue.length = 5;
1033 break;
1034 #endif
1035
1036 #ifdef FBCON_HAS_CFB32
1037 case 17 ... 32:
1038 v.bits_per_pixel = 32;
1039 dsp->dispsw = &fbcon_cfb32;
1040 dsp->dispsw_data = rivainfo->con_cmap.cfb32;
1041 nom = 4;
1042 den = 1;
1043 dsp->line_length = v.xres_virtual * 4;
1044 dsp->visual = FB_VISUAL_DIRECTCOLOR;
1045 #ifdef CONFIG_PREP
1046 v.red.offset = 8;
1047 v.green.offset = 16;
1048 v.blue.offset = 24;
1049 #else
1050 v.red.offset = 16;
1051 v.green.offset = 8;
1052 v.blue.offset = 0;
1053 #endif
1054 v.red.length = 8;
1055 v.green.length = 8;
1056 v.blue.length = 8;
1057 break;
1058 #endif
1059
1060 default:
1061 printk (KERN_ERR PFX "mode %dx%dx%d rejected...color depth not supported.\n",
1062 var->xres, var->yres, var->bits_per_pixel);
1063 DPRINTK ("EXIT, returning -EINVAL\n");
1064 return -EINVAL;
1065 }
1066
1067 if (v.xres * nom / den * v.yres > rivainfo->ram_amount) {
1068 printk (KERN_ERR PFX "mode %dx%dx%d rejected...resolution too high to fit into video memory!\n",
1069 var->xres, var->yres, var->bits_per_pixel);
1070 DPRINTK ("EXIT - EINVAL error\n");
1071 return -EINVAL;
1072 }
1073
1074 /* use highest possible virtual resolution */
1075 if (v.xres_virtual == -1 &&
1076 v.yres_virtual == -1) {
1077 printk (KERN_WARNING PFX "using maximum available virtual resolution\n");
1078 for (i = 0; modes[i].xres != -1; i++) {
1079 if (modes[i].xres * nom / den * modes[i].yres < rivainfo->ram_amount / 2)
1080 break;
1081 }
1082 if (modes[i].xres == -1) {
1083 printk (KERN_ERR PFX "could not find a virtual resolution that fits into video memory!!\n");
1084 DPRINTK ("EXIT - EINVAL error\n");
1085 return -EINVAL;
1086 }
1087 v.xres_virtual = modes[i].xres;
1088 v.yres_virtual = modes[i].yres;
1089
1090 printk (KERN_INFO PFX "virtual resolution set to maximum of %dx%d\n",
1091 v.xres_virtual, v.yres_virtual);
1092 } else if (v.xres_virtual == -1) {
1093 /* FIXME: maximize X virtual resolution only */
1094 } else if (v.yres_virtual == -1) {
1095 /* FIXME: maximize Y virtual resolution only */
1096 }
1097
1098 if (v.xoffset < 0)
1099 v.xoffset = 0;
1100 if (v.yoffset < 0)
1101 v.yoffset = 0;
1102
1103 /* truncate xoffset and yoffset to maximum if too high */
1104 if (v.xoffset > v.xres_virtual - v.xres)
1105 v.xoffset = v.xres_virtual - v.xres - 1;
1106
1107 if (v.yoffset > v.yres_virtual - v.yres)
1108 v.yoffset = v.yres_virtual - v.yres - 1;
1109
1110 v.red.msb_right =
1111 v.green.msb_right =
1112 v.blue.msb_right =
1113 v.transp.offset =
1114 v.transp.length =
1115 v.transp.msb_right = 0;
1116
1117 switch (v.activate & FB_ACTIVATE_MASK) {
1118 case FB_ACTIVATE_TEST:
1119 DPRINTK ("EXIT - FB_ACTIVATE_TEST\n");
1120 return 0;
1121 case FB_ACTIVATE_NXTOPEN: /* ?? */
1122 case FB_ACTIVATE_NOW:
1123 break; /* continue */
1124 default:
1125 DPRINTK ("EXIT - unknown activation type\n");
1126 return -EINVAL; /* unknown */
1127 }
1128
1129 dsp->type = FB_TYPE_PACKED_PIXELS;
1130
1131 #warning FIXME: verify that the above code sets dsp->* fields correctly
1132
1133 memcpy (&dsp->var, &v, sizeof (v));
1134
1135 riva_load_video_mode (rivainfo, &v);
1136
1137 if (chgvar && info && info->changevar)
1138 info->changevar (con);
1139
1140 DPRINTK ("EXIT, returning 0\n");
1141 return 0;
1142 }
1143
1144
1145
1146 /**
1147 * rivafb_get_cmap
1148 * @cmap:
1149 * @kspc:
1150 * @con:
1151 * @info:
1152 *
1153 * DESCRIPTION:
1154 *
1155 * NOTES:
1156 * Copied from matroxfb::matroxfb_get_cmap()
1157 */
1158
1159 int rivafb_get_cmap (struct fb_cmap *cmap, int kspc, int con,
1160 struct fb_info *info)
1161 {
1162 struct rivafb_info *rivainfo = (struct rivafb_info *) info;
1163 struct display *dsp;
1164
1165 DPRINTK ("ENTER\n");
1166
1167 assert (rivainfo != NULL);
1168 assert (cmap != NULL);
1169
1170 dsp = (con < 0) ? rivainfo->info.disp : &fb_display[con];
1171
1172 if (con == rivainfo->currcon) { /* current console? */
1173 int rc = fb_get_cmap (cmap, kspc, riva_getcolreg, info);
1174 DPRINTK ("EXIT - returning %d\n", rc);
1175 return rc;
1176 } else if (dsp->cmap.len) /* non default colormap? */
1177 fb_copy_cmap (&dsp->cmap, cmap, kspc ? 0 : 2);
1178 else
1179 fb_copy_cmap (fb_default_cmap (riva_get_cmap_len (&dsp->var)),
1180 cmap, kspc ? 0 : 2);
1181
1182 DPRINTK ("EXIT, returning 0\n");
1183
1184 return 0;
1185 }
1186
1187
1188 /**
1189 * rivafb_set_cmap
1190 * @cmap:
1191 * @kspc:
1192 * @con:
1193 * @info:
1194 *
1195 * DESCRIPTION:
1196 *
1197 * NOTES:
1198 * Copied from matroxfb::matroxfb_set_cmap()
1199 */
1200
1201 int rivafb_set_cmap (struct fb_cmap *cmap, int kspc, int con,
1202 struct fb_info *info)
1203 {
1204 struct rivafb_info *rivainfo = (struct rivafb_info *) info;
1205 struct display *dsp;
1206 unsigned int cmap_len;
1207
1208 DPRINTK ("ENTER\n");
1209
1210 assert (rivainfo != NULL);
1211 assert (cmap != NULL);
1212
1213 dsp = (con < 0) ? rivainfo->info.disp : &fb_display[con];
1214
1215 cmap_len = riva_get_cmap_len (&dsp->var);
1216 if (dsp->cmap.len != cmap_len) {
1217 int err = fb_alloc_cmap (&dsp->cmap, cmap_len, 0);
1218 if (err) {
1219 DPRINTK ("EXIT - returning %d\n", err);
1220 return err;
1221 }
1222 }
1223 if (con == rivainfo->currcon) { /* current console? */
1224 int rc = fb_set_cmap (cmap, kspc, riva_setcolreg, info);
1225 DPRINTK ("EXIT - returning %d\n", rc);
1226 return rc;
1227 } else
1228 fb_copy_cmap (cmap, &dsp->cmap, kspc ? 0 : 1);
1229
1230 DPRINTK ("EXIT, returning 0\n");
1231
1232 return 0;
1233 }
1234
1235
1236
1237 /**
1238 * rivafb_pan_display
1239 * @var: standard kernel fb changeable data
1240 * @par: riva-specific hardware info about current video mode
1241 * @info: pointer to rivafb_info object containing info for current riva board
1242 *
1243 * DESCRIPTION:
1244 * Pan (or wrap, depending on the `vmode' field) the display using the
1245 * `xoffset' and `yoffset' fields of the `var' structure.
1246 * If the values don't fit, return -EINVAL.
1247 *
1248 * This call looks only at xoffset, yoffset and the FB_VMODE_YWRAP flag
1249 */
1250
1251 int rivafb_pan_display (struct fb_var_screeninfo *var, int con,
1252 struct fb_info *info)
1253 {
1254 unsigned int base;
1255 struct display *dsp;
1256 struct rivafb_info *rivainfo = (struct rivafb_info *) info;
1257
1258 DPRINTK ("ENTER\n");
1259
1260 assert (rivainfo != NULL);
1261
1262 if (var->xoffset > (var->xres_virtual - var->xres))
1263 return -EINVAL;
1264 if (var->yoffset > (var->yres_virtual - var->yres))
1265 return -EINVAL;
1266
1267 dsp = (con < 0) ? rivainfo->info.disp : &fb_display[con];
1268
1269 if (var->vmode & FB_VMODE_YWRAP) {
1270 if (var->yoffset < 0 || var->yoffset >= dsp->var.yres_virtual || var->xoffset)
1271 return -EINVAL;
1272 } else {
1273 if (var->xoffset+dsp->var.xres > dsp->var.xres_virtual ||
1274 var->yoffset+dsp->var.yres > dsp->var.yres_virtual)
1275 return -EINVAL;
1276 }
1277
1278 base = var->yoffset * dsp->line_length + var->xoffset;
1279
1280 if (con == rivainfo->currcon) {
1281 /* FIXME: do the dirty deed */
1282 }
1283
1284 dsp->var.xoffset = var->xoffset;
1285 dsp->var.yoffset = var->yoffset;
1286
1287 if (var->vmode & FB_VMODE_YWRAP)
1288 dsp->var.vmode |= FB_VMODE_YWRAP;
1289 else
1290 dsp->var.vmode &= ~FB_VMODE_YWRAP;
1291
1292 DPRINTK ("EXIT, returning 0\n");
1293
1294 return 0;
1295 }
1296
1297
1298
1299 /**
1300 * rivafb_ioctl
1301 * @inode:
1302 * @file:
1303 * @cmd:
1304 * @arg:
1305 * @con:
1306 * @info:
1307 *
1308 * DESCRIPTION:
1309 */
1310
1311 int rivafb_ioctl (struct inode *inode, struct file *file, unsigned int cmd,
1312 unsigned long arg, int con, struct fb_info *info)
1313 {
1314 struct rivafb_info *rivainfo = (struct rivafb_info *) info;
1315
1316 DPRINTK ("ENTER\n");
1317
1318 assert (rivainfo != NULL);
1319
1320 /* no rivafb-specific ioctls */
1321
1322 DPRINTK ("EXIT, returning -EINVAL\n");
1323
1324 return -EINVAL;
1325 }
1326
1327
1328
1329
1330 /**
1331 * rivafb_switch
1332 * @con:
1333 * @info:
1334 *
1335 * DESCRIPTION:
1336 */
1337
1338 int rivafb_switch(int con, struct fb_info *info)
1339 {
1340 struct rivafb_info *rivainfo = (struct rivafb_info *) info;
1341 struct fb_cmap* cmap;
1342 struct display *dsp;
1343
1344 DPRINTK("ENTER\n");
1345
1346 assert (rivainfo != NULL);
1347
1348 dsp = (con < 0) ? rivainfo->info.disp : &fb_display[con];
1349
1350 if (rivainfo->currcon >= 0) {
1351 /* Do we have to save the colormap? */
1352 cmap = &(rivainfo->currcon_display->cmap);
1353 DPRINTK("switch1: con = %d, cmap.len = %d\n", rivainfo->currcon, cmap->len);
1354
1355 if (cmap->len) {
1356 DPRINTK("switch1a: %p %p %p %p\n", cmap->red, cmap->green, cmap->blue, cmap->transp);
1357 fb_get_cmap(cmap, 1, riva_getcolreg, info);
1358 #ifdef DEBUG
1359 if (cmap->red) {
1360 DPRINTK("switch1r: %X\n", cmap->red[0]);
1361 }
1362 #endif
1363 }
1364 }
1365 rivainfo->currcon = con;
1366 rivainfo->currcon_display = dsp;
1367 dsp->var.activate = FB_ACTIVATE_NOW;
1368
1369 #ifdef riva_DEBUG
1370 cmap = &dsp->cmap;
1371 DPRINTK("switch2: con = %d, cmap.len = %d\n", con, cmap->len);
1372 DPRINTK("switch2a: %p %p %p %p\n", cmap->red, cmap->green, cmap->blue, cmap->transp);
1373 if (dsp->cmap.red) {
1374 DPRINTK("switch2r: %X\n", cmap->red[0]);
1375 }
1376 #endif
1377
1378 rivafb_set_var(&dsp->var, con, info);
1379
1380 #ifdef riva_DEBUG
1381 DPRINTK("switch3: con = %d, cmap.len = %d\n", con, cmap->len);
1382 DPRINTK("switch3a: %p %p %p %p\n", cmap->red, cmap->green, cmap->blue, cmap->transp);
1383 if (dsp->cmap.red) {
1384 DPRINTK("switch3r: %X\n", cmap->red[0]);
1385 }
1386 #endif
1387
1388 DPRINTK("EXIT, returning 0\n");
1389
1390 return 0;
1391 }
1392
1393
1394
1395 void rivafb_blank (int blank, struct fb_info *info)
1396 {
1397 unsigned char tmp;
1398 struct rivafb_info *rivainfo = (struct rivafb_info *) info;
1399
1400 DPRINTK ("ENTER\n");
1401
1402 assert (rivainfo != NULL);
1403
1404 tmp = vga_io_rseq (VGA_SEQ_CLOCK_MODE) & ~VGA_SR01_SCREEN_OFF;
1405
1406 if (blank)
1407 tmp |= VGA_SR01_SCREEN_OFF;
1408
1409 vga_io_wseq (VGA_SEQ_CLOCK_MODE, tmp);
1410
1411 DPRINTK("EXIT\n");
1412 }
1413
1414
1415 /* -------------------------------------------------------------------------
1416 *
1417 * internal fb_ops helper functions
1418 *
1419 * -------------------------------------------------------------------------
1420 */
1421
1422
1423 /**
1424 * riva_get_cmap_len
1425 * @var:
1426 *
1427 * DESCRIPTION:
1428 */
1429
1430 static int riva_get_cmap_len(const struct fb_var_screeninfo *var)
1431 {
1432 int rc = 16; /* reasonable default */
1433
1434 assert (var != NULL);
1435
1436 switch (var->bits_per_pixel) {
1437 #ifdef FBCON_HAS_CFB4
1438 case 4:
1439 rc = 16; /* pseudocolor... 16 entries HW palette */
1440 break;
1441 #endif
1442 #ifdef FBCON_HAS_CFB8
1443 case 8:
1444 rc = 256; /* pseudocolor... 256 entries HW palette */
1445 break;
1446 #endif
1447 #ifdef FBCON_HAS_CFB16
1448 case 16:
1449 rc = 16; /* directcolor... 16 entries SW palette */
1450 break; /* Mystique: truecolor, 16 entries SW palette, HW palette hardwired into 1:1 mapping */
1451 #endif
1452 #ifdef FBCON_HAS_CFB32
1453 case 32:
1454 rc = 16; /* directcolor... 16 entries SW palette */
1455 break; /* Mystique: truecolor, 16 entries SW palette, HW palette hardwired into 1:1 mapping */
1456 #endif
1457 default:
1458 assert (0);
1459 /* should not occur */
1460 break;
1461 }
1462
1463 return rc;
1464 }
1465
1466
1467 /**
1468 * riva_getcolreg
1469 * @regno:
1470 * @red:
1471 * @green:
1472 * @blue:
1473 * @transp:
1474 * @info: pointer to rivafb_info object containing info for current riva board
1475 *
1476 * DESCRIPTION:
1477 * Read a single color register and split it into colors/transparent.
1478 * The return values must have a 16 bit magnitude.
1479 * Return != 0 for invalid regno.
1480 *
1481 * CALLED FROM:
1482 * fbcmap.c:fb_get_cmap()
1483 * fbgen.c:fbgen_get_cmap()
1484 * fbgen.c:fbgen_switch()
1485 */
1486
1487 static int riva_getcolreg (unsigned regno, unsigned *red, unsigned *green,
1488 unsigned *blue, unsigned *transp,
1489 struct fb_info *info)
1490 {
1491 struct rivafb_info *rivainfo = (struct rivafb_info *) info;
1492
1493 if (regno > 255)
1494 return 1;
1495 *red = rivainfo->palette[regno].red;
1496 *green = rivainfo->palette[regno].green;
1497 *blue = rivainfo->palette[regno].blue;
1498 *transp = 0;
1499 return 0;
1500 }
1501
1502
1503 /**
1504 * riva_setcolreg
1505 * @regno:
1506 * @red:
1507 * @green:
1508 * @blue:
1509 * @transp:
1510 * @info: pointer to rivafb_info object containing info for current riva board
1511 *
1512 * DESCRIPTION:
1513 * Set a single color register. The values supplied have a 16 bit
1514 * magnitude.
1515 * Return != 0 for invalid regno.
1516 *
1517 * CALLED FROM:
1518 * fbcmap.c:fb_set_cmap()
1519 * fbgen.c:fbgen_get_cmap()
1520 * fbgen.c:fbgen_install_cmap()
1521 * fbgen.c:fbgen_set_var()
1522 * fbgen.c:fbgen_switch()
1523 * fbgen.c:fbgen_blank()
1524 * fbgen.c:fbgen_blank()
1525 */
1526
1527 static int riva_setcolreg (unsigned regno, unsigned red, unsigned green,
1528 unsigned blue, unsigned transp,
1529 struct fb_info *info)
1530 {
1531 struct rivafb_info *rivainfo = (struct rivafb_info *) info;
1532 struct display *p;
1533
1534 DPRINTK("ENTER\n");
1535
1536 assert (rivainfo != NULL);
1537 assert (rivainfo->currcon_display != NULL);
1538
1539 if (regno > 255)
1540 return -EINVAL;
1541
1542 p = rivainfo->currcon_display;
1543 if (p->var.grayscale) {
1544 /* gray = 0.30*R + 0.59*G + 0.11*B */
1545 red = green = blue = (red * 77 + green * 151 + blue * 28) >> 8;
1546 }
1547
1548 #ifdef FBCON_HAS_CFB8
1549 switch (p->var.bits_per_pixel) {
1550 case 8:
1551 /* "transparent" stuff is completely ignored. */
1552 riva_wclut (regno, red >> 10, green >> 10, blue >> 10);
1553 break;
1554 default:
1555 /* do nothing */
1556 break;
1557 }
1558 #endif /* FBCON_HAS_CFB8 */
1559
1560 rivainfo->palette[regno].red = red;
1561 rivainfo->palette[regno].green = green;
1562 rivainfo->palette[regno].blue = blue;
1563
1564 if (regno >= 16)
1565 return 0;
1566
1567 switch (p->var.bits_per_pixel) {
1568
1569 #ifdef FBCON_HAS_CFB16
1570 case 16:
1571 assert (regno < 16);
1572 #ifdef CONFIG_PREP
1573 rivainfo->con_cmap.cfb16[regno] =
1574 ((red & 0xf800) >> 9) |
1575 ((green & 0xf800) >> 14) |
1576 ((green & 0xf800) << 2) |
1577 ((blue & 0xf800) >> 3);
1578 #else
1579 rivainfo->con_cmap.cfb16[regno] =
1580 ((red & 0xf800) >> 1) |
1581 ((green & 0xf800) >> 6) |
1582 ((blue & 0xf800) >> 11);
1583 #endif
1584 break;
1585 #endif /* FBCON_HAS_CFB16 */
1586
1587 #ifdef FBCON_HAS_CFB32
1588 case 32:
1589 assert (regno < 16);
1590 #ifdef CONFIG_PREP
1591 rivainfo->con_cmap.cfb32[regno] =
1592 ((red & 0xff00)) |
1593 ((green & 0xff00) << 8) |
1594 ((blue & 0xff00) << 16);
1595 #else
1596 rivainfo->con_cmap.cfb32[regno] =
1597 ((red & 0xff00) << 8) |
1598 ((green & 0xff00)) |
1599 ((blue & 0xff00) >> 8);
1600 #endif
1601 break;
1602 #endif /* FBCON_HAS_CFB32 */
1603
1604 default:
1605 /* do nothing */
1606 break;
1607 }
1608
1609 return 0;
1610 }
1611
1612
1613
1614 /*
1615 * riva_load_video_mode()
1616 *
1617 * calculate some timings and then send em off to riva_load_state()
1618 */
1619
1620 static void riva_load_video_mode (struct rivafb_info *rinfo,
1621 struct fb_var_screeninfo *video_mode)
1622 {
1623 struct riva_regs newmode;
1624 int bpp, width, hDisplaySize, hDisplay, hStart,
1625 hEnd, hTotal, height, vDisplay, vStart,
1626 vEnd, vTotal, dotClock;
1627
1628 /* time to calculate */
1629
1630 bpp = video_mode->bits_per_pixel;
1631 width = hDisplaySize = video_mode->xres;
1632 hDisplay = (hDisplaySize/8) - 1;
1633 hStart = (hDisplaySize + video_mode->right_margin)/8 + 2;
1634 hEnd = (hDisplaySize + video_mode->right_margin +
1635 video_mode->hsync_len)/8 - 1;
1636 hTotal = (hDisplaySize + video_mode->right_margin +
1637 video_mode->hsync_len + video_mode->left_margin)/8 - 1;
1638 height = video_mode->yres;
1639 vDisplay = video_mode->yres - 1;
1640 vStart = video_mode->yres + video_mode->lower_margin - 1;
1641 vEnd = video_mode->yres + video_mode->lower_margin +
1642 video_mode->vsync_len - 1;
1643 vTotal = video_mode->yres + video_mode->lower_margin +
1644 video_mode->vsync_len + video_mode->upper_margin + 2;
1645 dotClock = 1000000000 / video_mode->pixclock;
1646
1647 memcpy(&newmode, &reg_template, sizeof(struct riva_regs));
1648
1649 newmode.crtc[0x0] = Set8Bits(hTotal - 4);
1650 newmode.crtc[0x1] = Set8Bits(hDisplay);
1651 newmode.crtc[0x2] = Set8Bits(hDisplay);
1652 newmode.crtc[0x3] = SetBitField(hTotal,4:0,4:0) | SetBit(7);
1653 newmode.crtc[0x4] = Set8Bits(hStart);
1654 newmode.crtc[0x5] = SetBitField(hTotal,5:5,7:7)
1655 | SetBitField(hEnd,4:0,4:0);
1656 newmode.crtc[0x6] = SetBitField(vTotal,7:0,7:0);
1657 newmode.crtc[0x7] = SetBitField(vTotal,8:8,0:0)
1658 | SetBitField(vDisplay,8:8,1:1)
1659 | SetBitField(vStart,8:8,2:2)
1660 | SetBitField(vDisplay,8:8,3:3)
1661 | SetBit(4)
1662 | SetBitField(vTotal,9:9,5:5)
1663 | SetBitField(vDisplay,9:9,6:6)
1664 | SetBitField(vStart,9:9,7:7);
1665 newmode.crtc[0x9] = SetBitField(vDisplay,9:9,5:5)
1666 | SetBit(6);
1667 newmode.crtc[0x10] = Set8Bits(vStart);
1668 newmode.crtc[0x11] = SetBitField(vEnd,3:0,3:0)
1669 | SetBit(5);
1670 newmode.crtc[0x12] = Set8Bits(vDisplay);
1671 newmode.crtc[0x13] = ((width/8)*(bpp/8)) & 0xFF;
1672 newmode.crtc[0x15] = Set8Bits(vDisplay);
1673 newmode.crtc[0x16] = Set8Bits(vTotal + 1);
1674
1675 newmode.ext.bpp = bpp;
1676 newmode.ext.width = width;
1677 newmode.ext.height = height;
1678
1679 rinfo->riva.CalcStateExt(&rinfo->riva,&newmode.ext,bpp,width,
1680 hDisplaySize,hDisplay,hStart,hEnd,hTotal,
1681 height,vDisplay,vStart,vEnd,vTotal,dotClock);
1682
1683 rinfo->initial_state = newmode;
1684 riva_load_state(rinfo,&newmode);
1685 }
1686
1687
1688
1689
1690
1691 /* ------------------------------------------------------------------------- */
1692
1693
1694 /*
1695 * Modularization
1696 */
1697
1698 #ifdef MODULE
1699 int __init init_module(void)
1700 {
1701 return rivafb_init();
1702 }
1703
1704 void __exit cleanup_module(void)
1705 {
1706 struct rivafb_info *tmp, *board = riva_boards;
1707
1708 while (board != NULL) {
1709 riva_load_state (board, &board->initial_state);
1710
1711 unregister_framebuffer ((struct fb_info *) board);
1712
1713 tmp = board;
1714 iounmap (tmp->ctrl_base);
1715 iounmap (tmp->fb_base);
1716 board = board->next;
1717
1718 kfree (tmp);
1719 }
1720 }
1721 #endif /* MODULE */
1722
1723
1724
1725
1726
1727 /* from GGI */
1728 static
1729 void riva_save_state(struct rivafb_info *rinfo, struct riva_regs *regs)
1730 {
1731 int i;
1732
1733 io_out8(NV_CIO_SR_LOCK_INDEX, 0x3D4);
1734 io_out8(NV_CIO_SR_UNLOCK_RW_VALUE, 0x3D5);
1735
1736 rinfo->riva.UnloadStateExt(&rinfo->riva, &regs->ext);
1737
1738 regs->misc_output = io_in8(0x3CC);
1739
1740 for (i = 0; i < NUM_CRT_REGS; i++)
1741 {
1742 io_out8(i, 0x3D4);
1743 regs->crtc[i] = io_in8(0x3D5);
1744 }
1745
1746 for (i = 0; i < NUM_ATC_REGS; i++)
1747 {
1748 io_out8(i, 0x3C0);
1749 regs->attr[i] = io_in8(0x3C1);
1750 }
1751
1752 for (i = 0; i < NUM_GRC_REGS; i++)
1753 {
1754 io_out8(i, 0x3CE);
1755 regs->gra[i] = io_in8(0x3CF);
1756 }
1757
1758
1759 for (i = 0; i < NUM_SEQ_REGS; i++)
1760 {
1761 io_out8(i, 0x3C4);
1762 regs->seq[i] = io_in8(0x3C5);
1763 }
1764 }
1765
1766
1767 /* from GGI */
1768 static
1769 void riva_load_state(struct rivafb_info *rinfo, struct riva_regs *regs)
1770 {
1771 int i;
1772 RIVA_HW_STATE *state = &regs->ext;
1773
1774 io_out8(0x11, 0x3D4);
1775 io_out8(0x00, 0x3D5);
1776
1777 io_out8(NV_CIO_SR_LOCK_INDEX, 0x3D4);
1778 io_out8(NV_CIO_SR_UNLOCK_RW_VALUE, 0x3D5);
1779
1780 rinfo->riva.LoadStateExt(&rinfo->riva,state);
1781
1782 io_out8(regs->misc_output, 0x3C2);
1783
1784 for (i = 0; i < NUM_CRT_REGS; i++)
1785 {
1786 if (i < 0x19)
1787 {
1788 io_out8(i, 0x3D4);
1789 io_out8(regs->crtc[i], 0x3D5);
1790 }
1791 else
1792 {
1793 switch (i)
1794 {
1795 case 0x19:
1796 case 0x20:
1797 case 0x21:
1798 case 0x22:
1799 case 0x23:
1800 case 0x24:
1801 case 0x25:
1802 case 0x26:
1803 case 0x27:
1804 #if 0
1805 case 0x28:
1806 #endif
1807 case 0x29:
1808 case 0x2a:
1809 case 0x2b:
1810 case 0x2c:
1811 case 0x2d:
1812 case 0x2e:
1813 case 0x2f:
1814 case 0x30:
1815 case 0x31:
1816 case 0x32:
1817 case 0x33:
1818 case 0x34:
1819 case 0x35:
1820 case 0x36:
1821 case 0x37:
1822 case 0x38:
1823 case 0x39:
1824 case 0x3a:
1825 case 0x3b:
1826 case 0x3c:
1827 case 0x3d:
1828 case 0x3e:
1829 case 0x3f:
1830 #if 0
1831 case 0x40:
1832 #endif
1833 break;
1834 default:
1835 io_out8(i, 0x3D4);
1836 io_out8(regs->crtc[i], 0x3D5);
1837 }
1838 }
1839 }
1840
1841 for (i = 0; i < NUM_ATC_REGS; i++)
1842 {
1843 io_out8(i, 0x3C0);
1844 io_out8(regs->attr[i], 0x3C1);
1845 }
1846
1847 for (i = 0; i < NUM_GRC_REGS; i++)
1848 {
1849 io_out8(i, 0x3CE);
1850 io_out8(regs->gra[i], 0x3CF);
1851 }
1852
1853 for (i = 0; i < NUM_SEQ_REGS; i++)
1854 {
1855 io_out8(i, 0x3C4);
1856 io_out8(regs->seq[i], 0x3C5);
1857 }
1858 }
1859
1860
1861
1862
1863 /**
1864 * riva_board_list_add
1865 * @board_list: Root node of list of boards
1866 * @new_node: New node to be added
1867 *
1868 * DESCRIPTION:
1869 * Adds @new_node to the list referenced by @board_list
1870 *
1871 * RETURNS:
1872 * New root node
1873 */
1874 static
1875 struct rivafb_info *riva_board_list_add(struct rivafb_info *board_list,
1876 struct rivafb_info *new_node)
1877 {
1878 struct rivafb_info *i_p = board_list;
1879
1880 new_node->next = NULL;
1881
1882 if (board_list == NULL)
1883 return new_node;
1884
1885 while (i_p->next != NULL)
1886 i_p = i_p->next;
1887 i_p->next = new_node;
1888
1889 return board_list;
1890 }
1891
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