include/asm-mips/sgihpc.h

   1 /* $Id: sgihpc.h,v 1.4 1998/09/16 22:52:42 ralf Exp $
   2  *
   3  * sgihpc.h: Various HPC I/O controller defines.  The HPC is basically
   4  *           the approximate functional equivalent of the Sun SYSIO
   5  *           on SGI INDY machines.
   6  *
   7  * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
   8  * Copyright (C) 1998 Ralf Baechle (ralf@gnu.org)
   9  */
  10 #ifndef _MIPS_SGIHPC_H
  11 #define _MIPS_SGIHPC_H
  12
  13 #include <asm/page.h>
  14
  15 extern int sgi_has_ioc2; /* to know if we have older ioc1 or ioc2. */
  16 extern int sgi_guiness;  /* GUINESS or FULLHOUSE machine. */
  17 extern int sgi_boardid;  /* Board revision. */
  18
  19 /* An HPC dma descriptor. */
  20 struct hpc_dma_desc {
  21         unsigned long pbuf;      /* physical address of data buffer */
  22         unsigned long cntinfo;   /* counter and info bits */
  23 #define HPCDMA_EOX    0x80000000 /* last desc in chain for tx */
  24 #define HPCDMA_EOR    0x80000000 /* last desc in chain for rx */
  25 #define HPCDMA_EOXP   0x40000000 /* end of packet for tx */
  26 #define HPCDMA_EORP   0x40000000 /* end of packet for rx */
  27 #define HPCDMA_XIE    0x20000000 /* irq generated when at end of this desc */
  28 #define HPCDMA_XIU    0x01000000 /* Tx buffer in use by CPU. */
  29 #define HPCDMA_EIPC   0x00ff0000 /* SEEQ ethernet special xternal bytecount */
  30 #define HPCDMA_ETXD   0x00008000 /* set to one by HPC when packet tx'd */
  31 #define HPCDMA_OWN    0x00004000 /* Denotes ring buffer ownership on rx */
  32 #define HPCDMA_BCNT   0x00003fff /* size in bytes of this dma buffer */
  33
  34         unsigned long pnext;     /* paddr of next hpc_dma_desc if any */
  35 };
  36
  37 typedef volatile unsigned long hpcreg;
  38
  39 /* HPC1 stuff. */
  40
  41 /* HPC3 stuff. */
  42
  43 /* The set of regs for each HPC3 pbus dma channel. */
  44 struct hpc3_pbus_dmacregs {
  45         hpcreg pbdma_bptr; /* pbus dma channel buffer ptr */
  46         hpcreg pbdma_dptr; /* pbus dma channel desc ptr */
  47         char _unused1[PAGE_SIZE - (2 * sizeof(hpcreg))]; /* padding */
  48         hpcreg pbdma_ctrl; /* pbus dma channel control reg */
  49 #define HPC3_PDMACTRL_SEL  0x00000002 /* little endian transfer */
  50 #define HPC3_PDMACTRL_RCV  0x00000004 /* direction is receive */
  51 #define HPC3_PDMACTRL_FLSH 0x00000008 /* enable flush for receive DMA */
  52 #define HPC3_PDMACTRL_ACT  0x00000010 /* start dma transfer */
  53 #define HPC3_PDMACTRL_LD   0x00000020 /* load enable for ACT */
  54 #define HPC3_PDMACTRL_RT   0x00000040 /* Use realtime GIO bus servicing */
  55 #define HPC3_PDMACTRL_HW   0x0000ff00 /* DMA High-water mark */
  56 #define HPC3_PDMACTRL_FB   0x003f0000 /* Ptr to beginning of fifo */
  57 #define HPC3_PDMACTRL_FE   0x3f000000 /* Ptr to end of fifo */
  58
  59         char _unused2[PAGE_SIZE - (sizeof(hpcreg))]; /* padding */
  60 };
  61
  62 /* The HPC3 scsi registers, this does not include external ones. */
  63 struct hpc3_scsiregs {
  64         hpcreg cbptr;   /* current dma buffer ptr, diagnostic use only */
  65         hpcreg ndptr;   /* next dma descriptor ptr */
  66         char _unused1[PAGE_SIZE - (2 * sizeof(hpcreg))]; /* padding */
  67         hpcreg bcd;     /* byte count info */
  68 #define HPC3_SBCD_BCNTMSK 0x00003fff /* bytes to transfer from/to memory */
  69 #define HPC3_SBCD_XIE     0x00004000 /* Send IRQ when done with cur buf */
  70 #define HPC3_SBCD_EOX     0x00008000 /* Indicates this is last buf in chain */
  71
  72         hpcreg ctrl;    /* control register */
  73 #define HPC3_SCTRL_IRQ    0x01 /* IRQ asserted, either dma done or parity */
  74 #define HPC3_SCTRL_ENDIAN 0x02 /* DMA endian mode, 0=big 1=little */
  75 #define HPC3_SCTRL_DIR    0x04 /* DMA direction, 1=dev2mem 0=mem2dev */
  76 #define HPC3_SCTRL_FLUSH  0x08 /* Tells HPC3 to flush scsi fifos */
  77 #define HPC3_SCTRL_ACTIVE 0x10 /* SCSI DMA channel is active */
  78 #define HPC3_SCTRL_AMASK  0x20 /* DMA active inhibits PIO */
  79 #define HPC3_SCTRL_CRESET 0x40 /* Resets dma channel and external controller */
  80 #define HPC3_SCTRL_PERR   0x80 /* Bad parity on HPC3 iface to scsi controller */
  81
  82         hpcreg gfptr;   /* current GIO fifo ptr */
  83         hpcreg dfptr;   /* current device fifo ptr */
  84         hpcreg dconfig; /* DMA configuration register */
  85 #define HPC3_SDCFG_HCLK 0x00001 /* Enable DMA half clock mode */
  86 #define HPC3_SDCFG_D1   0x00006 /* Cycles to spend in D1 state */
  87 #define HPC3_SDCFG_D2   0x00038 /* Cycles to spend in D2 state */
  88 #define HPC3_SDCFG_D3   0x001c0 /* Cycles to spend in D3 state */
  89 #define HPC3_SDCFG_HWAT 0x00e00 /* DMA high water mark */
  90 #define HPC3_SDCFG_HW   0x01000 /* Enable 16-bit halfword DMA accesses to scsi */
  91 #define HPC3_SDCFG_SWAP 0x02000 /* Byte swap all DMA accesses */
  92 #define HPC3_SDCFG_EPAR 0x04000 /* Enable parity checking for DMA */
  93 #define HPC3_SDCFG_POLL 0x08000 /* hd_dreq polarity control */
  94 #define HPC3_SDCFG_ERLY 0x30000 /* hd_dreq behavior control bits */
  95
  96         hpcreg pconfig; /* PIO configuration register */
  97 #define HPC3_SPCFG_P3   0x0003 /* Cycles to spend in P3 state */
  98 #define HPC3_SPCFG_P2W  0x001c /* Cycles to spend in P2 state for writes */
  99 #define HPC3_SPCFG_P2R  0x01e0 /* Cycles to spend in P2 state for reads */
 100 #define HPC3_SPCFG_P1   0x0e00 /* Cycles to spend in P1 state */
 101 #define HPC3_SPCFG_HW   0x1000 /* Enable 16-bit halfword PIO accesses to scsi */
 102 #define HPC3_SPCFG_SWAP 0x2000 /* Byte swap all PIO accesses */
 103 #define HPC3_SPCFG_EPAR 0x4000 /* Enable parity checking for PIO */
 104 #define HPC3_SPCFG_FUJI 0x8000 /* Fujitsu scsi controller mode for faster dma/pio */
 105
 106         char _unused2[PAGE_SIZE - (6 * sizeof(hpcreg))]; /* padding */
 107 };
 108
 109 /* SEEQ ethernet HPC3 registers, only one seeq per HPC3. */
 110 struct hpc3_ethregs {
 111         /* Receiver registers. */
 112         hpcreg rx_cbptr;   /* current dma buffer ptr, diagnostic use only */
 113         hpcreg rx_ndptr;   /* next dma descriptor ptr */
 114         char _unused1[PAGE_SIZE - (2 * sizeof(hpcreg))]; /* padding */
 115         hpcreg rx_bcd;     /* byte count info */
 116 #define HPC3_ERXBCD_BCNTMSK 0x00003fff /* bytes to be sent to memory */
 117 #define HPC3_ERXBCD_XIE     0x20000000 /* HPC3 interrupts cpu at end of this buf */
 118 #define HPC3_ERXBCD_EOX     0x80000000 /* flags this as end of descriptor chain */
 119
 120         hpcreg rx_ctrl;    /* control register */
 121 #define HPC3_ERXCTRL_STAT50 0x0000003f /* Receive status reg bits of Seeq8003 */
 122 #define HPC3_ERXCTRL_STAT6  0x00000040 /* Rdonly irq status */
 123 #define HPC3_ERXCTRL_STAT7  0x00000080 /* Rdonlt old/new status bit from Seeq */
 124 #define HPC3_ERXCTRL_ENDIAN 0x00000100 /* Endian for dma channel, little=1 big=0 */
 125 #define HPC3_ERXCTRL_ACTIVE 0x00000200 /* Tells if DMA transfer is in progress */
 126 #define HPC3_ERXCTRL_AMASK  0x00000400 /* Tells if ACTIVE inhibits PIO's to hpc3 */
 127 #define HPC3_ERXCTRL_RBO    0x00000800 /* Receive buffer overflow if set to 1 */
 128
 129         hpcreg rx_gfptr;   /* current GIO fifo ptr */
 130         hpcreg rx_dfptr;   /* current device fifo ptr */
 131         hpcreg _unused2;   /* padding */
 132         hpcreg rx_reset;   /* reset register */
 133 #define HPC3_ERXRST_CRESET 0x1 /* Reset dma channel and external controller */
 134 #define HPC3_ERXRST_CLRIRQ 0x2 /* Clear channel interrupt */
 135 #define HPC3_ERXRST_LBACK  0x4 /* Enable diagnostic loopback mode of Seeq8003 */
 136
 137         hpcreg rx_dconfig; /* DMA configuration register */
 138 #define HPC3_ERXDCFG_D1    0x0000f /* Cycles to spend in D1 state for PIO */
 139 #define HPC3_ERXDCFG_D2    0x000f0 /* Cycles to spend in D2 state for PIO */
 140 #define HPC3_ERXDCFG_D3    0x00f00 /* Cycles to spend in D3 state for PIO */
 141 #define HPC3_ERXDCFG_WCTRL 0x01000 /* Enable writes of desc into ex ctrl port */
 142 #define HPC3_ERXDCFG_FRXDC 0x02000 /* Clear eop stat bits upon rxdc, hw seeq fix */
 143 #define HPC3_ERXDCFG_FEOP  0x04000 /* Bad packet marker timeout enable */
 144 #define HPC3_ERXDCFG_FIRQ  0x08000 /* Another bad packet timeout enable */
 145 #define HPC3_ERXDCFG_PTO   0x30000 /* Programmed timeout value for above two */
 146
 147         hpcreg rx_pconfig; /* PIO configuration register */
 148 #define HPC3_ERXPCFG_P1    0x000f /* Cycles to spend in P1 state for PIO */
 149 #define HPC3_ERXPCFG_P2    0x00f0 /* Cycles to spend in P2 state for PIO */
 150 #define HPC3_ERXPCFG_P3    0x0f00 /* Cycles to spend in P3 state for PIO */
 151 #define HPC3_ERXPCFG_TST   0x1000 /* Diagnistic ram test feature bit */
 152
 153         char _unused3[PAGE_SIZE - (8 * sizeof(hpcreg))]; /* padding */
 154
 155         /* Transmitter registers. */
 156         hpcreg tx_cbptr;   /* current dma buffer ptr, diagnostic use only */
 157         hpcreg tx_ndptr;   /* next dma descriptor ptr */
 158         char _unused4[PAGE_SIZE - (2 * sizeof(hpcreg))]; /* padding */
 159         hpcreg tx_bcd;     /* byte count info */
 160 #define HPC3_ETXBCD_BCNTMSK 0x00003fff /* bytes to be read from memory */
 161 #define HPC3_ETXBCD_ESAMP   0x10000000 /* if set, too late to add descriptor */
 162 #define HPC3_ETXBCD_XIE     0x20000000 /* Interrupt cpu at end of cur desc */
 163 #define HPC3_ETXBCD_EOP     0x40000000 /* Last byte of cur buf is end of packet */
 164 #define HPC3_ETXBCD_EOX     0x80000000 /* This buf is the end of desc chain */
 165
 166         hpcreg tx_ctrl;    /* control register */
 167 #define HPC3_ETXCTRL_STAT30 0x0000000f /* Rdonly copy of seeq tx stat reg */
 168 #define HPC3_ETXCTRL_STAT4  0x00000010 /* Indicate late collision occurred */
 169 #define HPC3_ETXCTRL_STAT75 0x000000e0 /* Rdonly irq status from seeq */
 170 #define HPC3_ETXCTRL_ENDIAN 0x00000100 /* Dma channel endian mode, 1=little 0=big */
 171 #define HPC3_ETXCTRL_ACTIVE 0x00000200 /* DMA tx channel is active */
 172 #define HPC3_ETXCTRL_AMASK  0x00000400 /* Indicates ACTIVE inhibits PIO's */
 173
 174         hpcreg tx_gfptr;   /* current GIO fifo ptr */
 175         hpcreg tx_dfptr;   /* current device fifo ptr */
 176         char _unused5[PAGE_SIZE - (4 * sizeof(hpcreg))]; /* padding */
 177 };
 178
 179 struct hpc3_regs {
 180         /* First regs for the PBUS 8 dma channels. */
 181         struct hpc3_pbus_dmacregs pbdma0, pbdma1, pbdma2, pbdma3;
 182         struct hpc3_pbus_dmacregs pbdma4, pbdma5, pbdma6, pbdma7;
 183
 184         /* Now the HPC scsi registers, we get two scsi reg sets. */
 185         struct hpc3_scsiregs scsi_chan0, scsi_chan1;
 186
 187         /* The SEEQ hpc3 ethernet dma/control registers. */
 188         struct hpc3_ethregs ethregs;
 189
 190         /* Here are where the hpc3 fifo's can be directly accessed
 191          * via PIO accesses.  Under normal operation we never stick
 192          * our grubby paws in here so it's just padding.
 193          */
 194         char _unused1[PAGE_SIZE * 16];
 195
 196         /* HPC3 irq status regs.  Due to a peculiar bug you need to
 197          * look at two different register addresses to get at all of
 198          * the status bits.  The first reg can only reliably report
 199          * bits 4:0 of the status, and the second reg can only
 200          * reliably report bits 9:5 of the hpc3 irq status.  I told
 201          * you it was a peculiar bug. ;-)
 202          */
 203         hpcreg istat0;      /* Irq status, only bits <4:0> reliable. */
 204 #define HPC3_ISTAT_PBIMASK  0x0ff  /* irq bits for pbus devs 0 --> 7 */
 205 #define HPC3_ISTAT_SC0MASK  0x100  /* irq bit for scsi channel 0 */
 206 #define HPC3_ISTAT_SC1MASK  0x200  /* irq bit for scsi channel 1 */
 207
 208         hpcreg gio64_misc;  /* GIO64 misc control bits. */
 209 #define HPC3_GIOMISC_ERTIME   0x1    /* Enable external timer real time. */
 210 #define HPC3_GIOMISC_DENDIAN  0x2    /* dma descriptor endian, 1=lit 0=big */
 211
 212         hpcreg eeprom_data; /* EEPROM data reg. */
 213 #define HPC3_EEPROM_EPROT     0x01   /* Protect register enable */
 214 #define HPC3_EEPROM_CSEL      0x02   /* Chip select */
 215 #define HPC3_EEPROM_ECLK      0x04   /* EEPROM clock */
 216 #define HPC3_EEPROM_DATO      0x08   /* Data out */
 217 #define HPC3_EEPROM_DATI      0x10   /* Data in */
 218
 219         hpcreg istat1;      /* Irq status, only bits <9:5> reliable. */
 220         hpcreg gio64_estat; /* GIO64 error interrupt status reg. */
 221 #define HPC3_GIOESTAT_BLMASK  0x000ff  /* Bus lane where bad parity occurred */
 222 #define HPC3_GIOESTAT_CTYPE   0x00100  /* Bus cycle type, 0=PIO 1=DMA */
 223 #define HPC3_GIOESTAT_PIDMSK  0x3f700  /* DMA channel parity identifier */
 224
 225         /* Now direct PIO per-HPC3 peripheral access to external regs. */
 226         char _unused2[0x13ff0]; /* Trust me... */
 227         hpcreg scsi0_ext[256];  /* SCSI channel 0 external regs */
 228         char _unused3[0x07c00]; /* Trust me... */
 229         hpcreg scsi1_ext[256];  /* SCSI channel 1 external regs */
 230         char _unused4[0x07c00]; /* It'll only hurt a little... */
 231
 232         /* Per-peripheral device external registers and dma/pio control. */
 233         hpcreg pbus_extregs[256][10]; /* 2nd indice indexes controller */
 234         hpcreg pbus_dmacfgs[128][10]; /* 2nd indice indexes controller */
 235 #define HPC3_PIODCFG_D3R    0x00000001 /* Cycles to spend in D3 for reads */
 236 #define HPC3_PIODCFG_D4R    0x0000001e /* Cycles to spend in D4 for reads */
 237 #define HPC3_PIODCFG_D5R    0x000001e0 /* Cycles to spend in D5 for reads */
 238 #define HPC3_PIODCFG_D3W    0x00000200 /* Cycles to spend in D3 for writes */
 239 #define HPC3_PIODCFG_D4W    0x00003c00 /* Cycles to spend in D4 for writes */
 240 #define HPC3_PIODCFG_D5W    0x0003c000 /* Cycles to spend in D5 for writes */
 241 #define HPC3_PIODCFG_HWORD  0x00040000 /* Enable 16-bit dma access mode */
 242 #define HPC3_PIODCFG_EHI    0x00080000 /* Places halfwords on high 16 bits of bus */
 243 #define HPC3_PIODCFG_RTIME  0x00200000 /* Make this device real time on GIO bus */
 244 #define HPC3_PIODCFG_BURST  0x07c00000 /* 5 bit burst count for DMA device */
 245 #define HPC3_PIODCFG_DRQLV  0x08000000 /* Use live pbus_dreq unsynchronized signal */
 246
 247         hpcreg pbus_piocfgs[64][10]; /* 2nd indice indexes controller */
 248 #define HPC3_PIOPCFG_RP2    0x00001  /* Cycles to spend in P2 state for reads */
 249 #define HPC3_PIOPCFG_RP3    0x0001e  /* Cycles to spend in P3 state for reads */
 250 #define HPC3_PIOPCFG_RP4    0x001e0  /* Cycles to spend in P4 state for reads */
 251 #define HPC3_PIOPCFG_WP2    0x00200  /* Cycles to spend in P2 state for writes */
 252 #define HPC3_PIOPCFG_WP3    0x03c00  /* Cycles to spend in P3 state for writes */
 253 #define HPC3_PIOPCFG_WP4    0x3c000  /* Cycles to spend in P4 state for writes */
 254 #define HPC3_PIOPCFG_HW     0x40000  /* Enable 16-bit PIO accesses */
 255 #define HPC3_PIOPCFG_EHI    0x80000  /* Place even address bits in bits <15:8> */
 256
 257         /* PBUS PROM control regs. */
 258         hpcreg pbus_promwe;     /* PROM write enable register */
 259 #define HPC3_PROM_WENAB     0x1 /* Enable writes to the PROM */
 260
 261         char _unused5[0x800 - sizeof(hpcreg)];
 262         hpcreg pbus_promswap;   /* Chip select swap reg */
 263 #define HPC3_PROM_SWAP      0x1 /* invert GIO addr bit to select prom0 or prom1 */
 264
 265         char _unused6[0x800 - sizeof(hpcreg)];
 266         hpcreg pbus_gout;       /* PROM general purpose output reg */
 267 #define HPC3_PROM_STAT      0x1 /* General purpose status bit in gout */
 268
 269         char _unused7[0x1000 - sizeof(hpcreg)];
 270         hpcreg pbus_promram[16384]; /* 64k of PROM battery backed ram */
 271 };
 272
 273 /* It is possible to have two HPC3's within the address space on
 274  * one machine, though only having one is more likely on an INDY.
 275  * Controller 0 lives at physical address 0x1fb80000 and the controller
 276  * 1 if present lives at address 0x1fb00000.
 277  */
 278 extern struct hpc3_regs *hpc3c0, *hpc3c1;
 279 #define HPC3_CHIP0_PBASE   0x1fb80000 /* physical */
 280 #define HPC3_CHIP1_PBASE   0x1fb00000 /* physical */
 281
 282 /* Control and misc status information, these live in pbus channel 6. */
 283 struct hpc3_miscregs {
 284         hpcreg pdata, pctrl, pstat, pdmactrl, pistat, pimask;
 285         hpcreg ptimer1, ptimer2, ptimer3, ptimer4;
 286         hpcreg _unused1[2];
 287         hpcreg ser1cmd, ser1data;
 288         hpcreg ser0cmd, ser0data;
 289         hpcreg kbdmouse0, kbdmouse1;
 290         hpcreg gcsel, genctrl, panel;
 291         hpcreg _unused2;
 292         hpcreg sysid;
 293         hpcreg _unused3;
 294         hpcreg read, _unused4;
 295         hpcreg dselect;
 296 #define HPC3_DSELECT_SCLK10MHZ   0x00 /* use 10MHZ serial clock */
 297 #define HPC3_DSELECT_ISDNB       0x01 /* enable isdn B */
 298 #define HPC3_DSELECT_ISDNA       0x02 /* enable isdn A */
 299 #define HPC3_DSELECT_LPR         0x04 /* use parallel DMA */
 300 #define HPC3_DSELECT_SCLK667MHZ  0x10 /* use 6.67MHZ serial clock */
 301 #define HPC3_DSELECT_SCLKEXT     0x20 /* use external serial clock */
 302
 303         hpcreg _unused5;
 304         hpcreg write1;
 305 #define HPC3_WRITE1_PRESET    0x01  /* 0=LPR_RESET, 1=NORMAL */
 306 #define HPC3_WRITE1_KMRESET   0x02  /* 0=KBDMOUSE_RESET, 1=NORMAL */
 307 #define HPC3_WRITE1_ERESET    0x04  /* 0=EISA_RESET, 1=NORMAL */
 308 #define HPC3_WRITE1_GRESET    0x08  /* 0=MAGIC_GIO_RESET, 1=NORMAL */
 309 #define HPC3_WRITE1_LC0OFF    0x10  /* turn led off (guiness=red, else green) */
 310 #define HPC3_WRITE1_LC1OFF    0x20  /* turn led off (guiness=green, else amber) */
 311
 312         hpcreg _unused6;
 313         hpcreg write2;
 314 #define HPC3_WRITE2_NTHRESH  0x01 /* use 4.5db threshhold */
 315 #define HPC3_WRITE2_TPSPEED  0x02 /* use 100ohm TP speed */
 316 #define HPC3_WRITE2_EPSEL    0x04 /* force cable mode: 1=AUI 0=TP */
 317 #define HPC3_WRITE2_EASEL    0x08 /* 1=autoselect 0=manual cable selection */
 318 #define HPC3_WRITE2_U1AMODE  0x10 /* 1=PC 0=MAC UART mode */
 319 #define HPC3_WRITE2_U0AMODE  0x20 /* 1=PC 0=MAC UART mode */
 320 #define HPC3_WRITE2_MLO      0x40 /* 1=4.75V 0=+5V */
 321 #define HPC3_WRITE2_MHI      0x80 /* 1=5.25V 0=+5V */
 322 };
 323 extern struct hpc3_miscregs *hpc3mregs;
 324 #define HPC3_MREGS_PBASE   0x1fbd9800 /* physical */
 325
 326 /* We need software copies of these because they are write only. */
 327 extern unsigned long sgi_hpc_write1, sgi_hpc_write2;
 328
 329 #define SGI_KEYBOARD_IRQ 20
 330
 331 struct hpc_keyb {
 332 #ifdef __MIPSEB__
 333         unsigned char _unused0[3];
 334         volatile unsigned char data;
 335         unsigned char _unused1[3];
 336         volatile unsigned char command;
 337 #else
 338         volatile unsigned char data;
 339         unsigned char _unused0[3];
 340         volatile unsigned char command;
 341         unsigned char _unused1[3];
 342 #endif
 343 };
 344
 345 /* Indy RTC  */
 346
 347 /* The layout of registers for the INDY Dallas 1286 clock chipset. */
 348 struct indy_clock {
 349         volatile unsigned int hsec;
 350         volatile unsigned int sec;
 351         volatile unsigned int min;
 352         volatile unsigned int malarm;
 353         volatile unsigned int hr;
 354         volatile unsigned int halarm;
 355         volatile unsigned int day;
 356         volatile unsigned int dalarm;
 357         volatile unsigned int date;
 358         volatile unsigned int month;
 359         volatile unsigned int year;
 360         volatile unsigned int cmd;
 361         volatile unsigned int whsec;
 362         volatile unsigned int wsec;
 363         volatile unsigned int _unused0[50];
 364 };
 365
 366 #define INDY_CLOCK_REGS (KSEG1ADDR(0x1fbe0000))
 367
 368 extern void sgihpc_init(void);
 369
 370 #endif /* !(_MIPS_SGIHPC_H) */