2 * Regular lowlevel cardbus driver ("yenta")
4 * (C) Copyright 1999, 2000 Linus Torvalds
6 #include <linux/init.h>
8 #include <linux/sched.h>
9 #include <linux/interrupt.h>
10 #include <linux/delay.h>
11 #include <linux/module.h>
13 #include <pcmcia/version.h>
14 #include <pcmcia/cs_types.h>
15 #include <pcmcia/ss.h>
16 #include <pcmcia/cs.h>
24 #define DEBUG(x,args...) printk(__FUNCTION__ ": " x,##args)
26 #define DEBUG(x,args...)
30 #define to_cycles(ns) ((ns)/120)
31 #define to_ns(cycles) ((cycles)*120)
34 * Generate easy-to-use ways of reading a cardbus sockets
35 * regular memory space ("cb_xxx"), configuration space
36 * ("config_xxx") and compatibility space ("exca_xxxx")
38 static inline u32
cb_readl(pci_socket_t
*socket
, unsigned reg
)
40 u32 val
= readl(socket
->base
+ reg
);
41 DEBUG("%p %04x %08x\n", socket
, reg
, val
);
45 static inline void cb_writel(pci_socket_t
*socket
, unsigned reg
, u32 val
)
47 DEBUG("%p %04x %08x\n", socket
, reg
, val
);
48 writel(val
, socket
->base
+ reg
);
51 static inline u8
config_readb(pci_socket_t
*socket
, unsigned offset
)
54 pci_read_config_byte(socket
->dev
, offset
, &val
);
55 DEBUG("%p %04x %02x\n", socket
, offset
, val
);
59 static inline u16
config_readw(pci_socket_t
*socket
, unsigned offset
)
62 pci_read_config_word(socket
->dev
, offset
, &val
);
63 DEBUG("%p %04x %04x\n", socket
, offset
, val
);
67 static inline u32
config_readl(pci_socket_t
*socket
, unsigned offset
)
70 pci_read_config_dword(socket
->dev
, offset
, &val
);
71 DEBUG("%p %04x %08x\n", socket
, offset
, val
);
75 static inline void config_writeb(pci_socket_t
*socket
, unsigned offset
, u8 val
)
77 DEBUG("%p %04x %02x\n", socket
, offset
, val
);
78 pci_write_config_byte(socket
->dev
, offset
, val
);
81 static inline void config_writew(pci_socket_t
*socket
, unsigned offset
, u16 val
)
83 DEBUG("%p %04x %04x\n", socket
, offset
, val
);
84 pci_write_config_word(socket
->dev
, offset
, val
);
87 static inline void config_writel(pci_socket_t
*socket
, unsigned offset
, u32 val
)
89 DEBUG("%p %04x %08x\n", socket
, offset
, val
);
90 pci_write_config_dword(socket
->dev
, offset
, val
);
93 static inline u8
exca_readb(pci_socket_t
*socket
, unsigned reg
)
95 u8 val
= readb(socket
->base
+ 0x800 + reg
);
96 DEBUG("%p %04x %02x\n", socket
, reg
, val
);
100 static inline u8
exca_readw(pci_socket_t
*socket
, unsigned reg
)
103 val
= readb(socket
->base
+ 0x800 + reg
);
104 val
|= readb(socket
->base
+ 0x800 + reg
+ 1) << 8;
105 DEBUG("%p %04x %04x\n", socket
, reg
, val
);
109 static inline void exca_writeb(pci_socket_t
*socket
, unsigned reg
, u8 val
)
111 DEBUG("%p %04x %02x\n", socket
, reg
, val
);
112 writeb(val
, socket
->base
+ 0x800 + reg
);
115 static void exca_writew(pci_socket_t
*socket
, unsigned reg
, u16 val
)
117 DEBUG("%p %04x %04x\n", socket
, reg
, val
);
118 writeb(val
, socket
->base
+ 0x800 + reg
);
119 writeb(val
>> 8, socket
->base
+ 0x800 + reg
+ 1);
123 * Ugh, mixed-mode cardbus and 16-bit pccard state: things depend
124 * on what kind of card is inserted..
126 static int yenta_get_status(pci_socket_t
*socket
, unsigned int *value
)
129 u32 state
= cb_readl(socket
, CB_SOCKET_STATE
);
131 val
= (state
& CB_3VCARD
) ? SS_3VCARD
: 0;
132 val
|= (state
& CB_XVCARD
) ? SS_XVCARD
: 0;
133 val
|= (state
& (CB_CDETECT1
| CB_CDETECT2
| CB_5VCARD
| CB_3VCARD
134 | CB_XVCARD
| CB_YVCARD
)) ? 0 : SS_PENDING
;
136 if (state
& CB_CBCARD
) {
138 val
|= (state
& CB_CARDSTS
) ? SS_STSCHG
: 0;
139 val
|= (state
& (CB_CDETECT1
| CB_CDETECT2
)) ? 0 : SS_DETECT
;
140 val
|= (state
& CB_PWRCYCLE
) ? SS_POWERON
| SS_READY
: 0;
142 u8 status
= exca_readb(socket
, I365_STATUS
);
143 val
|= ((status
& I365_CS_DETECT
) == I365_CS_DETECT
) ? SS_DETECT
: 0;
144 if (exca_readb(socket
, I365_INTCTL
) & I365_PC_IOCARD
) {
145 val
|= (status
& I365_CS_STSCHG
) ? 0 : SS_STSCHG
;
147 val
|= (status
& I365_CS_BVD1
) ? 0 : SS_BATDEAD
;
148 val
|= (status
& I365_CS_BVD2
) ? 0 : SS_BATWARN
;
150 val
|= (status
& I365_CS_WRPROT
) ? SS_WRPROT
: 0;
151 val
|= (status
& I365_CS_READY
) ? SS_READY
: 0;
152 val
|= (status
& I365_CS_POWERON
) ? SS_POWERON
: 0;
159 static int yenta_Vcc_power(u32 control
)
161 switch (control
& CB_SC_VCC_MASK
) {
162 case CB_SC_VCC_5V
: return 50;
163 case CB_SC_VCC_3V
: return 33;
168 static int yenta_Vpp_power(u32 control
)
170 switch (control
& CB_SC_VPP_MASK
) {
171 case CB_SC_VPP_12V
: return 120;
172 case CB_SC_VPP_5V
: return 50;
173 case CB_SC_VPP_3V
: return 33;
178 static int yenta_get_socket(pci_socket_t
*socket
, socket_state_t
*state
)
183 control
= cb_readl(socket
, CB_SOCKET_CONTROL
);
185 state
->Vcc
= yenta_Vcc_power(control
);
186 state
->Vpp
= yenta_Vpp_power(control
);
187 state
->io_irq
= socket
->io_irq
;
189 if (cb_readl(socket
, CB_SOCKET_STATE
) & CB_CBCARD
) {
190 u16 bridge
= config_readw(socket
, CB_BRIDGE_CONTROL
);
191 if (bridge
& CB_BRIDGE_CRST
)
192 state
->flags
|= SS_RESET
;
196 /* 16-bit card state.. */
197 reg
= exca_readb(socket
, I365_POWER
);
198 state
->flags
= (reg
& I365_PWR_AUTO
) ? SS_PWR_AUTO
: 0;
199 state
->flags
|= (reg
& I365_PWR_OUT
) ? SS_OUTPUT_ENA
: 0;
201 reg
= exca_readb(socket
, I365_INTCTL
);
202 state
->flags
|= (reg
& I365_PC_RESET
) ? 0 : SS_RESET
;
203 state
->flags
|= (reg
& I365_PC_IOCARD
) ? SS_IOCARD
: 0;
205 reg
= exca_readb(socket
, I365_CSCINT
);
206 state
->csc_mask
= (reg
& I365_CSC_DETECT
) ? SS_DETECT
: 0;
207 if (state
->flags
& SS_IOCARD
) {
208 state
->csc_mask
|= (reg
& I365_CSC_STSCHG
) ? SS_STSCHG
: 0;
210 state
->csc_mask
|= (reg
& I365_CSC_BVD1
) ? SS_BATDEAD
: 0;
211 state
->csc_mask
|= (reg
& I365_CSC_BVD2
) ? SS_BATWARN
: 0;
212 state
->csc_mask
|= (reg
& I365_CSC_READY
) ? SS_READY
: 0;
218 static void yenta_set_power(pci_socket_t
*socket
, socket_state_t
*state
)
220 u32 reg
= 0; /* CB_SC_STPCLK? */
221 switch (state
->Vcc
) {
222 case 33: reg
= CB_SC_VCC_3V
; break;
223 case 50: reg
= CB_SC_VCC_5V
; break;
224 default: reg
= 0; break;
226 switch (state
->Vpp
) {
227 case 33: reg
|= CB_SC_VPP_3V
; break;
228 case 50: reg
|= CB_SC_VPP_5V
; break;
229 case 120: reg
|= CB_SC_VPP_12V
; break;
231 if (reg
!= cb_readl(socket
, CB_SOCKET_CONTROL
))
232 cb_writel(socket
, CB_SOCKET_CONTROL
, reg
);
235 static int yenta_set_socket(pci_socket_t
*socket
, socket_state_t
*state
)
239 if (state
->flags
& SS_DEBOUNCED
) {
240 /* The insertion debounce period has ended. Clear any pending insertion events */
241 socket
->events
&= ~SS_DETECT
;
242 state
->flags
&= ~SS_DEBOUNCED
; /* SS_DEBOUNCED is oneshot */
244 yenta_set_power(socket
, state
);
245 socket
->io_irq
= state
->io_irq
;
246 bridge
= config_readw(socket
, CB_BRIDGE_CONTROL
) & ~(CB_BRIDGE_CRST
| CB_BRIDGE_INTR
);
247 if (cb_readl(socket
, CB_SOCKET_STATE
) & CB_CBCARD
) {
249 bridge
|= (state
->flags
& SS_RESET
) ? CB_BRIDGE_CRST
: 0;
251 /* ISA interrupt control? */
252 intr
= exca_readb(socket
, I365_INTCTL
);
253 intr
= (intr
& ~0xf);
254 if (!socket
->cb_irq
) {
255 intr
|= state
->io_irq
;
256 bridge
|= CB_BRIDGE_INTR
;
258 exca_writeb(socket
, I365_INTCTL
, intr
);
262 reg
= exca_readb(socket
, I365_INTCTL
) & (I365_RING_ENA
| I365_INTR_ENA
);
263 reg
|= (state
->flags
& SS_RESET
) ? 0 : I365_PC_RESET
;
264 reg
|= (state
->flags
& SS_IOCARD
) ? I365_PC_IOCARD
: 0;
265 if (state
->io_irq
!= socket
->cb_irq
) {
266 reg
|= state
->io_irq
;
267 bridge
|= CB_BRIDGE_INTR
;
269 exca_writeb(socket
, I365_INTCTL
, reg
);
271 reg
= exca_readb(socket
, I365_POWER
) & (I365_VCC_MASK
|I365_VPP1_MASK
);
272 reg
|= I365_PWR_NORESET
;
273 if (state
->flags
& SS_PWR_AUTO
) reg
|= I365_PWR_AUTO
;
274 if (state
->flags
& SS_OUTPUT_ENA
) reg
|= I365_PWR_OUT
;
275 if (exca_readb(socket
, I365_POWER
) != reg
)
276 exca_writeb(socket
, I365_POWER
, reg
);
278 /* CSC interrupt: no ISA irq for CSC */
279 reg
= I365_CSC_DETECT
;
280 if (state
->flags
& SS_IOCARD
) {
281 if (state
->csc_mask
& SS_STSCHG
) reg
|= I365_CSC_STSCHG
;
283 if (state
->csc_mask
& SS_BATDEAD
) reg
|= I365_CSC_BVD1
;
284 if (state
->csc_mask
& SS_BATWARN
) reg
|= I365_CSC_BVD2
;
285 if (state
->csc_mask
& SS_READY
) reg
|= I365_CSC_READY
;
287 exca_writeb(socket
, I365_CSCINT
, reg
);
288 exca_readb(socket
, I365_CSC
);
290 config_writew(socket
, CB_BRIDGE_CONTROL
, bridge
);
291 /* Socket event mask: get card insert/remove events.. */
292 cb_writel(socket
, CB_SOCKET_EVENT
, -1);
293 cb_writel(socket
, CB_SOCKET_MASK
, CB_CDMASK
);
297 static int yenta_get_io_map(pci_socket_t
*socket
, struct pccard_io_map
*io
)
300 unsigned char ioctl
, addr
;
306 io
->start
= exca_readw(socket
, I365_IO(map
)+I365_W_START
);
307 io
->stop
= exca_readw(socket
, I365_IO(map
)+I365_W_STOP
);
309 ioctl
= exca_readb(socket
, I365_IOCTL
);
310 addr
= exca_readb(socket
, I365_ADDRWIN
);
311 io
->speed
= to_ns(ioctl
& I365_IOCTL_WAIT(map
)) ? 1 : 0;
312 io
->flags
= (addr
& I365_ENA_IO(map
)) ? MAP_ACTIVE
: 0;
313 io
->flags
|= (ioctl
& I365_IOCTL_0WS(map
)) ? MAP_0WS
: 0;
314 io
->flags
|= (ioctl
& I365_IOCTL_16BIT(map
)) ? MAP_16BIT
: 0;
315 io
->flags
|= (ioctl
& I365_IOCTL_IOCS16(map
)) ? MAP_AUTOSZ
: 0;
320 static int yenta_set_io_map(pci_socket_t
*socket
, struct pccard_io_map
*io
)
323 unsigned char ioctl
, addr
, enable
;
330 enable
= I365_ENA_IO(map
);
331 addr
= exca_readb(socket
, I365_ADDRWIN
);
333 /* Disable the window before changing it.. */
336 exca_writeb(socket
, I365_ADDRWIN
, addr
);
339 exca_writew(socket
, I365_IO(map
)+I365_W_START
, io
->start
);
340 exca_writew(socket
, I365_IO(map
)+I365_W_STOP
, io
->stop
);
342 ioctl
= exca_readb(socket
, I365_IOCTL
) & ~I365_IOCTL_MASK(map
);
343 if (io
->flags
& MAP_0WS
) ioctl
|= I365_IOCTL_0WS(map
);
344 if (io
->flags
& MAP_16BIT
) ioctl
|= I365_IOCTL_16BIT(map
);
345 if (io
->flags
& MAP_AUTOSZ
) ioctl
|= I365_IOCTL_IOCS16(map
);
346 exca_writeb(socket
, I365_IOCTL
, ioctl
);
348 if (io
->flags
& MAP_ACTIVE
)
349 exca_writeb(socket
, I365_ADDRWIN
, addr
| enable
);
353 static int yenta_get_mem_map(pci_socket_t
*socket
, struct pccard_mem_map
*mem
)
357 unsigned int start
, stop
, page
, offset
;
363 addr
= exca_readb(socket
, I365_ADDRWIN
);
364 mem
->flags
= (addr
& I365_ENA_MEM(map
)) ? MAP_ACTIVE
: 0;
366 start
= exca_readw(socket
, I365_MEM(map
) + I365_W_START
);
367 mem
->flags
|= (start
& I365_MEM_16BIT
) ? MAP_16BIT
: 0;
368 mem
->flags
|= (start
& I365_MEM_0WS
) ? MAP_0WS
: 0;
369 start
= (start
& 0x0fff) << 12;
371 stop
= exca_readw(socket
, I365_MEM(map
) + I365_W_STOP
);
372 mem
->speed
= to_ns(stop
>> 14);
373 stop
= ((stop
& 0x0fff) << 12) + 0x0fff;
375 offset
= exca_readw(socket
, I365_MEM(map
) + I365_W_OFF
);
376 mem
->flags
|= (offset
& I365_MEM_WRPROT
) ? MAP_WRPROT
: 0;
377 mem
->flags
|= (offset
& I365_MEM_REG
) ? MAP_ATTRIB
: 0;
378 offset
= ((offset
& 0x3fff) << 12) + start
;
379 mem
->card_start
= offset
& 0x3ffffff;
381 page
= exca_readb(socket
, CB_MEM_PAGE(map
)) << 24;
382 mem
->sys_start
= start
+ page
;
383 mem
->sys_stop
= start
+ page
;
388 static int yenta_set_mem_map(pci_socket_t
*socket
, struct pccard_mem_map
*mem
)
391 unsigned char addr
, enable
;
392 unsigned int start
, stop
, card_start
;
396 start
= mem
->sys_start
;
397 stop
= mem
->sys_stop
;
398 card_start
= mem
->card_start
;
400 if (map
> 4 || start
> stop
|| ((start
^ stop
) >> 24) ||
401 (card_start
>> 26) || mem
->speed
> 1000)
404 enable
= I365_ENA_MEM(map
);
405 addr
= exca_readb(socket
, I365_ADDRWIN
);
408 exca_writeb(socket
, I365_ADDRWIN
, addr
);
411 exca_writeb(socket
, CB_MEM_PAGE(map
), start
>> 24);
413 word
= (start
>> 12) & 0x0fff;
414 if (mem
->flags
& MAP_16BIT
)
415 word
|= I365_MEM_16BIT
;
416 if (mem
->flags
& MAP_0WS
)
417 word
|= I365_MEM_0WS
;
418 exca_writew(socket
, I365_MEM(map
) + I365_W_START
, word
);
420 word
= (stop
>> 12) & 0x0fff;
421 switch (to_cycles(mem
->speed
)) {
423 case 1: word
|= I365_MEM_WS0
; break;
424 case 2: word
|= I365_MEM_WS1
; break;
425 default: word
|= I365_MEM_WS1
| I365_MEM_WS0
; break;
427 exca_writew(socket
, I365_MEM(map
) + I365_W_STOP
, word
);
429 word
= ((card_start
- start
) >> 12) & 0x3fff;
430 if (mem
->flags
& MAP_WRPROT
)
431 word
|= I365_MEM_WRPROT
;
432 if (mem
->flags
& MAP_ATTRIB
)
433 word
|= I365_MEM_REG
;
434 exca_writew(socket
, I365_MEM(map
) + I365_W_OFF
, word
);
436 if (mem
->flags
& MAP_ACTIVE
)
437 exca_writeb(socket
, I365_ADDRWIN
, addr
| enable
);
441 static void yenta_proc_setup(pci_socket_t
*socket
, struct proc_dir_entry
*base
)
446 static unsigned int yenta_events(pci_socket_t
*socket
)
452 /* Clear interrupt status for the event */
453 cb_event
= cb_readl(socket
, CB_SOCKET_EVENT
);
454 cb_writel(socket
, CB_SOCKET_EVENT
, cb_event
);
456 csc
= exca_readb(socket
, I365_CSC
);
458 events
= (cb_event
& (CB_CD1EVENT
| CB_CD2EVENT
)) ? SS_DETECT
: 0 ;
459 events
|= (csc
& I365_CSC_DETECT
) ? SS_DETECT
: 0;
460 if (exca_readb(socket
, I365_INTCTL
) & I365_PC_IOCARD
) {
461 events
|= (csc
& I365_CSC_STSCHG
) ? SS_STSCHG
: 0;
463 events
|= (csc
& I365_CSC_BVD1
) ? SS_BATDEAD
: 0;
464 events
|= (csc
& I365_CSC_BVD2
) ? SS_BATWARN
: 0;
465 events
|= (csc
& I365_CSC_READY
) ? SS_READY
: 0;
471 static void yenta_bh(void *data
)
473 pci_socket_t
*socket
= data
;
476 spin_lock_irq(&socket
->event_lock
);
477 events
= socket
->events
;
479 spin_unlock_irq(&socket
->event_lock
);
481 socket
->handler(socket
->info
, events
);
484 static void yenta_interrupt(int irq
, void *dev_id
, struct pt_regs
*regs
)
487 pci_socket_t
*socket
= (pci_socket_t
*) dev_id
;
489 events
= yenta_events(socket
);
491 spin_lock(&socket
->event_lock
);
492 socket
->events
|= events
;
493 spin_unlock(&socket
->event_lock
);
494 schedule_task(&socket
->tq_task
);
498 static void yenta_interrupt_wrapper(unsigned long data
)
500 pci_socket_t
*socket
= (pci_socket_t
*) data
;
502 yenta_interrupt(0, (void *)socket
, NULL
);
503 socket
->poll_timer
.expires
= jiffies
+ HZ
;
504 add_timer(&socket
->poll_timer
);
508 * Only probe "regular" interrupts, don't
509 * touch dangerous spots like the mouse irq,
510 * because there are mice that apparently
511 * get really confused if they get fondled
514 * Default to 11, 10, 9, 7, 6, 5, 4, 3.
516 static u32 isa_interrupts
= 0x0ef8;
518 static unsigned int yenta_probe_irq(pci_socket_t
*socket
, u32 isa_irq_mask
)
525 /* Set up ISA irq routing to probe the ISA irqs.. */
526 bridge_ctrl
= config_readw(socket
, CB_BRIDGE_CONTROL
);
527 if (!(bridge_ctrl
& CB_BRIDGE_INTR
)) {
528 bridge_ctrl
|= CB_BRIDGE_INTR
;
529 config_writew(socket
, CB_BRIDGE_CONTROL
, bridge_ctrl
);
533 * Probe for usable interrupts using the force
534 * register to generate bogus card status events.
536 cb_writel(socket
, CB_SOCKET_EVENT
, -1);
537 cb_writel(socket
, CB_SOCKET_MASK
, CB_CSTSMASK
);
538 exca_writeb(socket
, I365_CSCINT
, 0);
539 val
= probe_irq_on() & isa_irq_mask
;
540 for (i
= 1; i
< 16; i
++) {
541 if (!((val
>> i
) & 1))
543 exca_writeb(socket
, I365_CSCINT
, I365_CSC_STSCHG
| (i
<< 4));
544 cb_writel(socket
, CB_SOCKET_FORCE
, CB_FCARDSTS
);
546 cb_writel(socket
, CB_SOCKET_EVENT
, -1);
548 cb_writel(socket
, CB_SOCKET_MASK
, 0);
549 exca_writeb(socket
, I365_CSCINT
, 0);
551 mask
= probe_irq_mask(val
) & 0xffff;
553 bridge_ctrl
&= ~CB_BRIDGE_INTR
;
554 config_writew(socket
, CB_BRIDGE_CONTROL
, bridge_ctrl
);
560 * Set static data that doesn't need re-initializing..
562 static void yenta_get_socket_capabilities(pci_socket_t
*socket
, u32 isa_irq_mask
)
564 socket
->cap
.features
|= SS_CAP_PAGE_REGS
| SS_CAP_PCCARD
| SS_CAP_CARDBUS
;
565 socket
->cap
.map_size
= 0x1000;
566 socket
->cap
.pci_irq
= socket
->cb_irq
;
567 socket
->cap
.irq_mask
= yenta_probe_irq(socket
, isa_irq_mask
);
568 socket
->cap
.cb_dev
= socket
->dev
;
569 socket
->cap
.bus
= NULL
;
571 printk("Yenta IRQ list %04x, PCI irq%d\n", socket
->cap
.irq_mask
, socket
->cb_irq
);
574 extern void cardbus_register(pci_socket_t
*socket
);
577 * 'Bottom half' for the yenta_open routine. Allocate the interrupt line
578 * and register the socket with the upper layers.
580 static void yenta_open_bh(void * data
)
582 pci_socket_t
* socket
= (pci_socket_t
*) data
;
584 /* It's OK to overwrite this now */
585 socket
->tq_task
.routine
= yenta_bh
;
587 if (!socket
->cb_irq
|| request_irq(socket
->cb_irq
, yenta_interrupt
, SA_SHIRQ
, socket
->dev
->name
, socket
)) {
588 /* No IRQ or request_irq failed. Poll */
589 socket
->cb_irq
= 0; /* But zero is a valid IRQ number. */
590 socket
->poll_timer
.function
= yenta_interrupt_wrapper
;
591 socket
->poll_timer
.data
= (unsigned long)socket
;
592 socket
->poll_timer
.expires
= jiffies
+ HZ
;
593 add_timer(&socket
->poll_timer
);
596 /* Figure out what the dang thing can do for the PCMCIA layer... */
597 yenta_get_socket_capabilities(socket
, isa_interrupts
);
598 printk("Socket status: %08x\n", cb_readl(socket
, CB_SOCKET_STATE
));
600 /* Register it with the pcmcia layer.. */
601 cardbus_register(socket
);
606 static void yenta_clear_maps(pci_socket_t
*socket
)
609 pccard_io_map io
= { 0, 0, 0, 0, 1 };
610 pccard_mem_map mem
= { 0, 0, 0, 0, 0, 0 };
612 mem
.sys_stop
= 0x0fff;
613 yenta_set_socket(socket
, &dead_socket
);
614 for (i
= 0; i
< 2; i
++) {
616 yenta_set_io_map(socket
, &io
);
618 for (i
= 0; i
< 5; i
++) {
620 yenta_set_mem_map(socket
, &mem
);
625 * Initialize the standard cardbus registers
627 static void yenta_config_init(pci_socket_t
*socket
)
630 struct pci_dev
*dev
= socket
->dev
;
632 pci_set_power_state(socket
->dev
, 0);
634 config_writel(socket
, CB_LEGACY_MODE_BASE
, 0);
635 config_writel(socket
, PCI_BASE_ADDRESS_0
, dev
->resource
[0].start
);
636 config_writew(socket
, PCI_COMMAND
,
642 /* MAGIC NUMBERS! Fixme */
643 config_writeb(socket
, PCI_CACHE_LINE_SIZE
, L1_CACHE_BYTES
/ 4);
644 config_writeb(socket
, PCI_LATENCY_TIMER
, 168);
645 config_writeb(socket
, PCI_SEC_LATENCY_TIMER
, 176);
646 config_writeb(socket
, PCI_PRIMARY_BUS
, dev
->bus
->number
);
647 config_writeb(socket
, PCI_SECONDARY_BUS
, dev
->subordinate
->number
);
648 config_writeb(socket
, PCI_SUBORDINATE_BUS
, dev
->subordinate
->number
);
651 * Set up the bridging state:
652 * - enable write posting.
653 * - memory window 0 prefetchable, window 1 non-prefetchable
654 * - PCI interrupts enabled if a PCI interrupt exists..
656 bridge
= config_readw(socket
, CB_BRIDGE_CONTROL
);
657 bridge
&= ~(CB_BRIDGE_CRST
| CB_BRIDGE_PREFETCH1
| CB_BRIDGE_INTR
| CB_BRIDGE_ISAEN
| CB_BRIDGE_VGAEN
);
658 bridge
|= CB_BRIDGE_PREFETCH0
| CB_BRIDGE_POSTEN
;
660 bridge
|= CB_BRIDGE_INTR
;
661 config_writew(socket
, CB_BRIDGE_CONTROL
, bridge
);
663 exca_writeb(socket
, I365_GBLCTL
, 0x00);
664 exca_writeb(socket
, I365_GENCTL
, 0x00);
666 /* Redo card voltage interrogation */
667 cb_writel(socket
, CB_SOCKET_FORCE
, CB_CVSTEST
);
670 /* Called at resume and initialization events */
671 static int yenta_init(pci_socket_t
*socket
)
673 yenta_config_init(socket
);
674 yenta_clear_maps(socket
);
678 static int yenta_suspend(pci_socket_t
*socket
)
680 yenta_set_socket(socket
, &dead_socket
);
683 * This does not work currently. The controller
684 * loses too much informationduring D3 to come up
685 * cleanly. We should probably fix yenta_init()
686 * to update all the critical registers, notably
687 * the IO and MEM bridging region data.. That is
688 * something that pci_set_power_state() should
689 * probably know about bridges anyway.
691 pci_set_power_state(socket->dev, 3);
697 static void yenta_allocate_res(pci_socket_t
*socket
, int nr
, unsigned type
)
700 struct resource
*root
, *res
;
702 u32 align
, size
, min
, max
;
705 offset
= 0x1c + 8*nr
;
706 bus
= socket
->dev
->subordinate
;
707 res
= socket
->dev
->resource
+ PCI_BRIDGE_RESOURCES
+ nr
;
708 res
->name
= bus
->name
;
712 root
= pci_find_parent_resource(socket
->dev
, res
);
717 start
= config_readl(socket
, offset
);
718 end
= config_readl(socket
, offset
+4) | 0xfff;
719 if (start
&& end
> start
) {
722 request_resource(root
, res
);
726 align
= size
= 4*1024*1024;
727 min
= PCIBIOS_MIN_MEM
; max
= ~0U;
728 if (type
& IORESOURCE_IO
) {
731 min
= PCIBIOS_MIN_IO
;
735 if (allocate_resource(root
, res
, size
, min
, max
, align
, NULL
, NULL
) < 0)
738 config_writel(socket
, offset
, res
->start
);
739 config_writel(socket
, offset
+4, res
->end
);
743 * Allocate the bridge mappings for the device..
745 static void yenta_allocate_resources(pci_socket_t
*socket
)
747 yenta_allocate_res(socket
, 0, IORESOURCE_MEM
|IORESOURCE_PREFETCH
);
748 yenta_allocate_res(socket
, 1, IORESOURCE_MEM
);
749 yenta_allocate_res(socket
, 2, IORESOURCE_IO
);
750 yenta_allocate_res(socket
, 3, IORESOURCE_IO
); /* PCI isn't clever enough to use this one yet */
754 * Close it down - release our resources and go home..
756 static void yenta_close(pci_socket_t
*sock
)
759 free_irq(sock
->cb_irq
, sock
);
761 del_timer_sync(&sock
->poll_timer
);
771 * Different cardbus controllers have slightly different
772 * initialization sequences etc details. List them here..
774 #define PD(x,y) PCI_VENDOR_ID_##x, PCI_DEVICE_ID_##x##_##y
775 static struct cardbus_override_struct
{
776 unsigned short vendor
;
777 unsigned short device
;
778 struct pci_socket_ops
*op
;
779 } cardbus_override
[] = {
780 { PD(TI
,1130), &ti113x_ops
},
781 { PD(TI
,1031), &ti_ops
},
782 { PD(TI
,1131), &ti113x_ops
},
783 { PD(TI
,1250), &ti1250_ops
},
784 { PD(TI
,1220), &ti_ops
},
785 { PD(TI
,1221), &ti_ops
},
786 { PD(TI
,1210), &ti_ops
},
787 { PD(TI
,1450), &ti_ops
},
788 { PD(TI
,1225), &ti_ops
},
789 { PD(TI
,1251A
), &ti_ops
},
790 { PD(TI
,1211), &ti_ops
},
791 { PD(TI
,1251B
), &ti_ops
},
792 { PD(TI
,1420), &ti_ops
},
794 { PD(RICOH
,RL5C465
), &ricoh_ops
},
795 { PD(RICOH
,RL5C466
), &ricoh_ops
},
796 { PD(RICOH
,RL5C475
), &ricoh_ops
},
797 { PD(RICOH
,RL5C476
), &ricoh_ops
},
798 { PD(RICOH
,RL5C478
), &ricoh_ops
}
801 #define NR_OVERRIDES (sizeof(cardbus_override)/sizeof(struct cardbus_override_struct))
804 * Initialize a cardbus controller. Make sure we have a usable
805 * interrupt, and that we can map the cardbus area. Fill in the
806 * socket information structure..
808 static int yenta_open(pci_socket_t
*socket
)
811 struct pci_dev
*dev
= socket
->dev
;
814 * Do some basic sanity checking..
816 if (pci_enable_device(dev
))
818 if (!pci_resource_start(dev
, 0)) {
819 printk("No cardbus resource!\n");
824 * Ok, start setup.. Map the cardbus registers,
825 * and request the IRQ.
827 socket
->base
= ioremap(pci_resource_start(dev
, 0), 0x1000);
831 yenta_config_init(socket
);
833 /* Disable all events */
834 cb_writel(socket
, CB_SOCKET_MASK
, 0x0);
836 /* Set up the bridge regions.. */
837 yenta_allocate_resources(socket
);
839 socket
->cb_irq
= dev
->irq
;
841 /* Do we have special options for the device? */
842 for (i
= 0; i
< NR_OVERRIDES
; i
++) {
843 struct cardbus_override_struct
*d
= cardbus_override
+i
;
844 if (dev
->vendor
== d
->vendor
&& dev
->device
== d
->device
) {
847 int retval
= d
->op
->open(socket
);
854 /* Get the PCMCIA kernel thread to complete the
855 initialisation later. We can't do this here,
856 because, er, because Linus says so :)
858 socket
->tq_task
.routine
= yenta_open_bh
;
859 socket
->tq_task
.data
= socket
;
862 schedule_task(&socket
->tq_task
);
868 * Standard plain cardbus - no frills, no extensions
870 struct pci_socket_ops yenta_operations
= {
884 EXPORT_SYMBOL(yenta_operations
);