nb/intel/i945: Put stage cache in TSEG
[coreboot.git] / src / commonlib / 
tree40ffe0166ec1277b8409032555c873a781e4e338
drwxr-xr-x   ..
-rw-r--r-- 821 Makefile.inc
-rw-r--r-- 8477 cbfs.c
-rw-r--r-- 15248 fsp_relocate.c
drwxr-xr-x - include
-rw-r--r-- 7340 iobuf.c
-rw-r--r-- 10623 lz4.c.inc
-rw-r--r-- 6348 lz4_wrapper.c
-rw-r--r-- 1219 mem_pool.c
-rw-r--r-- 12254 region.c
drwxr-xr-x - storage