| 2016-08-18 | Rizwan Qureshi | skylake: Do FspTempRamInit only for FSP1.1 & tidy up... Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> |
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| 2016-08-17 | Rizwan Qureshi | soc/intel/skylake: restore MCHBAR and DMIBAR programming Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> |
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| 2016-08-11 | Rizwan Qureshi | vendorcode/intel/fsp: Add fsp 2.0 header files for... Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> |
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| 2016-08-06 | Rizwan Qureshi | soc/intel/skylake: Add Kabylake device Ids Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> |
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| 2016-03-12 | Rizwan Qureshi | glados/chell: send an extra VR mailbox command ...Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> |
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| 2016-03-12 | Rizwan Qureshi | soc/intel/skylake: add option to enable VR specific... ...Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> |
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| 2016-01-19 | Rizwan Qureshi | intel/kunimitsu: Enable FspSkipMpInit token ...Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> |
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| 2016-01-16 | Rizwan Qureshi | intel/kunimitsu: remove/disable Wake on lan ...Commit-Ready: Rizwan Qureshi <rizwan.qureshi@intel.com> Original-Tested-by: Rizwan Qureshi <rizwan.qureshi@intel.com> |
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| 2016-01-16 | Rizwan Qureshi | intel/kunimitsu: Add VrConfig UPD parameters ...Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> |
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| 2016-01-16 | Rizwan Qureshi | intel/skylake: Add VrConfig UPD parameters from coreboot ...Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> |
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| 2016-01-16 | Rizwan Qureshi | intel/skylake: Enable SkipMpInit token ...Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> |
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| 2016-01-15 | Rizwan Qureshi | intel/kunimitsu: Add new configuration parameters ...Commit-Ready: Rizwan Qureshi <rizwan.qureshi@intel.com> Original-Tested-by: Rizwan Qureshi <rizwan.qureshi@intel.com> |
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| 2016-01-15 | Rizwan Qureshi | intel/skylake: More UPD params are added for PCH policy... ...Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> |
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| 2015-11-05 | Rizwan Qureshi | skylake: Set Pkg Power clamping bit in Power Limit MSR ...Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> |
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| 2015-10-27 | Rizwan Qureshi | intel/kunimitsu: USB Phy settings and Skip UART2 init... ...Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> |
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| 2015-10-27 | Rizwan Qureshi | intel/skylake: FSP 1.7.0 MemoryInit/SiliconInit params... ...Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> |
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| 2015-08-19 | Rizwan Qureshi | Skylake: update cbmem_top ...Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> |
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| 2015-08-19 | Rizwan Qureshi | skylake: Update Memory and Silicon Init params ...Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> |
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| 2015-07-29 | Rizwan Qureshi | skylake: Update microcode reload in ramstage. ...Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> |
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| 2015-07-29 | Rizwan Qureshi | Add SoC specific microcode update check in ramstage ...Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> |
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| 2015-07-29 | Rizwan Qureshi | Skylake: Fix microcode reload in bootblock cpu init ...Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> |
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