soc/intel/skylake: Add config for mbx command for Intersil VR C-state issues
commitb3e18c7a434700ace381443a0e16718d8c6af7f6
authorRizwan Qureshi <rizwan.qureshi@intel.corp-partner.google.com>
Mon, 25 Sep 2017 12:05:15 +0000 (25 17:35 +0530)
committerMartin Roth <martinroth@google.com>
Thu, 5 Oct 2017 17:46:15 +0000 (5 17:46 +0000)
tree6621c6020ab66951a53ce20bd1d46eaa637116f6
parentbd55c02a2398e2ce95cb06ff9f1e3fb1c20d0ab8
soc/intel/skylake: Add config for mbx command for Intersil VR C-state issues

Config for activating VR mailbox command for Intersil VR C-state issues.
0 - no mailbox command sent.
1 - VR mailbox command sent for IA/GT rails only.
2 - VR mailbox command sent for IA/GT/SA rails.

BUG=b:65499724
BRANCH=none
TEST= build and boot soraka.

Change-Id: Ibcced31b7ba473ffa7368c90c945d07a81a368d4
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/21680
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
src/soc/intel/skylake/chip.h
src/soc/intel/skylake/chip_fsp20.c