vendor/intel/skykabylake: Update FSP header files to version 2.7.2
commitbd55c02a2398e2ce95cb06ff9f1e3fb1c20d0ab8
authorBalaji Manigandan B <balaji.manigandan@intel.com>
Fri, 22 Sep 2017 08:57:56 +0000 (22 14:27 +0530)
committerMartin Roth <martinroth@google.com>
Thu, 5 Oct 2017 17:45:46 +0000 (5 17:45 +0000)
tree17496aca51e0b349ac9816ba9fb27102219cc1ea
parent53b8a82e72b74e7598c5344597e014cd5c6fb49e
vendor/intel/skykabylake: Update FSP header files to version 2.7.2

Update FSP header files to version 2.7.2.

New UPDs added
FspmUpd.h:
 *CleanMemory

FspsUpd.h:
 *IslVrCmd
 *ThreeStrikeCounterDisable

Structure member names used to specify memory configuration
to MRC have been updated, SoC side romstage code is updated
to handle this change.

CQ-DEPEND=CL:*460573,CL:*460612,CL:*460592
BUG=b:65499724
BRANCH=None
TEST= Build and boot soraka, basic sanity check and suspend resume checks.

Change-Id: Ia4eca011bc9a3b1a50e49d6d86a09d05a0cbf151
Signed-off-by: Balaji Manigandan B <balaji.manigandan@intel.com>
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/21679
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
src/soc/intel/skylake/romstage/romstage_fsp20.c
src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspmUpd.h
src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspsUpd.h
src/vendorcode/intel/fsp/fsp2_0/skykabylake/MemInfoHob.h