| commit | 1d900935df918318e198ae61eb8bf42ef1edf674 | |
| author | Lijian Zhao <lijian.zhao@intel.com> | |
| Tue, 25 Sep 2018 22:52:03 +0000 (25 15:52 -0700) | ||
| committer | Patrick Georgi <pgeorgi@google.com> | |
| Fri, 28 Sep 2018 09:53:59 +0000 (28 09:53 +0000) | ||
| tree | a33dc88a6c4331a85ab830fff18aec4f01217fe9 | treesnapshot (tar.gz zip) |
| parent | 4586ccdfe6e62e6c104f65f798e6242c7a146333 | commitdiff |
soc/intel/cannonlake: Add ACPI entry for LAN
Add ACPI DSDT entry for integrated Gigabit LAN controller.
Change-Id: I15bf1d4065894531871380b3318f553b637f4a97
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/28743
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add ACPI DSDT entry for integrated Gigabit LAN controller.
Change-Id: I15bf1d4065894531871380b3318f553b637f4a97
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/28743
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| src/soc/intel/cannonlake/acpi/pch_glan.asl | [new file with mode: 0644] | blob |
| src/soc/intel/cannonlake/acpi/southbridge.asl | diffblobblamehistory |