src/soc/mediatek/mt8186/rtc.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 /*
   4  * This file is created based on MT8186 Functional Specification
   5  * Chapter number: 5.13
   6  */
   7
   8 #include <delay.h>
   9 #include <halt.h>
  10 #include <soc/rtc.h>
  11 #include <soc/rtc_common.h>
  12 #include <soc/mt6366.h>
  13 #include <soc/pmic_wrap.h>
  14 #include <timer.h>
  15
  16 #define RTC_GPIO_USER_MASK        ((1 << 13) - (1 << 8))
  17
  18 /* Initialize RTC setting of using DCXO clock */
  19 static bool rtc_enable_dcxo(void)
  20 {
  21         u16 bbpu, con, osc32con, sec;
  22
  23         rtc_read(RTC_BBPU, &bbpu);
  24         rtc_write(RTC_BBPU, bbpu | RTC_BBPU_KEY | RTC_BBPU_RELOAD);
  25
  26         if (!rtc_write_trigger()) {
  27                 rtc_info("rtc_write_trigger() failed\n");
  28                 return false;
  29         }
  30
  31         mdelay(1);
  32         if (!rtc_writeif_unlock()) {
  33                 rtc_info("rtc_writeif_unlock() failed\n");
  34                 return false;
  35         }
  36
  37         rtc_read(RTC_OSC32CON, &osc32con);
  38         osc32con &= ~(RTC_EMBCK_SRC_SEL | RTC_EMBCK_SEL_MODE_MASK
  39                       | RTC_GPS_CKOUT_EN);
  40         osc32con |= RTC_XOSC32_ENB | RTC_REG_XOSC32_ENB
  41                     | RTC_EMB_K_EOSC32_MODE | RTC_EMBCK_SEL_OPTION;
  42         if (!rtc_xosc_write(osc32con)) {
  43                 rtc_info("rtc_xosc_write() failed\n");
  44                 return false;
  45         }
  46
  47         rtc_read(RTC_CON, &con);
  48         rtc_read(RTC_OSC32CON, &osc32con);
  49         rtc_read(RTC_AL_SEC, &sec);
  50         rtc_info("con = %#x, osc32con = %#x, sec = %#x\n", con, osc32con, sec);
  51
  52         return true;
  53 }
  54
  55 /* Initialize RTC related gpio */
  56 bool rtc_gpio_init(void)
  57 {
  58         u16 con;
  59
  60         /* RTC_32K1V8 clock change from 128k div 4 source to RTC 32k source */
  61         pwrap_write_field(PMIC_RG_TOP_CKSEL_CON0_SET, 0x1, 0x1, 3);
  62
  63         /* Export 32K clock RTC_32K1V8_1 */
  64         pwrap_write_field(PMIC_RG_TOP_CKPDN_CON1_CLR, 0x1, 0x1, 1);
  65
  66         /* Export 32K clock RTC_32K2V8 */
  67         rtc_read(RTC_CON, &con);
  68         con &= (RTC_CON_LPSTA_RAW | RTC_CON_LPRST | RTC_CON_EOSC32_LPEN
  69                 | RTC_CON_XOSC32_LPEN);
  70         con |= (RTC_CON_GPEN | RTC_CON_GOE);
  71         con &= ~RTC_CON_F32KOB;
  72         rtc_write(RTC_CON, con);
  73
  74         return rtc_write_trigger();
  75 }
  76
  77 u16 rtc_get_frequency_meter(u16 val, u16 measure_src, u16 window_size)
  78 {
  79         u16 bbpu, osc32con;
  80         u16 fqmtr_busy, fqmtr_data, fqmtr_rst, fqmtr_tcksel;
  81         struct stopwatch sw;
  82
  83         rtc_read(RTC_BBPU, &bbpu);
  84         rtc_write(RTC_BBPU, bbpu | RTC_BBPU_KEY | RTC_BBPU_RELOAD);
  85         if (!rtc_write_trigger()) {
  86                 rtc_info("rtc_write_trigger() failed\n");
  87                 return false;
  88         }
  89
  90         rtc_read(RTC_OSC32CON, &osc32con);
  91         if (!rtc_xosc_write((osc32con & ~RTC_XOSCCALI_MASK) |
  92                             (val & RTC_XOSCCALI_MASK))) {
  93                 rtc_info("rtc_xosc_write() failed\n");
  94                 return false;
  95         }
  96
  97         /* Enable FQMTR clock */
  98         pwrap_write_field(PMIC_RG_TOP_CKPDN_CON0_CLR, 1, 1,
  99                           PMIC_RG_FQMTR_32K_CK_PDN_SHIFT);
 100         pwrap_write_field(PMIC_RG_TOP_CKPDN_CON0_CLR, 1, 1,
 101                           PMIC_RG_FQMTR_CK_PDN_SHIFT);
 102
 103         /* FQMTR reset */
 104         pwrap_write_field(PMIC_RG_FQMTR_RST, 1, 1, PMIC_FQMTR_RST_SHIFT);
 105         do {
 106                 rtc_read(PMIC_RG_FQMTR_DATA, &fqmtr_data);
 107                 rtc_read(PMIC_RG_FQMTR_CON0, &fqmtr_busy);
 108         } while (fqmtr_data && (fqmtr_busy & PMIC_FQMTR_CON0_BUSY));
 109         rtc_read(PMIC_RG_FQMTR_RST, &fqmtr_rst);
 110         /* FQMTR normal */
 111         pwrap_write_field(PMIC_RG_FQMTR_RST, 0, 1, PMIC_FQMTR_RST_SHIFT);
 112
 113         /* Set frequency meter window value (0=1X32K(fixed clock)) */
 114         rtc_write(PMIC_RG_FQMTR_WINSET, window_size);
 115         /* Enable 26M and set test clock source */
 116         rtc_write(PMIC_RG_FQMTR_CON0, PMIC_FQMTR_CON0_DCXO26M_EN | measure_src);
 117         /* Enable 26M -> delay 100us -> enable FQMTR */
 118         udelay(100);
 119         rtc_read(PMIC_RG_FQMTR_CON0, &fqmtr_tcksel);
 120         /* Enable FQMTR */
 121         rtc_write(PMIC_RG_FQMTR_CON0, fqmtr_tcksel | PMIC_FQMTR_CON0_FQMTR_EN);
 122         udelay(100);
 123
 124         stopwatch_init_usecs_expire(&sw, FQMTR_TIMEOUT_US);
 125         /* FQMTR read until ready */
 126         if (!wait_us(FQMTR_TIMEOUT_US,
 127                      rtc_read(PMIC_RG_FQMTR_CON0, &fqmtr_busy) == 0 &&
 128                      !(fqmtr_busy & PMIC_FQMTR_CON0_BUSY))) {
 129                 rtc_info("get frequency time out: %#x\n", fqmtr_busy);
 130                 return false;
 131         }
 132
 133         /* Read data should be closed to 26M/32k = 794 */
 134         rtc_read(PMIC_RG_FQMTR_DATA, &fqmtr_data);
 135
 136         rtc_read(PMIC_RG_FQMTR_CON0, &fqmtr_tcksel);
 137         /* Disable FQMTR */
 138         rtc_write(PMIC_RG_FQMTR_CON0, fqmtr_tcksel & ~PMIC_FQMTR_CON0_FQMTR_EN);
 139         /* Disable FQMTR -> delay 100us -> disable 26M */
 140         udelay(100);
 141         /* Disable 26M */
 142         rtc_read(PMIC_RG_FQMTR_CON0, &fqmtr_tcksel);
 143         rtc_write(PMIC_RG_FQMTR_CON0,
 144                   fqmtr_tcksel & ~PMIC_FQMTR_CON0_DCXO26M_EN);
 145         rtc_info("input = %#x, output = %#x\n", val, fqmtr_data);
 146
 147         /* Disable FQMTR clock */
 148         pwrap_write_field(PMIC_RG_TOP_CKPDN_CON0_SET, 1, 1,
 149                           PMIC_RG_FQMTR_32K_CK_PDN_SHIFT);
 150         pwrap_write_field(PMIC_RG_TOP_CKPDN_CON0_SET, 1, 1,
 151                           PMIC_RG_FQMTR_CK_PDN_SHIFT);
 152
 153         return fqmtr_data;
 154 }
 155
 156 /* Low power detect setting */
 157 static bool rtc_lpd_init(void)
 158 {
 159         u16 con, sec;
 160
 161         /* Set RTC_LPD_OPT */
 162         rtc_read(RTC_AL_SEC, &sec);
 163         sec |= RTC_LPD_OPT_F32K_CK_ALIVE;
 164         rtc_write(RTC_AL_SEC, sec);
 165         if (!rtc_write_trigger()) {
 166                 rtc_info("rtc_write_trigger() failed\n");
 167                 return false;
 168         }
 169
 170         /* Initialize XOSC32 to detect 32k clock stop */
 171         rtc_read(RTC_CON, &con);
 172         con |= RTC_CON_XOSC32_LPEN;
 173         if (!rtc_lpen(con))
 174                 return false;
 175
 176         /* Initialize EOSC32 to detect RTC low power */
 177         rtc_read(RTC_CON, &con);
 178         con |= RTC_CON_EOSC32_LPEN;
 179         if (!rtc_lpen(con))
 180                 return false;
 181
 182         rtc_read(RTC_CON, &con);
 183         con &= ~RTC_CON_XOSC32_LPEN;
 184         rtc_write(RTC_CON, con);
 185
 186         /* Set RTC_LPD_OPT */
 187         rtc_read(RTC_AL_SEC, &sec);
 188         sec &= ~RTC_LPD_OPT_MASK;
 189         sec |= RTC_LPD_OPT_EOSC_LPD;
 190         rtc_write(RTC_AL_SEC, sec);
 191         if (!rtc_write_trigger()) {
 192                 rtc_info("rtc_write_trigger() failed\n");
 193                 return false;
 194         }
 195
 196         return true;
 197 }
 198
 199 static bool rtc_hw_init(void)
 200 {
 201         u16 bbpu;
 202
 203         rtc_read(RTC_BBPU, &bbpu);
 204         rtc_write(RTC_BBPU, bbpu | RTC_BBPU_KEY | RTC_BBPU_INIT);
 205         if (!rtc_write_trigger()) {
 206                 rtc_info("rtc_write_trigger() failed\n");
 207                 return false;
 208         }
 209
 210         udelay(500);
 211
 212         rtc_read(RTC_BBPU, &bbpu);
 213         rtc_write(RTC_BBPU, bbpu | RTC_BBPU_KEY | RTC_BBPU_RELOAD);
 214         if (!rtc_write_trigger()) {
 215                 rtc_info("rtc_write_trigger() failed\n");
 216                 return false;
 217         }
 218
 219         rtc_read(RTC_BBPU, &bbpu);
 220         if (bbpu & RTC_BBPU_INIT) {
 221                 rtc_info("timeout\n");
 222                 return false;
 223         }
 224
 225         return true;
 226 }
 227
 228 static void mt6366_dcxo_disable_unused(void)
 229 {
 230         /* Disable clock buffer XO_CEL */
 231         rtc_write(PMIC_RG_DCXO_CW00_CLR, 0x0800);
 232         /* Mask bblpm request and switch off bblpm mode */
 233         rtc_write(PMIC_RG_DCXO_CW23, 0x0052);
 234 }
 235
 236 /* Check RTC Initialization */
 237 int rtc_init(int recover)
 238 {
 239         int ret;
 240
 241         rtc_info("recovery: %d\n", recover);
 242
 243         /* Write powerkeys to enable RTC functions */
 244         if (!rtc_powerkey_init()) {
 245                 ret = -RTC_STATUS_POWERKEY_INIT_FAIL;
 246                 goto err;
 247         }
 248
 249         /* Write interface unlock need to be set after powerkey match */
 250         if (!rtc_writeif_unlock()) {
 251                 ret = -RTC_STATUS_WRITEIF_UNLOCK_FAIL;
 252                 goto err;
 253         }
 254
 255         rtc_osc_init();
 256
 257         /* In recovery mode, we need 20ms delay for register setting. */
 258         if (recover)
 259                 mdelay(20);
 260
 261         if (!rtc_gpio_init()) {
 262                 ret = -RTC_STATUS_GPIO_INIT_FAIL;
 263                 goto err;
 264         }
 265
 266         if (!rtc_hw_init()) {
 267                 ret = -RTC_STATUS_HW_INIT_FAIL;
 268                 goto err;
 269         }
 270
 271         if (!rtc_reg_init()) {
 272                 ret = -RTC_STATUS_REG_INIT_FAIL;
 273                 goto err;
 274         }
 275
 276         if (!rtc_lpd_init()) {
 277                 ret = -RTC_STATUS_LPD_INIT_FAIL;
 278                 goto err;
 279         }
 280
 281         /*
 282          * After lpd init, powerkeys need to be written again to enable
 283          * low power detect function.
 284          */
 285         if (!rtc_powerkey_init()) {
 286                 ret = -RTC_STATUS_POWERKEY_INIT_FAIL;
 287                 goto err;
 288         }
 289
 290         return RTC_STATUS_OK;
 291 err:
 292         rtc_info("init failed: ret = %d\n", ret);
 293         return ret;
 294 }
 295
 296 /* Enable RTC bbpu */
 297 void rtc_bbpu_power_on(void)
 298 {
 299         u16 bbpu;
 300         int ret;
 301
 302         /* Pull powerhold high, control by pmic */
 303         mt6366_set_power_hold(true);
 304
 305         /* Pull PWRBB high */
 306         bbpu = RTC_BBPU_KEY | RTC_BBPU_AUTO | RTC_BBPU_RELOAD | RTC_BBPU_PWREN;
 307         rtc_write(RTC_BBPU, bbpu);
 308         ret = rtc_write_trigger();
 309         rtc_info("rtc_write_trigger = %d\n", ret);
 310
 311         rtc_read(RTC_BBPU, &bbpu);
 312         rtc_info("done BBPU = %#x\n", bbpu);
 313 }
 314
 315 static void dcxo_init(void)
 316 {
 317         /* Buffer setting */
 318         rtc_write(PMIC_RG_DCXO_CW15, 0xA2AA);
 319         rtc_write(PMIC_RG_DCXO_CW13, 0x98E9);
 320         rtc_write(PMIC_RG_DCXO_CW16, 0x9855);
 321
 322         /* 26M enable control */
 323         /* Enable clock buffer XO_SOC, XO_CEL */
 324         rtc_write(PMIC_RG_DCXO_CW00, 0x4805);
 325         rtc_write(PMIC_RG_DCXO_CW11, 0x8000);
 326
 327         /* Load thermal coefficient */
 328         rtc_write(PMIC_RG_TOP_TMA_KEY, 0x9CA7);
 329         rtc_write(PMIC_RG_DCXO_CW21, 0x12A7);
 330         rtc_write(PMIC_RG_DCXO_ELR0, 0xD004);
 331         rtc_write(PMIC_RG_TOP_TMA_KEY, 0x0000);
 332
 333         /* Adjust OSC FPM setting */
 334         rtc_write(PMIC_RG_DCXO_CW07, 0x8FFE);
 335
 336         /* Re-calibrate OSC current */
 337         rtc_write(PMIC_RG_DCXO_CW09, 0x008F);
 338         udelay(100);
 339         rtc_write(PMIC_RG_DCXO_CW09, 0x408F);
 340         mdelay(5);
 341
 342         mt6366_dcxo_disable_unused();
 343 }
 344
 345 /* Initialize rtc boot flow */
 346 void rtc_boot(void)
 347 {
 348         /* DCXO clock initialized settings */
 349         dcxo_init();
 350
 351         /* DCXO 32k initialized settings */
 352         pwrap_write_field(PMIC_RG_DCXO_CW02, 0xF, 0xF, 0);
 353         pwrap_write_field(PMIC_RG_SCK_TOP_CON0, 0x1, 0x1, 0);
 354
 355         /* Use DCXO 32K clock */
 356         if (!rtc_enable_dcxo())
 357                 rtc_info("rtc_enable_dcxo() failed\n");
 358
 359         rtc_boot_common();
 360         rtc_bbpu_power_on();
 361 }