soc/intel/common/block: fix storage size of HEST log address
[coreboot.git] / src / arch / x86 / postcar.c
blob1df8c44366c1182d879ffd24825994ad78718b47
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 #include <arch/romstage.h>
4 #include <cbmem.h>
5 #include <console/console.h>
6 #include <cpu/x86/mtrr.h>
7 #include <main_decl.h>
8 #include <program_loading.h>
9 #include <timestamp.h>
12 * Systems without a native coreboot cache-as-ram teardown may implement
13 * this to use an alternate method.
15 __weak void late_car_teardown(void) { /* do nothing */ }
17 void main(void)
19 late_car_teardown();
21 console_init();
24 * CBMEM needs to be recovered because timestamps rely on
25 * the cbmem infrastructure being around. Explicitly recover it.
27 * On some platforms CBMEM needs to be initialized earlier.
28 * Use cbmem_online() to avoid init CBMEM twice.
30 if (!cbmem_online())
31 cbmem_initialize();
33 timestamp_add_now(TS_START_POSTCAR);
35 display_mtrrs();
37 /* Load and run ramstage. */
38 run_ramstage();