src/soc/intel/alderlake/Makefile.inc

   1 ifeq ($(CONFIG_SOC_INTEL_ALDERLAKE),y)
   2 subdirs-y += romstage
   3 subdirs-y += ../../../cpu/intel/microcode
   4 subdirs-y += ../../../cpu/intel/turbo
   5
   6 # all (bootblock, verstage, romstage, postcar, ramstage)
   7 all-y += gspi.c
   8 all-y += i2c.c
   9 all-y += pmutil.c
  10 all-y += spi.c
  11 all-y += uart.c
  12
  13 bootblock-y += bootblock/bootblock.c
  14 bootblock-y += bootblock/pch.c
  15 bootblock-y += bootblock/report_platform.c
  16 bootblock-y += espi.c
  17 bootblock-y += p2sb.c
  18 bootblock-$(CONFIG_ALDERLAKE_CONFIGURE_DESCRIPTOR) += bootblock/update_descriptor.c
  19
  20 romstage-y += espi.c
  21 romstage-y += meminit.c
  22 romstage-y += pcie_rp.c
  23 romstage-y += reset.c
  24 romstage-y += cpu.c
  25
  26 ramstage-y += acpi.c
  27 ramstage-y += chip.c
  28 ramstage-y += cpu.c
  29 ramstage-y += dptf.c
  30 ramstage-y += elog.c
  31 ramstage-y += espi.c
  32 ramstage-y += finalize.c
  33 ramstage-y += fsp_params.c
  34 ramstage-y += lockdown.c
  35 ramstage-y += me.c
  36 ramstage-y += p2sb.c
  37 ramstage-y += pcie_rp.c
  38 ramstage-y += pmc.c
  39 ramstage-y += reset.c
  40 ramstage-$(CONFIG_SOC_INTEL_ALDERLAKE_TCSS_USB4_SUPPORT) += retimer.c
  41 ramstage-y += soundwire.c
  42 ramstage-y += systemagent.c
  43 ramstage-y += tcss.c
  44 ramstage-y += vr_config.c
  45 ramstage-y += xhci.c
  46 ramstage-$(CONFIG_SOC_INTEL_CRASHLOG) += crashlog.c
  47
  48 smm-y += elog.c
  49 smm-y += p2sb.c
  50 smm-y += pmutil.c
  51 smm-y += smihandler.c
  52 smm-y += uart.c
  53 smm-y += xhci.c
  54
  55 ifeq ($(CONFIG_SOC_INTEL_ALDERLAKE_PCH_S),y)
  56 bootblock-y += gpio_pch_s.c
  57 romstage-y += gpio_pch_s.c
  58 ramstage-y += gpio_pch_s.c
  59 smm-y += gpio_pch_s.c
  60 verstage-y += gpio_pch_s.c
  61 else
  62 bootblock-y += gpio.c
  63 romstage-y += gpio.c
  64 ramstage-y += gpio.c
  65 smm-y += gpio.c
  66 verstage-y += gpio.c
  67 endif
  68
  69 CPPFLAGS_common += -I$(src)/soc/intel/alderlake
  70 CPPFLAGS_common += -I$(src)/soc/intel/alderlake/include
  71
  72 ifeq ($(CONFIG_STITCH_ME_BIN),y)
  73
  74 $(eval $(call cse_add_dummy_to_bp1_bp2,DLMP))
  75 $(eval $(call cse_add_dummy_to_bp1_bp2,IFPP))
  76 $(eval $(call cse_add_dummy_to_bp1_bp2,SBDT))
  77 $(eval $(call cse_add_decomp_to_bp1_bp2,RBEP))
  78 $(eval $(call cse_add_dummy_to_bp1_bp2,UFSP))
  79 $(eval $(call cse_add_dummy_to_bp1_bp2,UFSG))
  80 $(eval $(call cse_add_input_to_bp1_bp2,OEMP))
  81 $(eval $(call cse_add_input_to_bp1_bp2,PMCP))
  82 $(eval $(call cse_add_decomp,bp1,MFTP))
  83 $(eval $(call cse_add_decomp,bp2,FTPR))
  84 $(eval $(call cse_add_input_to_bp1_bp2,IOMP))
  85 $(eval $(call cse_add_input_to_bp1_bp2,NPHY))
  86 $(eval $(call cse_add_input_to_bp1_bp2,TBTP))
  87 $(eval $(call cse_add_input_to_bp1_bp2,PCHC))
  88 $(eval $(call cse_add_decomp,bp2,NFTP))
  89 $(eval $(call cse_add_dummy,bp2,ISHP))
  90 $(eval $(call cse_add_input,bp2,IUNP))
  91
  92 endif
  93
  94 endif