src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 #include <baseboard/variants.h>
   4 #include <delay.h>
   5 #include <gpio.h>
   6 #include <soc/gpio.h>
   7 #include <soc/smi.h>
   8 #include <stdlib.h>
   9 #include <boardid.h>
  10 #include <variant/gpio.h>
  11
  12 static const struct soc_amd_gpio gpio_set_stage_ram[] = {
  13         /* PWR_BTN_L */
  14         PAD_NF(GPIO_0, PWR_BTN_L, PULL_NONE),
  15         /* SYS_RESET_L */
  16         PAD_NF(GPIO_1, SYS_RESET_L, PULL_NONE),
  17         /* PCIE_WAKE_L */
  18         PAD_NF(GPIO_2, WAKE_L, PULL_NONE),
  19         /* H1_FCH_INT_ODL */
  20         PAD_INT(GPIO_3, PULL_NONE, EDGE_LOW, STATUS_DELIVERY),
  21         /* PEN_DETECT_ODL */
  22         PAD_WAKE(GPIO_4, PULL_NONE, EDGE_HIGH, S3),
  23         /* PEN_POWER_EN - Enabled*/
  24         PAD_GPO(GPIO_5, HIGH),
  25         /* EN_PWR_TOUCHPAD */
  26         PAD_GPO(GPIO_6, HIGH),
  27         /* I2S_SDIN */
  28         PAD_NF(GPIO_7, ACP_I2S_SDIN, PULL_NONE),
  29         /* I2S_LRCLK - Bit banged in depthcharge */
  30         PAD_NF(GPIO_8, ACP_I2S_LRCLK, PULL_NONE),
  31         /* TOUCHPAD_INT_ODL */
  32         PAD_SCI(GPIO_9, PULL_NONE, EDGE_LOW),
  33         /* S0iX SLP - (unused - goes to EC & FPMCU */
  34         PAD_NC(GPIO_10),
  35         /* EC_IN_RW_OD */
  36         PAD_GPI(GPIO_11, PULL_NONE),
  37         /* USI_INT_ODL */
  38         PAD_GPI(GPIO_12, PULL_NONE),
  39         /* GPIO_13 - GPIO_15: Not available */
  40         /* USB_OC0_L - USB C0/A0 */
  41         PAD_NF(GPIO_16, USB_OC0_L, PULL_NONE),
  42         /* USB_OC1_L - USB C1 */
  43         PAD_NF(GPIO_17, USB_OC1_L, PULL_NONE),
  44         /* WIFI_DISABLE */
  45         PAD_GPO(GPIO_18, LOW),
  46         /* I2C3_SCL - H1 */
  47         PAD_NF(GPIO_19, I2C3_SCL, PULL_NONE),
  48         /* I2C3_SDA - H1 */
  49         PAD_NF(GPIO_20, I2C3_SDA, PULL_NONE),
  50         /* EMMC_CMD */
  51         PAD_NF(GPIO_21, EMMC_CMD, PULL_NONE),
  52         /* EC_FCH_SCI_ODL */
  53         PAD_SCI(GPIO_22, PULL_NONE, EDGE_LOW),
  54         /* AC_PRES */
  55         PAD_NF(GPIO_23, AC_PRES, PULL_UP),
  56         /* EC_FCH_WAKE_L */
  57         PAD_SCI(GPIO_24, PULL_NONE, EDGE_LOW),
  58         /* GPIO_25: Not available */
  59         /* PCIE_RST0_L - Fixed timings */
  60         PAD_NF(GPIO_26, PCIE_RST_L, PULL_NONE),
  61         /* GPIO_27: Configured in bootblock. */
  62         /* GPIO_28: Not available */
  63         /* GPIO_29: Handled in bootblock for wifi power/reset control. */
  64         /* FCH_ESPI_EC_CS_L */
  65         PAD_NF(GPIO_30, ESPI_CS_L, PULL_NONE),
  66         /* EC_AP_INT_ODL (Sensor Framesync) */
  67         PAD_GPI(GPIO_31, PULL_NONE),
  68         /* TP */
  69         PAD_NC(GPIO_32),
  70         /* GPIO_33 - GPIO_39: Not available */
  71         /* NVME_AUX_RESET_L */
  72         PAD_GPO(GPIO_40, HIGH),
  73         /* GPIO_41: Not available */
  74         /* GPIO_42: Handled in bootblock for wifi power/reset control. */
  75         /* GPIO_43 - GPIO_66: Not available */
  76         /* DMIC_SEL */
  77         /*
  78          * Make sure Ext ROM Sharing is disabled before using this GPIO.  Otherwise SPI flash
  79          * access will be very slow.
  80          */
  81         PAD_GPO(GPIO_67, LOW),  // Select Camera 1 Dmic
  82         /* EMMC_RESET */
  83         PAD_GPO(GPIO_68, LOW),
  84         /* RAM ID 3 */
  85         PAD_GPI(GPIO_69, PULL_NONE),
  86         /* EMMC_CLK */
  87         PAD_NF(GPIO_70, EMMC_CLK, PULL_NONE),
  88         /* GPIO_71 - GPIO_73: Not available */
  89         /* EMMC_DATA4 */
  90         PAD_NF(GPIO_74, EMMC_DATA4, PULL_NONE),
  91         /* EMMC_DATA6 */
  92         PAD_NF(GPIO_75, EMMC_DATA6, PULL_NONE),
  93         /* EN_PWR_CAMERA */
  94         PAD_GPO(GPIO_76, HIGH),
  95         /* GPIO_77 - GPIO_83: Not available */
  96         /* UNUSED */
  97         PAD_NC(GPIO_84),
  98         /* APU_EDP_BL_DISABLE TODP: Set low in depthcharge */
  99         PAD_GPO(GPIO_85, HIGH),
 100         /* RAM ID 2 */
 101         PAD_GPI(GPIO_86, PULL_NONE),
 102         /* EMMC_DATA7 */
 103         PAD_NF(GPIO_87, EMMC_DATA7, PULL_NONE),
 104         /* EMMC_DATA5 */
 105         PAD_NF(GPIO_88, EMMC_DATA5, PULL_NONE),
 106         /*  EN_DEV_BEEP_L */
 107         PAD_GPO(GPIO_89, HIGH),
 108         /* RAM ID 1 */
 109         PAD_GPI(GPIO_90, PULL_NONE),
 110         /* EN_SPKR TODO: Verify driver enables this (add to ACPI) */
 111         PAD_GPO(GPIO_91, LOW),
 112         /* CLK_REQ0_L - WIFI */
 113         PAD_NF(GPIO_92, CLK_REQ0_L, PULL_NONE),
 114         /* GPIO_93 - GPIO_103: Not available */
 115         /* EMMC_DATA0 */
 116         PAD_NF(GPIO_104, EMMC_DATA0, PULL_NONE),
 117         /* EMMC_DATA1 */
 118         PAD_NF(GPIO_105, EMMC_DATA1, PULL_NONE),
 119         /* EMMC_DATA2 */
 120         PAD_NF(GPIO_106, EMMC_DATA2, PULL_NONE),
 121         /* EMMC_DATA3 */
 122         PAD_NF(GPIO_107, EMMC_DATA3, PULL_NONE),
 123         /* ESPI_ALERT_L */
 124         PAD_NF(GPIO_108, ESPI_ALERT_L, PULL_UP),
 125         /* EMMC_DS */
 126         PAD_NF(GPIO_109, EMMC_DS, PULL_NONE),
 127         /* GPIO_110 - GPIO112: Not available */
 128         /* I2C2_SCL - USI/Touchpad */
 129         PAD_NF(GPIO_113, I2C2_SCL, PULL_NONE),
 130         /* I2C2_SDA - USI/Touchpad */
 131         PAD_NF(GPIO_114, I2C2_SDA, PULL_NONE),
 132         /* CLK_REQ1_L - SD Card */
 133         PAD_NF(GPIO_115, CLK_REQ1_L, PULL_NONE),
 134         /* CLK_REQ2_L - NVMe */
 135         PAD_NF(GPIO_116, CLK_REQ2_L, PULL_NONE),
 136         /* GPIO_117 - GPIO_128: Not available */
 137         /* KBRST_L */
 138         PAD_NF(GPIO_129, KBRST_L, PULL_NONE),
 139         /* GPIO_130 - GPIO_131: Not available */
 140         /* RAM ID 0 */
 141         PAD_GPI(GPIO_132, PULL_NONE),
 142         /* GPIO_133 - GPIO_134: Not available */
 143         /* DEV_BEEP_CODEC_IN (Dev beep Data out) */
 144         PAD_GPI(GPIO_135, PULL_NONE),
 145         /* UART0_RXD - DEBUG */
 146         PAD_NF(GPIO_136, UART0_RXD, PULL_NONE),
 147         /* BIOS_FLASH_WP_ODL */
 148         PAD_GPI(GPIO_137, PULL_NONE),
 149         /* UART0_TXD - DEBUG */
 150         PAD_NF(GPIO_138, UART0_TXD, PULL_NONE),
 151         /* DEV_BEEP_BCLK */
 152         PAD_GPI(GPIO_139, PULL_NONE),
 153         /* USI_RESET */
 154         PAD_GPO(GPIO_140, HIGH),
 155         /* USB_HUB_RST_L */
 156         PAD_GPO(GPIO_141, HIGH),
 157         /* SD_AUX_RESET_L */
 158         PAD_GPO(GPIO_142, HIGH),
 159         /* BT_DISABLE */
 160         PAD_GPO(GPIO_143, LOW),
 161         /*
 162          * USI_REPORT_EN - TODO: Driver resets this later.
 163          * Do we want it high or low initially?
 164          */
 165         PAD_GPO(GPIO_144, HIGH),
 166 };
 167
 168 const __weak
 169 struct soc_amd_gpio *variant_base_gpio_table(size_t *size)
 170 {
 171         *size = ARRAY_SIZE(gpio_set_stage_ram);
 172         return gpio_set_stage_ram;
 173 }
 174
 175 /*
 176  * This function is still needed for boards that sets gevents above 23
 177  * that will generate SCI or SMI. Normally this function
 178  * points to a table of gevents and what needs to be set. The code that
 179  * calls it was modified so that when this function returns NULL then the
 180  * caller does nothing.
 181  */
 182 const __weak struct sci_source *variant_gpe_table(size_t *num)
 183 {
 184         return NULL;
 185 }
 186
 187 static void wifi_power_reset_configure_active_low_power(void)
 188 {
 189         /*
 190          * Configure WiFi GPIOs such that:
 191          * - WIFI_AUX_RESET is configured first to assert PERST# to WiFi device.
 192          * - Enable power to WiFi using EN_PWR_WIFI_L.
 193          * - Wait for 50ms after power to WiFi is enabled.
 194          * - Deassert WIFI_AUX_RESET.
 195          */
 196         static const struct soc_amd_gpio v3_wifi_table[] = {
 197                 /* WIFI_AUX_RESET */
 198                 PAD_GPO(GPIO_29, HIGH),
 199                 /* EN_PWR_WIFI_L */
 200                 PAD_GPO(GPIO_42, LOW),
 201         };
 202         program_gpios(v3_wifi_table, ARRAY_SIZE(v3_wifi_table));
 203
 204         mdelay(50);
 205         gpio_set(GPIO_29, 0);
 206 }
 207
 208 static void wifi_power_reset_configure_active_high_power(void)
 209 {
 210         /*
 211          * When GPIO_42 is configured as active high for enabling WiFi power, WIFI_AUX_RESET
 212          * gets pulled high because of external PU to PP3300_WIFI. Thus, EN_PWR_WIFI needs to be
 213          * set low before driving it high to trigger a WiFi power cycle to meet PCIe
 214          * requirements. Thus, configure GPIOs such that:
 215          * - WIFI_AUX_RESET is configured first to assert PERST# to WiFi device
 216          * - Disable power to WiFi.
 217          * - Wait 10ms for WiFi power to go low.
 218          * - Enable power to WiFi using EN_PWR_WIFI.
 219          * - Deassert WIFI_AUX_RESET.
 220          */
 221         static const struct soc_amd_gpio v3_wifi_table[] = {
 222                 /* WIFI_AUX_RESET */
 223                 PAD_GPO(GPIO_29, HIGH),
 224                 /* EN_PWR_WIFI */
 225                 PAD_GPO(GPIO_42, LOW),
 226         };
 227         program_gpios(v3_wifi_table, ARRAY_SIZE(v3_wifi_table));
 228
 229         mdelay(10);
 230         gpio_set(GPIO_42, 1);
 231         mdelay(50);
 232         gpio_set(GPIO_29, 0);
 233 }
 234
 235 static void wifi_power_reset_configure_v3(void)
 236 {
 237         if (variant_has_active_low_wifi_power())
 238                 wifi_power_reset_configure_active_low_power();
 239         else
 240                 wifi_power_reset_configure_active_high_power();
 241 }
 242
 243 static void wifi_power_reset_configure_pre_v3(void)
 244 {
 245         /*
 246          * Configure WiFi GPIOs such that:
 247          * - WIFI_AUX_RESET_L is configured first to assert PERST# to WiFi device.
 248          * - Disable power to WiFi since GPIO_29 goes high on PWRGOOD but has a glitch on RESET#
 249          *   deassertion causing WiFi to enter a bad state.
 250          * - Wait 10ms for WiFi power to go low.
 251          * - Enable power to WiFi using EN_PWR_WIFI.
 252          * - Wait for 50ms after power to WiFi is enabled.
 253          * - Deassert WIFI_AUX_RESET_L.
 254          */
 255         static const struct soc_amd_gpio pre_v3_wifi_table[] = {
 256                 /* WIFI_AUX_RESET_L */
 257                 PAD_GPO(GPIO_42, LOW),
 258                 /* EN_PWR_WIFI */
 259                 PAD_GPO(GPIO_29, LOW),
 260         };
 261         program_gpios(pre_v3_wifi_table, ARRAY_SIZE(pre_v3_wifi_table));
 262
 263         mdelay(10);
 264         gpio_set(GPIO_29, 1);
 265         mdelay(50);
 266         gpio_set(GPIO_42, 1);
 267 }
 268
 269 __weak void variant_pcie_gpio_configure(void)
 270 {
 271         static const struct soc_amd_gpio pcie_gpio_table[] = {
 272                 /* PCIE_RST1_L - Variable timings (May remove) */
 273                 PAD_NF(GPIO_27, PCIE_RST1_L, PULL_NONE),
 274                 /* NVME_AUX_RESET_L */
 275                 PAD_GPO(GPIO_40, HIGH),
 276                 /* CLK_REQ0_L - WIFI */
 277                 PAD_NF(GPIO_92, CLK_REQ0_L, PULL_NONE),
 278                 /* CLK_REQ1_L - SD Card */
 279                 PAD_NF(GPIO_115, CLK_REQ1_L, PULL_NONE),
 280                 /* CLK_REQ2_L - NVMe */
 281                 PAD_NF(GPIO_116, CLK_REQ2_L, PULL_NONE),
 282                 /* SD_AUX_RESET_L */
 283                 PAD_GPO(GPIO_142, HIGH),
 284         };
 285
 286         program_gpios(pcie_gpio_table, ARRAY_SIZE(pcie_gpio_table));
 287
 288         /* Deassert PCIE_RST1_L */
 289         gpio_set(GPIO_27, 1);
 290
 291         if (variant_uses_v3_schematics())
 292                 wifi_power_reset_configure_v3();
 293         else
 294                 wifi_power_reset_configure_pre_v3();
 295 }
 296
 297 static const struct soc_amd_gpio gpio_sleep_table[] = {
 298         /* PCIE_RST1_L */
 299         PAD_GPO(GPIO_27, LOW),
 300         /*
 301          * On pre-v3 schematics, GPIO_29 is EN_PWR_WIFI. So, setting to high should be no-op.
 302          * On v3+ schematics, GPIO_29 is WIFI_AUX_RESET. Setting to high ensures that PERST# is
 303          * asserted to WiFi device until coreboot reconfigures GPIO_29 on resume path.
 304          */
 305         PAD_GPO(GPIO_29, HIGH),
 306         /* NVME_AUX_RESET_L */
 307         PAD_GPO(GPIO_40, LOW),
 308         /* EN_PWR_CAMERA */
 309         PAD_GPO(GPIO_76, LOW),
 310 };
 311
 312 const __weak struct soc_amd_gpio *variant_sleep_gpio_table(size_t *size, int slp_typ)
 313 {
 314         *size = ARRAY_SIZE(gpio_sleep_table);
 315         return gpio_sleep_table;
 316 }