intel/skylake: Implement native Cache-as-RAM (CAR)
[coreboot.git] / src / include / trace.h
blob362a361f102ed98228c28c663248bb6d235b928b
1 /*
2 * This file is part of the coreboot project.
4 * Copyright (C) 2011 Rudolf Marek <r.marek@assembler.cz>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
16 #ifndef __TRACE_H
17 #define __TRACE_H
20 #ifdef __PRE_RAM__
22 #define DISABLE_TRACE
23 #define ENABLE_TRACE
24 #define DISABLE_TRACE_ON_FUNCTION
26 #else /* !__PRE_RAM__ */
28 #if CONFIG_TRACE && !defined(__SMM__)
30 void __cyg_profile_func_enter( void *, void * )
31 __attribute__ ((no_instrument_function));
33 void __cyg_profile_func_exit( void *, void * )
34 __attribute__ ((no_instrument_function));
36 extern volatile int trace_dis;
38 #define DISABLE_TRACE do { trace_dis = 1; } while (0);
39 #define ENABLE_TRACE do { trace_dis = 0; } while (0);
40 #define DISABLE_TRACE_ON_FUNCTION __attribute__ ((no_instrument_function));
42 #else /* !CONFIG_TRACE */
44 #define DISABLE_TRACE
45 #define ENABLE_TRACE
46 #define DISABLE_TRACE_ON_FUNCTION
48 #endif
49 #endif
50 #endif