2 ## This file is part of the coreboot project.
4 ## Copyright (C) 2012 Alexandru Gagniuc <mr.nuke.me@gmail.com>
5 ## Copyright (C) 2009-2010 coresystems GmbH
7 ## This program is free software; you can redistribute it and/or modify
8 ## it under the terms of the GNU General Public License as published by
9 ## the Free Software Foundation; version 2 of the License.
11 ## This program is distributed in the hope that it will be useful,
12 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ## GNU General Public License for more details.
17 mainmenu "coreboot configuration"
22 string "Local version string"
24 Append an extra string to the end of the coreboot version.
26 This can be useful if, for instance, you want to append the
27 respective board's hostname or some other identifying string to
28 the coreboot version number, so that you can easily distinguish
29 boot logs of different boards from each other.
32 string "CBFS prefix to use"
35 Select the prefix to all files put into the image. It's "fallback"
36 by default, "normal" is a common alternative.
38 config COMMON_CBFS_SPI_WRAPPER
44 Use common wrapper to interface CBFS to SPI bootrom.
46 config MULTIPLE_CBFS_INSTANCES
47 bool "Multiple CBFS instances in the bootrom"
50 Account for the firmware image containing more than one CBFS
51 instance. Locations of instances are known at build time and are
52 communicated between coreboot stages to make sure the next stage is
53 loaded from the appropriate instance.
56 prompt "Compiler to use"
59 This option allows you to select the compiler used for building
61 You must build the coreboot crosscompiler for the board that you
64 To build all the GCC crosscompilers (takes a LONG time), run:
67 For help on individual architectures, run the command:
73 Use the GNU Compiler Collection (GCC) to build coreboot.
75 For details see http://gcc.gnu.org.
77 config COMPILER_LLVM_CLANG
78 bool "LLVM/clang (TESTING ONLY - Not currently working)"
80 Use LLVM/clang to build coreboot. To use this, you must build the
81 coreboot version of the clang compiler. Run the command
83 Note that this option is not currently working correctly and should
84 really only be selected if you're trying to work on getting clang
87 For details see http://clang.llvm.org.
92 bool "Allow building with any toolchain"
94 depends on COMPILER_GCC
96 Many toolchains break when building coreboot since it uses quite
97 unusual linker features. Unless developers explicitely request it,
98 we'll have to assume that they use their distro compiler by mistake.
99 Make sure that using patched compilers is a conscious decision.
102 bool "Use ccache to speed up (re)compilation"
105 Enables the use of ccache for faster builds.
107 Requires the ccache utility in your system $PATH.
109 For details see https://ccache.samba.org.
112 bool "Generate flashmap descriptor parser using flex and bison"
115 Enable this option if you are working on the flashmap descriptor
116 parser and made changes to fmd_scanner.l or fmd_parser.y.
118 Otherwise, say N to use the provided pregenerated scanner/parser.
120 config SCONFIG_GENPARSER
121 bool "Generate SCONFIG parser using flex and bison"
124 Enable this option if you are working on the sconfig device tree
125 parser and made changes to sconfig.l or sconfig.y.
127 Otherwise, say N to use the provided pregenerated scanner/parser.
129 config USE_OPTION_TABLE
130 bool "Use CMOS for configuration values"
132 depends on HAVE_OPTION_TABLE
134 Enable this option if coreboot shall read options from the "CMOS"
135 NVRAM instead of using hard-coded values.
137 config STATIC_OPTION_TABLE
138 bool "Load default configuration values into CMOS on each boot"
140 depends on USE_OPTION_TABLE
142 Enable this option to reset "CMOS" NVRAM values to default on
143 every boot. Use this if you want the NVRAM configuration to
144 never be modified from its default values.
146 config UNCOMPRESSED_RAMSTAGE
150 config COMPRESS_RAMSTAGE
151 bool "Compress ramstage with LZMA"
152 default y if !UNCOMPRESSED_RAMSTAGE
155 Compress ramstage to save memory in the flash image. Note
156 that decompression might slow down booting if the boot flash
157 is connected through a slow link (i.e. SPI).
159 config INCLUDE_CONFIG_FILE
160 bool "Include the coreboot .config file into the ROM image"
163 Include the .config file that was used to compile coreboot
164 in the (CBFS) ROM image. This is useful if you want to know which
165 options were used to build a specific coreboot.rom image.
167 Saying Y here will increase the image size by 2-3KB.
169 You can use the following command to easily list the options:
171 grep -a CONFIG_ coreboot.rom
173 Alternatively, you can also use cbfstool to print the image
174 contents (including the raw 'config' item we're looking for).
178 $ cbfstool coreboot.rom print
179 coreboot.rom: 4096 kB, bootblocksize 1008, romsize 4194304,
183 Name Offset Type Size
184 cmos_layout.bin 0x0 cmos layout 1159
185 fallback/romstage 0x4c0 stage 339756
186 fallback/ramstage 0x53440 stage 186664
187 fallback/payload 0x80dc0 payload 51526
188 config 0x8d740 raw 3324
189 (empty) 0x8e480 null 3610440
191 config EARLY_CBMEM_INIT
192 def_bool !LATE_CBMEM_INIT
194 config COLLECT_TIMESTAMPS
195 bool "Create a table of timestamps collected during boot"
198 Make coreboot create a table of timer-ID/timer-value pairs to
199 allow measuring time spent at different phases of the boot process.
201 config HAS_PRECBMEM_TIMESTAMP_REGION
202 bool "Timestamp region exists for pre-cbmem timestamps"
203 default y if ARCH_ROMSTAGE_X86_32 && CACHE_AS_RAM
205 A separate region is maintained to allow storing of timestamps before
206 cbmem comes up. This is useful for storing timestamps across different
210 bool "Allow use of binary-only repository"
213 This draws in the blobs repository, which contains binary files that
214 might be required for some chipsets or boards.
215 This flag ensures that a "Free" option remains available for users.
218 bool "Code coverage support"
219 depends on COMPILER_GCC
222 Add code coverage support for coreboot. This will store code
223 coverage information in CBMEM for extraction from user space.
226 config RELOCATABLE_MODULES
230 If RELOCATABLE_MODULES is selected then support is enabled for
231 building relocatable modules in the RAM stage. Those modules can be
232 loaded anywhere and all the relocations are handled automatically.
234 config RELOCATABLE_RAMSTAGE
235 depends on EARLY_CBMEM_INIT
236 bool "Build the ramstage to be relocatable in 32-bit address space."
238 select RELOCATABLE_MODULES
240 The reloctable ramstage support allows for the ramstage to be built
241 as a relocatable module. The stage loader can identify a place
242 out of the OS way so that copying memory is unnecessary during an S3
243 wake. When selecting this option the romstage is responsible for
244 determing a stack location to use for loading the ramstage.
246 config CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM
247 depends on RELOCATABLE_RAMSTAGE
248 bool "Cache the relocated ramstage outside of cbmem."
251 The relocated ramstage is saved in an area specified by the
252 by the board and/or chipset.
254 config FLASHMAP_OFFSET
255 hex "Flash Map Offset"
256 default 0x00670000 if NORTHBRIDGE_INTEL_SANDYBRIDGE_MRC
257 default 0x00610000 if NORTHBRIDGE_INTEL_IVYBRIDGE_MRC
258 default CBFS_SIZE if !ARCH_X86
261 Offset of flash map in firmware image
263 # TODO: This doesn't belong here, move to src/arch/x86/Kconfig
265 prompt "Bootblock behaviour"
266 default BOOTBLOCK_SIMPLE
268 config BOOTBLOCK_SIMPLE
269 bool "Always load fallback"
271 config BOOTBLOCK_NORMAL
272 bool "Switch to normal if CMOS says so"
276 # To be selected by arch, SoC or mainboard if it does not want use the normal
277 # src/lib/bootblock.c#main() C entry point.
278 config BOOTBLOCK_CUSTOM
282 config BOOTBLOCK_SOURCE
284 default "bootblock_simple.c" if BOOTBLOCK_SIMPLE
285 default "bootblock_normal.c" if BOOTBLOCK_NORMAL
287 # To be selected by arch or platform if a C environment is available during the
288 # bootblock. Normally this signifies availability of RW memory (e.g. SRAM).
289 config C_ENVIRONMENT_BOOTBLOCK
293 config SKIP_MAX_REBOOT_CNT_CLEAR
294 bool "Do not clear reboot count after successful boot"
296 depends on BOOTBLOCK_NORMAL
298 Do not clear the reboot count immediately after successful boot.
299 Set to allow the payload to control normal/fallback image recovery.
300 Note that it is the responsibility of the payload to reset the
301 normal boot bit to 1 after each successsful boot.
304 bool "Update existing coreboot.rom image"
307 If this option is enabled, no new coreboot.rom file
308 is created. Instead it is expected that there already
309 is a suitable file for further processing.
310 The bootblock will not be modified.
312 If unsure, select 'N'
314 config GENERIC_GPIO_LIB
318 If enabled, compile the generic GPIO library. A "generic" GPIO
319 implies configurability usually found on SoCs, particularly the
320 ability to control internal pull resistors.
326 Mainboards that can read a board ID from the hardware straps
327 (ie. GPIO) select this configuration option.
329 config BOARD_ID_MANUAL
332 depends on !BOARD_ID_AUTO
334 If you want to maintain a board ID, but the hardware does not
335 have straps to automatically determine the ID, you can say Y
336 here and add a file named 'board_id' to CBFS. If you don't know
337 what this is about, say N.
339 config BOARD_ID_STRING
342 depends on BOARD_ID_MANUAL
344 This string is placed in the 'board_id' CBFS file for indicating
347 config RAM_CODE_SUPPORT
351 If enabled, coreboot discovers RAM configuration (value obtained by
352 reading board straps) and stores it in coreboot table.
354 config BOOTSPLASH_IMAGE
355 bool "Add a bootsplash image"
357 Select this option if you have a bootsplash image that you would
358 like to add to your ROM.
360 This will only add the image to the ROM. To actually run it check
361 options under 'Display' section.
363 config BOOTSPLASH_FILE
364 string "Bootsplash path and filename"
365 depends on BOOTSPLASH_IMAGE
366 default "bootsplash.jpg"
368 The path and filename of the file to use as graphical bootsplash
369 screen. The file format has to be jpg.
373 source "src/acpi/Kconfig"
377 source "src/mainboard/Kconfig"
380 hex "Size of CBFS filesystem in ROM"
381 default 0x100000 if HAVE_INTEL_FIRMWARE || \
382 NORTHBRIDGE_INTEL_X4X || \
383 NORTHBRIDGE_INTEL_GM45 || NORTHBRIDGE_INTEL_SANDYBRIDGE_MRC || \
384 NORTHBRIDGE_INTEL_IVYBRIDGE_MRC || NORTHBRIDGE_INTEL_IVYBRIDGE || \
385 NORTHBRIDGE_INTEL_SANDYBRIDGE || \
386 NORTHBRIDGE_INTEL_NEHALEM || SOC_INTEL_BRASWELL || \
388 default 0x200000 if SOC_INTEL_SKYLAKE
391 This is the part of the ROM actually managed by CBFS, located at the
392 end of the ROM (passed through cbfstool -o) on x86 and at at the start
393 of the ROM (passed through cbfstool -s) everywhere else. It defaults
394 to span the whole ROM on all but Intel systems that use an Intel Firmware
395 Descriptor. It can be overridden to make coreboot live alongside other
396 components like ChromeOS's vboot/FMAP or Intel's IFD / ME / TXE
400 string "fmap description file in fmd format"
401 default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/chromeos.fmd" if CHROMEOS
404 The build system creates a default FMAP from ROM_SIZE and CBFS_SIZE,
405 but in some cases more complex setups are required.
406 When an fmd is specified, it overrides the default format.
410 config SYSTEM_TYPE_LAPTOP
414 config CBFS_AUTOGEN_ATTRIBUTES
418 If this option is selected, every file in cbfs which has a constraint
419 regarding position or alignment will get an additional file attribute
420 which describes this constraint.
425 source "src/soc/*/*/Kconfig"
427 source "src/cpu/Kconfig"
428 comment "Northbridge"
429 source "src/northbridge/*/*/Kconfig"
430 comment "Southbridge"
431 source "src/southbridge/*/*/Kconfig"
433 source "src/superio/*/Kconfig"
434 comment "Embedded Controllers"
435 source "src/ec/acpi/Kconfig"
436 source "src/ec/*/*/Kconfig"
437 source "src/drivers/intel/fsp1_0/Kconfig"
439 source "src/southbridge/intel/common/firmware/Kconfig"
440 source "src/vendorcode/*/Kconfig"
442 source "src/arch/*/Kconfig"
446 source "src/device/Kconfig"
448 menu "Generic Drivers"
449 source "src/drivers/*/Kconfig"
459 select LPC_TPM if ARCH_X86
460 select I2C_TPM if ARCH_ARM
461 select I2C_TPM if ARCH_ARM64
463 Enable this option to enable TPM support in coreboot.
478 default 0x1000 if ARCH_X86
485 config MMCONF_SUPPORT_DEFAULT
489 config MMCONF_SUPPORT
493 config BOOTMODE_STRAPS
497 source "src/console/Kconfig"
499 config HAVE_ACPI_RESUME
503 config HAVE_HARD_RESET
507 This variable specifies whether a given board has a hard_reset
508 function, no matter if it's provided by board code or chipset code.
510 config HAVE_ROMSTAGE_CONSOLE_SPINLOCK
514 config HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK
518 This should be enabled on certain plaforms, such as the AMD
519 SR565x, that cannot handle concurrent CBFS accesses from
520 multiple APs during early startup.
522 config HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK
526 config HAVE_MONOTONIC_TIMER
529 The board/chipset provides a monotonic timer.
531 config GENERIC_UDELAY
533 depends on HAVE_MONOTONIC_TIMER
535 The board/chipset uses a generic udelay function utilizing the
540 depends on HAVE_MONOTONIC_TIMER
542 Provide a timer queue for performing time-based callbacks.
544 config COOP_MULTITASKING
546 depends on TIMER_QUEUE && ARCH_X86
548 Cooperative multitasking allows callbacks to be multiplexed on the
549 main thread of ramstage. With this enabled it allows for multiple
550 execution paths to take place when they have udelay() calls within
556 depends on COOP_MULTITASKING
558 How many execution threads to cooperatively multitask with.
560 config HAVE_OPTION_TABLE
564 This variable specifies whether a given board has a cmos.layout
565 file containing NVRAM/CMOS bit definitions.
566 It defaults to 'n' but can be selected in mainboard/*/Kconfig.
572 config HAVE_SMI_HANDLER
576 config PCI_IO_CFG_EXT
584 config CACHE_ROM_SIZE_OVERRIDE
588 # TODO: Can probably be removed once all chipsets have kconfig options for it.
593 config USE_WATCHDOG_ON_BOOT
601 Build board-specific VGA code.
607 Enable Unified Memory Architecture for graphics.
609 config HAVE_ACPI_TABLES
612 This variable specifies whether a given board has ACPI table support.
613 It is usually set in mainboard/*/Kconfig.
618 This variable specifies whether a given board has MP table support.
619 It is usually set in mainboard/*/Kconfig.
620 Whether or not the MP table is actually generated by coreboot
621 is configurable by the user via GENERATE_MP_TABLE.
623 config HAVE_PIRQ_TABLE
626 This variable specifies whether a given board has PIRQ table support.
627 It is usually set in mainboard/*/Kconfig.
628 Whether or not the PIRQ table is actually generated by coreboot
629 is configurable by the user via GENERATE_PIRQ_TABLE.
631 config MAX_PIRQ_LINKS
635 This variable specifies the number of PIRQ interrupt links which are
636 routable. On most chipsets, this is 4, INTA through INTD. Some
637 chipsets offer more than four links, commonly up to INTH. They may
638 also have a separate link for ATA or IOAPIC interrupts. When the PIRQ
639 table specifies links greater than 4, pirq_route_irqs will not
640 function properly, unless this variable is correctly set.
650 Build support for NHLT (non HD Audio) ACPI table generation.
652 #These Options are here to avoid "undefined" warnings.
653 #The actual selection and help texts are in the following menu.
657 config GENERATE_MP_TABLE
658 prompt "Generate an MP table" if HAVE_MP_TABLE || DRIVERS_GENERIC_IOAPIC
660 default HAVE_MP_TABLE || DRIVERS_GENERIC_IOAPIC
662 Generate an MP table (conforming to the Intel MultiProcessor
663 specification 1.4) for this board.
667 config GENERATE_PIRQ_TABLE
668 prompt "Generate a PIRQ table" if HAVE_PIRQ_TABLE
670 default HAVE_PIRQ_TABLE
672 Generate a PIRQ table for this board.
676 config GENERATE_SMBIOS_TABLES
678 bool "Generate SMBIOS tables"
681 Generate SMBIOS tables for this board.
685 config SMBIOS_PROVIDED_BY_MOBO
689 config MAINBOARD_SERIAL_NUMBER
690 string "SMBIOS Serial Number"
691 depends on GENERATE_SMBIOS_TABLES
692 depends on !SMBIOS_PROVIDED_BY_MOBO
695 The Serial Number to store in SMBIOS structures.
697 config MAINBOARD_VERSION
698 string "SMBIOS Version Number"
699 depends on GENERATE_SMBIOS_TABLES
700 depends on !SMBIOS_PROVIDED_BY_MOBO
703 The Version Number to store in SMBIOS structures.
705 config MAINBOARD_SMBIOS_MANUFACTURER
706 string "SMBIOS Manufacturer"
707 depends on GENERATE_SMBIOS_TABLES
708 depends on !SMBIOS_PROVIDED_BY_MOBO
709 default MAINBOARD_VENDOR
711 Override the default Manufacturer stored in SMBIOS structures.
713 config MAINBOARD_SMBIOS_PRODUCT_NAME
714 string "SMBIOS Product name"
715 depends on GENERATE_SMBIOS_TABLES
716 depends on !SMBIOS_PROVIDED_BY_MOBO
717 default MAINBOARD_PART_NUMBER
719 Override the default Product name stored in SMBIOS structures.
726 prompt "Add a payload"
727 default PAYLOAD_NONE if !ARCH_X86
728 default PAYLOAD_SEABIOS if ARCH_X86
733 Select this option if you want to create an "empty" coreboot
734 ROM image for a certain mainboard, i.e. a coreboot ROM image
735 which does not yet contain a payload.
737 For such an image to be useful, you have to use 'cbfstool'
738 to add a payload to the ROM image later.
741 bool "An ELF executable payload"
743 Select this option if you have a payload image (an ELF file)
744 which coreboot should run as soon as the basic hardware
745 initialization is completed.
747 You will be able to specify the location and file name of the
750 source "payloads/external/*/Kconfig.name"
754 source "payloads/external/*/Kconfig"
757 string "Payload path and filename"
758 depends on PAYLOAD_ELF
759 default "payload.elf"
761 The path and filename of the ELF executable file to use as payload.
763 # TODO: Defined if no payload? Breaks build?
764 config COMPRESSED_PAYLOAD_LZMA
765 bool "Use LZMA compression for payloads"
767 depends on !PAYLOAD_NONE && !PAYLOAD_LINUX
769 In order to reduce the size payloads take up in the ROM chip
770 coreboot can compress them using the LZMA algorithm.
776 # TODO: Better help text and detailed instructions.
778 bool "GDB debugging support"
780 depends on CONSOLE_SERIAL
782 If enabled, you will be able to set breakpoints for gdb debugging.
783 See src/arch/x86/lib/c_start.S for details.
786 bool "Wait for a GDB connection"
790 If enabled, coreboot will wait for a GDB connection.
793 bool "Halt when hitting a BUG() or assertion error"
796 If enabled, coreboot will call hlt() on a BUG() or failed ASSERT().
799 bool "Output verbose CBFS debug messages"
802 This option enables additional CBFS related debug messages.
804 config HAVE_DEBUG_RAM_SETUP
807 config DEBUG_RAM_SETUP
808 bool "Output verbose RAM init debug messages"
810 depends on HAVE_DEBUG_RAM_SETUP
812 This option enables additional RAM init related debug messages.
813 It is recommended to enable this when debugging issues on your
814 board which might be RAM init related.
816 Note: This option will increase the size of the coreboot image.
820 config HAVE_DEBUG_CAR
825 depends on HAVE_DEBUG_CAR
827 if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
828 # Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
829 # printk(BIOS_DEBUG, ...) calls.
831 bool "Output verbose Cache-as-RAM debug messages"
833 depends on HAVE_DEBUG_CAR
835 This option enables additional CAR related debug messages.
839 bool "Check PIRQ table consistency"
841 depends on GENERATE_PIRQ_TABLE
845 config HAVE_DEBUG_SMBUS
849 bool "Output verbose SMBus debug messages"
851 depends on HAVE_DEBUG_SMBUS
853 This option enables additional SMBus (and SPD) debug messages.
855 Note: This option will increase the size of the coreboot image.
860 bool "Output verbose SMI debug messages"
862 depends on HAVE_SMI_HANDLER
863 select SPI_FLASH_SMM if SPI_CONSOLE
865 This option enables additional SMI related debug messages.
867 Note: This option will increase the size of the coreboot image.
871 config DEBUG_SMM_RELOCATION
872 bool "Debug SMM relocation code"
874 depends on HAVE_SMI_HANDLER
876 This option enables additional SMM handler relocation related
879 Note: This option will increase the size of the coreboot image.
883 # Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
884 # printk(BIOS_DEBUG, ...) calls.
886 prompt "Output verbose malloc debug messages" if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
890 This option enables additional malloc related debug messages.
892 Note: This option will increase the size of the coreboot image.
896 # Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
897 # printk(BIOS_DEBUG, ...) calls.
899 prompt "Output verbose ACPI debug messages" if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
903 This option enables additional ACPI related debug messages.
905 Note: This option will slightly increase the size of the coreboot image.
909 # Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
910 # printk(BIOS_DEBUG, ...) calls.
911 config REALMODE_DEBUG
912 prompt "Enable debug messages for option ROM execution" if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
915 depends on PCI_OPTION_ROM_RUN_REALMODE
917 This option enables additional x86emu related debug messages.
919 Note: This option will increase the time to emulate a ROM.
924 bool "Output verbose x86emu debug messages"
926 depends on PCI_OPTION_ROM_RUN_YABEL
928 This option enables additional x86emu related debug messages.
930 Note: This option will increase the size of the coreboot image.
934 config X86EMU_DEBUG_JMP
935 bool "Trace JMP/RETF"
937 depends on X86EMU_DEBUG
939 Print information about JMP and RETF opcodes from x86emu.
941 Note: This option will increase the size of the coreboot image.
945 config X86EMU_DEBUG_TRACE
946 bool "Trace all opcodes"
948 depends on X86EMU_DEBUG
950 Print _all_ opcodes that are executed by x86emu.
952 WARNING: This will produce a LOT of output and take a long time.
954 Note: This option will increase the size of the coreboot image.
958 config X86EMU_DEBUG_PNP
959 bool "Log Plug&Play accesses"
961 depends on X86EMU_DEBUG
963 Print Plug And Play accesses made by option ROMs.
965 Note: This option will increase the size of the coreboot image.
969 config X86EMU_DEBUG_DISK
972 depends on X86EMU_DEBUG
974 Print Disk I/O related messages.
976 Note: This option will increase the size of the coreboot image.
980 config X86EMU_DEBUG_PMM
983 depends on X86EMU_DEBUG
985 Print messages related to POST Memory Manager (PMM).
987 Note: This option will increase the size of the coreboot image.
992 config X86EMU_DEBUG_VBE
993 bool "Debug VESA BIOS Extensions"
995 depends on X86EMU_DEBUG
997 Print messages related to VESA BIOS Extension (VBE) functions.
999 Note: This option will increase the size of the coreboot image.
1003 config X86EMU_DEBUG_INT10
1004 bool "Redirect INT10 output to console"
1006 depends on X86EMU_DEBUG
1008 Let INT10 (i.e. character output) calls print messages to debug output.
1010 Note: This option will increase the size of the coreboot image.
1014 config X86EMU_DEBUG_INTERRUPTS
1015 bool "Log intXX calls"
1017 depends on X86EMU_DEBUG
1019 Print messages related to interrupt handling.
1021 Note: This option will increase the size of the coreboot image.
1025 config X86EMU_DEBUG_CHECK_VMEM_ACCESS
1026 bool "Log special memory accesses"
1028 depends on X86EMU_DEBUG
1030 Print messages related to accesses to certain areas of the virtual
1031 memory (e.g. BDA (BIOS Data Area) or interrupt vectors)
1033 Note: This option will increase the size of the coreboot image.
1037 config X86EMU_DEBUG_MEM
1038 bool "Log all memory accesses"
1040 depends on X86EMU_DEBUG
1042 Print memory accesses made by option ROM.
1043 Note: This also includes accesses to fetch instructions.
1045 Note: This option will increase the size of the coreboot image.
1049 config X86EMU_DEBUG_IO
1050 bool "Log IO accesses"
1052 depends on X86EMU_DEBUG
1054 Print I/O accesses made by option ROM.
1056 Note: This option will increase the size of the coreboot image.
1060 config X86EMU_DEBUG_TIMINGS
1061 bool "Output timing information"
1063 depends on X86EMU_DEBUG && UDELAY_LAPIC && HAVE_MONOTONIC_TIMER
1065 Print timing information needed by i915tool.
1070 bool "Output verbose TPM debug messages"
1074 This option enables additional TPM related debug messages.
1076 config DEBUG_SPI_FLASH
1077 bool "Output verbose SPI flash debug messages"
1079 depends on SPI_FLASH
1081 This option enables additional SPI flash related debug messages.
1083 config DEBUG_USBDEBUG
1084 bool "Output verbose USB 2.0 EHCI debug dongle messages"
1088 This option enables additional USB 2.0 debug dongle related messages.
1090 Select this to debug the connection of usbdebug dongle. Note that
1091 you need some other working console to receive the messages.
1093 if SOUTHBRIDGE_INTEL_BD82X6X && DEFAULT_CONSOLE_LOGLEVEL_8
1094 # Only visible with the right southbridge and loglevel.
1095 config DEBUG_INTEL_ME
1096 bool "Verbose logging for Intel Management Engine"
1099 Enable verbose logging for Intel Management Engine driver that
1100 is present on Intel 6-series chipsets.
1104 bool "Trace function calls"
1107 If enabled, every function will print information to console once
1108 the function is entered. The syntax is ~0xaaaabbbb(0xccccdddd)
1109 the 0xaaaabbbb is the actual function and 0xccccdddd is EIP
1110 of calling function. Please note some printk related functions
1111 are omitted from trace to have good looking console dumps.
1113 config DEBUG_COVERAGE
1114 bool "Debug code coverage"
1118 If enabled, the code coverage hooks in coreboot will output some
1119 information about the coverage data that is dumped.
1123 # These probably belong somewhere else, but they are needed somewhere.
1124 config ENABLE_APIC_EXT_ID
1128 config WARNINGS_ARE_ERRORS
1132 # TODO: Remove this when all platforms are fixed.
1133 config IASL_WARNINGS_ARE_ERRORS
1136 Select to Fail the build if a IASL generates a warning.
1137 This will be defaulted to disabled for the platforms that
1138 currently fail. This allows the REST of the platforms to
1139 have this check enabled while we're working to get those
1142 DO NOT ADD TO ANY ADDITIONAL PLATFORMS INSTEAD OF FIXING
1145 # The four POWER_BUTTON_DEFAULT_ENABLE, POWER_BUTTON_DEFAULT_DISABLE,
1146 # POWER_BUTTON_FORCE_ENABLE and POWER_BUTTON_FORCE_DISABLE options are
1147 # mutually exclusive. One of these options must be selected in the
1148 # mainboard Kconfig if the chipset supports enabling and disabling of
1149 # the power button. Chipset code uses the ENABLE_POWER_BUTTON option set
1150 # in mainboard/Kconfig to know if the button should be enabled or not.
1152 config POWER_BUTTON_DEFAULT_ENABLE
1155 Select when the board has a power button which can optionally be
1156 disabled by the user.
1158 config POWER_BUTTON_DEFAULT_DISABLE
1161 Select when the board has a power button which can optionally be
1162 enabled by the user, e.g. when the board ships with a jumper over
1163 the power switch contacts.
1165 config POWER_BUTTON_FORCE_ENABLE
1168 Select when the board requires that the power button is always
1171 config POWER_BUTTON_FORCE_DISABLE
1174 Select when the board requires that the power button is always
1175 disabled, e.g. when it has been hardwired to ground.
1177 config POWER_BUTTON_IS_OPTIONAL
1179 default y if POWER_BUTTON_DEFAULT_ENABLE || POWER_BUTTON_DEFAULT_DISABLE
1180 default n if !(POWER_BUTTON_DEFAULT_ENABLE || POWER_BUTTON_DEFAULT_DISABLE)
1182 Internal option that controls ENABLE_POWER_BUTTON visibility.
1188 Internal option that controls whether we compile in register scripts.
1190 config MAX_REBOOT_CNT
1194 Internal option that sets the maximum number of bootblock executions allowed
1195 with the normal image enabled before assuming the normal image is defective
1196 and switching to the fallback image.