src/southbridge/amd/cimx/sb800/fadt.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2011 Advanced Micro Devices, Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  18  */
  19
  20
  21 /*
  22  * ACPI - create the Fixed ACPI Description Tables (FADT)
  23  */
  24
  25
  26 #include <string.h>
  27 #include <console/console.h>
  28 #include <arch/acpi.h>
  29 #include <arch/io.h>
  30 #include <device/device.h>
  31 #include "SBPLATFORM.h"
  32
  33 #ifndef FADT_BOOT_ARCH
  34 #if LEGACY_FREE
  35         #define FADT_BOOT_ARCH ACPI_FADT_LEGACY_FREE
  36 #else
  37         #define FADT_BOOT_ARCH (ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042)
  38 #endif
  39 #endif
  40
  41 #ifndef FADT_PM_PROFILE
  42         #define FADT_PM_PROFILE PM_UNSPECIFIED
  43 #endif
  44
  45 /*
  46  * Reference section 5.2.9 Fixed ACPI Description Table (FADT)
  47  * in the ACPI 3.0b specification.
  48  */
  49 void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
  50 {
  51         u16 val = 0;
  52         acpi_header_t *header = &(fadt->header);
  53
  54         printk(BIOS_DEBUG, "ACPI_BLK_BASE: 0x%04x\n", ACPI_BLK_BASE);
  55
  56         /* Prepare the header */
  57         memset((void *)fadt, 0, sizeof(acpi_fadt_t));
  58         memcpy(header->signature, "FACP", 4);
  59         header->length = sizeof(acpi_fadt_t);
  60         header->revision = ACPI_FADT_REV_ACPI_3_0;
  61         memcpy(header->oem_id, OEM_ID, 6);
  62         memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8);
  63         memcpy(header->asl_compiler_id, ASLC, 4);
  64         header->asl_compiler_revision = 0;
  65
  66         fadt->firmware_ctrl = (u32) facs;
  67         fadt->dsdt = (u32) dsdt;
  68         fadt->model = 0;                /* reserved, should be 0 ACPI 3.0 */
  69         fadt->preferred_pm_profile = FADT_PM_PROFILE;
  70         fadt->sci_int = 9;              /* HUDSON 1 - IRQ 09 – ACPI SCI */
  71         fadt->smi_cmd = 0;              /* disable system management mode */
  72         fadt->acpi_enable = 0;  /* unused if SMI_CMD = 0 */
  73         fadt->acpi_disable = 0; /* unused if SMI_CMD = 0 */
  74         fadt->s4bios_req = 0;   /* unused if SMI_CMD = 0 */
  75         fadt->pstate_cnt = 0;   /* unused if SMI_CMD = 0 */
  76
  77         val = PM1_EVT_BLK_ADDRESS;
  78         WritePMIO(SB_PMIOA_REG60, AccWidthUint16, &val);
  79         val = PM1_CNT_BLK_ADDRESS;
  80         WritePMIO(SB_PMIOA_REG62, AccWidthUint16, &val);
  81         val = PM1_TMR_BLK_ADDRESS;
  82         WritePMIO(SB_PMIOA_REG64, AccWidthUint16, &val);
  83         val = GPE0_BLK_ADDRESS;
  84         WritePMIO(SB_PMIOA_REG68, AccWidthUint16, &val);
  85
  86         /* CpuControl is in \_PR.CPU0, 6 bytes */
  87         val = CPU_CNT_BLK_ADDRESS;
  88         WritePMIO(SB_PMIOA_REG66, AccWidthUint16, &val);
  89         val = 0;
  90         WritePMIO(SB_PMIOA_REG6A, AccWidthUint16, &val);
  91         val = ACPI_PMA_CNT_BLK_ADDRESS;
  92         WritePMIO(SB_PMIOA_REG6E, AccWidthUint16, &val);
  93
  94         /* AcpiDecodeEnable, When set, SB uses the contents of the
  95          * PM registers at index 60-6B to decode ACPI I/O address.
  96          * AcpiSmiEn & SmiCmdEn*/
  97         val = BIT0 | BIT1 | BIT2 | BIT4;
  98         WritePMIO(SB_PMIOA_REG74, AccWidthUint16, &val);
  99
 100         /* RTC_En_En, TMR_En_En, GBL_EN_EN */
 101         outl(0x1, PM1_CNT_BLK_ADDRESS);           /* set SCI_EN */
 102         fadt->pm1a_evt_blk = PM1_EVT_BLK_ADDRESS;
 103         fadt->pm1b_evt_blk = 0x0000;
 104         fadt->pm1a_cnt_blk = PM1_CNT_BLK_ADDRESS;
 105         fadt->pm1b_cnt_blk = 0x0000;
 106         fadt->pm2_cnt_blk = ACPI_PMA_CNT_BLK_ADDRESS;
 107         fadt->pm_tmr_blk = PM1_TMR_BLK_ADDRESS;
 108         fadt->gpe0_blk = GPE0_BLK_ADDRESS;
 109         fadt->gpe1_blk = 0;             /* No gpe1 block in hudson1 */
 110
 111         fadt->pm1_evt_len = 4;  /* 32 bits */
 112         fadt->pm1_cnt_len = 2;  /* 16 bits */
 113         fadt->pm2_cnt_len = 1;  /* 8 bits */
 114         fadt->pm_tmr_len = 4;   /* 32 bits */
 115         fadt->gpe0_blk_len = 8; /* 64 bits */
 116         fadt->gpe1_blk_len = 0;
 117         fadt->gpe1_base = 0;
 118
 119         fadt->cst_cnt = 0x00;   /* unused if SMI_CMD = 0 */
 120         fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED;
 121         fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED;
 122         fadt->flush_size = 0;   /* set to 0 if WBINVD is 1 in flags */
 123         fadt->flush_stride = 0; /* set to 0 if WBINVD is 1 in flags */
 124         fadt->duty_offset = 1;  /* CLK_VAL bits 3:1 */
 125         fadt->duty_width = 3;   /* CLK_VAL bits 3:1 */
 126         fadt->day_alrm = 0;     /* 0x7d these have to be */
 127         fadt->mon_alrm = 0;     /* 0x7e added to cmos.layout */
 128         fadt->century = 0;      /* 0x7f to make rtc alrm work */
 129         fadt->iapc_boot_arch = FADT_BOOT_ARCH;  /* See table 5-10 */
 130         fadt->res2 = 0;         /* reserved, MUST be 0 ACPI 3.0 */
 131         fadt->flags = ACPI_FADT_WBINVD | /* See table 5-10 ACPI 3.0a spec */
 132                                 ACPI_FADT_C1_SUPPORTED |
 133                                 ACPI_FADT_SLEEP_BUTTON |
 134                                 ACPI_FADT_S4_RTC_WAKE |
 135                                 ACPI_FADT_32BIT_TIMER |
 136                                 ACPI_FADT_RESET_REGISTER |
 137                                 ACPI_FADT_PCI_EXPRESS_WAKE |
 138                                 ACPI_FADT_S4_RTC_VALID |
 139                                 ACPI_FADT_REMOTE_POWER_ON;
 140
 141         /* Format is from 5.2.3.1: Generic Address Structure */
 142         /* reset_reg: see section 4.7.3.6 ACPI 3.0a spec */
 143         /* 8 bit write of value 0x06 to 0xCF9 in IO space */
 144         fadt->reset_reg.space_id = ACPI_ADDRESS_SPACE_IO;
 145         fadt->reset_reg.bit_width = 8;
 146         fadt->reset_reg.bit_offset = 0;
 147         fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;
 148         fadt->reset_reg.addrl = 0xcf9;
 149         fadt->reset_reg.addrh = 0x0;
 150         fadt->reset_value = 6;
 151
 152         fadt->res3 = 0;         /* reserved, MUST be 0 ACPI 3.0 */
 153         fadt->res4 = 0;         /* reserved, MUST be 0 ACPI 3.0 */
 154         fadt->res5 = 0;         /* reserved, MUST be 0 ACPI 3.0 */
 155
 156         fadt->x_firmware_ctl_l = 0;     /* set to 0 if firmware_ctrl is used */
 157         fadt->x_firmware_ctl_h = 0;
 158         fadt->x_dsdt_l = (u32) dsdt;
 159         fadt->x_dsdt_h = 0;
 160
 161         fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
 162         fadt->x_pm1a_evt_blk.bit_width = 32;
 163         fadt->x_pm1a_evt_blk.bit_offset = 0;
 164         fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS;
 165         fadt->x_pm1a_evt_blk.addrl = PM1_EVT_BLK_ADDRESS;
 166         fadt->x_pm1a_evt_blk.addrh = 0x0;
 167
 168         fadt->x_pm1b_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
 169         fadt->x_pm1b_evt_blk.bit_width = 0;
 170         fadt->x_pm1b_evt_blk.bit_offset = 0;
 171         fadt->x_pm1b_evt_blk.access_size = 0;
 172         fadt->x_pm1b_evt_blk.addrl = 0x0;
 173         fadt->x_pm1b_evt_blk.addrh = 0x0;
 174
 175
 176         fadt->x_pm1a_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
 177         fadt->x_pm1a_cnt_blk.bit_width = 16;
 178         fadt->x_pm1a_cnt_blk.bit_offset = 0;
 179         fadt->x_pm1a_cnt_blk.access_size = 0;
 180         fadt->x_pm1a_cnt_blk.addrl = PM1_CNT_BLK_ADDRESS;
 181         fadt->x_pm1a_cnt_blk.addrh = 0x0;
 182
 183         fadt->x_pm1b_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
 184         fadt->x_pm1b_cnt_blk.bit_width = 0;
 185         fadt->x_pm1b_cnt_blk.bit_offset = 0;
 186         fadt->x_pm1b_cnt_blk.access_size = 0;
 187         fadt->x_pm1b_cnt_blk.addrl = 0x0;
 188         fadt->x_pm1b_cnt_blk.addrh = 0x0;
 189
 190
 191         fadt->x_pm2_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
 192         fadt->x_pm2_cnt_blk.bit_width = 8;      /* Hudson 1 Pm2Control is 8 bits */
 193         fadt->x_pm2_cnt_blk.bit_offset = 0;
 194         fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;
 195         fadt->x_pm2_cnt_blk.addrl = ACPI_PMA_CNT_BLK_ADDRESS;
 196         fadt->x_pm2_cnt_blk.addrh = 0x0;
 197
 198
 199         fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO;
 200         fadt->x_pm_tmr_blk.bit_width = 32;
 201         fadt->x_pm_tmr_blk.bit_offset = 0;
 202         fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
 203         fadt->x_pm_tmr_blk.addrl = PM1_TMR_BLK_ADDRESS;
 204         fadt->x_pm_tmr_blk.addrh = 0x0;
 205
 206
 207         fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO;
 208         fadt->x_gpe0_blk.bit_width = 64; /* EventStatus + Event Enable */
 209         fadt->x_gpe0_blk.bit_offset = 0;
 210         fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
 211         fadt->x_gpe0_blk.addrl = GPE0_BLK_ADDRESS;
 212         fadt->x_gpe0_blk.addrh = 0x0;
 213
 214
 215         fadt->x_gpe1_blk.space_id = ACPI_ADDRESS_SPACE_IO;
 216         fadt->x_gpe1_blk.bit_width = 0;
 217         fadt->x_gpe1_blk.bit_offset = 0;
 218         fadt->x_gpe1_blk.access_size = 0;
 219         fadt->x_gpe1_blk.addrl = 0;
 220         fadt->x_gpe1_blk.addrh = 0x0;
 221
 222         header->checksum = acpi_checksum((void *)fadt, sizeof(acpi_fadt_t));
 223
 224 }