src/mainboard/siemens/sitemp_g1p1/resourcemap.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2008 Advanced Micro Devices, Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  18  */
  19
  20 static void setup_sitemp_resource_map(void)
  21 {
  22         static const unsigned int register_values[] = {
  23                 /* Careful set limit registers before base registers which contain the enables */
  24                 /* DRAM Limit i Registers
  25                 * F1:0x44 i = 0
  26                 * F1:0x4C i = 1
  27                 * F1:0x54 i = 2
  28                 * F1:0x5C i = 3
  29                 * F1:0x64 i = 4
  30                 * F1:0x6C i = 5
  31                 * F1:0x74 i = 6
  32                 * F1:0x7C i = 7
  33                 * [ 2: 0] Destination Node ID
  34                 *       000 = Node 0
  35                 *       001 = Node 1
  36                 *       010 = Node 2
  37                 *       011 = Node 3
  38                 *       100 = Node 4
  39                 *       101 = Node 5
  40                 *       110 = Node 6
  41                 *       111 = Node 7
  42                 * [ 7: 3] Reserved
  43                 * [10: 8] Interleave select
  44                 *       specifies the values of A[14:12] to use with interleave enable.
  45                 * [15:11] Reserved
  46                 * [31:16] DRAM Limit Address i Bits 39-24
  47                 *       This field defines the upper address bits of a 40 bit  address
  48                 *       that define the end of the DRAM region.
  49                 */
  50                 PCI_ADDR(0, 0x18, 1, 0x44), 0x0000f8f8, 0x00000000,
  51                 PCI_ADDR(0, 0x18, 1, 0x4C), 0x0000f8f8, 0x00000001,
  52                 PCI_ADDR(0, 0x18, 1, 0x54), 0x0000f8f8, 0x00000002,
  53                 PCI_ADDR(0, 0x18, 1, 0x5C), 0x0000f8f8, 0x00000003,
  54                 PCI_ADDR(0, 0x18, 1, 0x64), 0x0000f8f8, 0x00000004,
  55                 PCI_ADDR(0, 0x18, 1, 0x6C), 0x0000f8f8, 0x00000005,
  56                 PCI_ADDR(0, 0x18, 1, 0x74), 0x0000f8f8, 0x00000006,
  57                 PCI_ADDR(0, 0x18, 1, 0x7C), 0x0000f8f8, 0x00000007,
  58                 /* DRAM Base i Registers
  59                 * F1:0x40 i = 0
  60                 * F1:0x48 i = 1
  61                 * F1:0x50 i = 2
  62                 * F1:0x58 i = 3
  63                 * F1:0x60 i = 4
  64                 * F1:0x68 i = 5
  65                 * F1:0x70 i = 6
  66                 * F1:0x78 i = 7
  67                 * [ 0: 0] Read Enable
  68                 *       0 = Reads Disabled
  69                 *       1 = Reads Enabled
  70                 * [ 1: 1] Write Enable
  71                 *       0 = Writes Disabled
  72                 *       1 = Writes Enabled
  73                 * [ 7: 2] Reserved
  74                 * [10: 8] Interleave Enable
  75                 *       000 = No interleave
  76                 *       001 = Interleave on A[12] (2 nodes)
  77                 *       010 = reserved
  78                 *       011 = Interleave on A[12] and A[14] (4 nodes)
  79                 *       100 = reserved
  80                 *       101 = reserved
  81                 *       110 = reserved
  82                 *       111 = Interleve on A[12] and A[13] and A[14] (8 nodes)
  83                 * [15:11] Reserved
  84                 * [13:16] DRAM Base Address i Bits 39-24
  85                 *       This field defines the upper address bits of a 40-bit address
  86                 *       that define the start of the DRAM region.
  87                 */
  88                 PCI_ADDR(0, 0x18, 1, 0x40), 0x0000f8fc, 0x00000000,
  89                 PCI_ADDR(0, 0x18, 1, 0x48), 0x0000f8fc, 0x00000000,
  90                 PCI_ADDR(0, 0x18, 1, 0x50), 0x0000f8fc, 0x00000000,
  91                 PCI_ADDR(0, 0x18, 1, 0x58), 0x0000f8fc, 0x00000000,
  92                 PCI_ADDR(0, 0x18, 1, 0x60), 0x0000f8fc, 0x00000000,
  93                 PCI_ADDR(0, 0x18, 1, 0x68), 0x0000f8fc, 0x00000000,
  94                 PCI_ADDR(0, 0x18, 1, 0x70), 0x0000f8fc, 0x00000000,
  95                 PCI_ADDR(0, 0x18, 1, 0x78), 0x0000f8fc, 0x00000000,
  96
  97                 /* Memory-Mapped I/O Limit i Registers
  98                  * F1:0x84 i = 0
  99                  * F1:0x8C i = 1
 100                  * F1:0x94 i = 2
 101                  * F1:0x9C i = 3
 102                  * F1:0xA4 i = 4
 103                  * F1:0xAC i = 5
 104                  * F1:0xB4 i = 6
 105                  * F1:0xBC i = 7
 106                  * [ 2: 0] Destination Node ID
 107                  *      000 = Node 0
 108                  *      001 = Node 1
 109                  *      010 = Node 2
 110                  *      011 = Node 3
 111                  *      100 = Node 4
 112                  *      101 = Node 5
 113                  *      110 = Node 6
 114                  *      111 = Node 7
 115                  * [ 3: 3] Reserved
 116                  * [ 5: 4] Destination Link ID
 117                  *      00 = Link 0
 118                  *      01 = Link 1
 119                  *      10 = Link 2
 120                  *      11 = Reserved
 121                  * [ 6: 6] Reserved
 122                  * [ 7: 7] Non-Posted
 123                  *      0 = CPU writes may be posted
 124                  *      1 = CPU writes must be non-posted
 125                  * [31: 8] Memory-Mapped I/O Limit Address i (39-16)
 126                  *      This field defines the upp adddress bits of a 40-bit address that
 127                  *      defines the end of a memory-mapped I/O region n
 128                  */
 129                 PCI_ADDR(0, 0x18, 1, 0x84), 0x00000048, 0x00000000,
 130                 PCI_ADDR(0, 0x18, 1, 0x8C), 0x00000048, 0x00000000,
 131                 PCI_ADDR(0, 0x18, 1, 0x94), 0x00000048, 0x00000000,
 132                 PCI_ADDR(0, 0x18, 1, 0x9C), 0x00000048, 0x00000000,
 133                 PCI_ADDR(0, 0x18, 1, 0xA4), 0x00000048, 0x00000000,
 134                 PCI_ADDR(0, 0x18, 1, 0xAC), 0x00000048, 0x00000000,
 135                 PCI_ADDR(0, 0x18, 1, 0xB4), 0x00000048, 0x00000000,
 136                 PCI_ADDR(0, 0x18, 1, 0xBC), 0x00000048, 0x00ffff00,
 137
 138                 /* Memory-Mapped I/O Base i Registers
 139                 * F1:0x80 i = 0
 140                 * F1:0x88 i = 1
 141                 * F1:0x90 i = 2
 142                 * F1:0x98 i = 3
 143                 * F1:0xA0 i = 4
 144                 * F1:0xA8 i = 5
 145                 * F1:0xB0 i = 6
 146                 * F1:0xB8 i = 7
 147                 * [ 0: 0] Read Enable
 148                 *       0 = Reads disabled
 149                 *       1 = Reads Enabled
 150                 * [ 1: 1] Write Enable
 151                 *       0 = Writes disabled
 152                 *       1 = Writes Enabled
 153                 * [ 2: 2] Cpu Disable
 154                 *       0 = Cpu can use this I/O range
 155                 *       1 = Cpu requests do not use this I/O range
 156                 * [ 3: 3] Lock
 157                 *       0 = base/limit registers i are read/write
 158                 *       1 = base/limit registers i are read-only
 159                 * [ 7: 4] Reserved
 160                 * [31: 8] Memory-Mapped I/O Base Address i (39-16)
 161                 *       This field defines the upper address bits of a 40bit address
 162                 *       that defines the start of memory-mapped I/O region i
 163                 */
 164                 PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00000000,
 165                 PCI_ADDR(0, 0x18, 1, 0x88), 0x000000f0, 0x00000000,
 166                 PCI_ADDR(0, 0x18, 1, 0x90), 0x000000f0, 0x00000000,
 167                 PCI_ADDR(0, 0x18, 1, 0x98), 0x000000f0, 0x00000000,
 168                 PCI_ADDR(0, 0x18, 1, 0xA0), 0x000000f0, 0x00000000,
 169                 PCI_ADDR(0, 0x18, 1, 0xA8), 0x000000f0, 0x00000000,
 170                 PCI_ADDR(0, 0x18, 1, 0xB0), 0x000000f0, 0x00000000,
 171                 PCI_ADDR(0, 0x18, 1, 0xB8), 0x000000f0, 0x00fc0003,
 172
 173                 /* PCI I/O Limit i Registers
 174                 * F1:0xC4 i = 0
 175                 * F1:0xCC i = 1
 176                 * F1:0xD4 i = 2
 177                 * F1:0xDC i = 3
 178                 * [ 2: 0] Destination Node ID
 179                 *       000 = Node 0
 180                 *       001 = Node 1
 181                 *       010 = Node 2
 182                 *       011 = Node 3
 183                 *       100 = Node 4
 184                 *       101 = Node 5
 185                 *       110 = Node 6
 186                 *       111 = Node 7
 187                 * [ 3: 3] Reserved
 188                 * [ 5: 4] Destination Link ID
 189                 *       00 = Link 0
 190                 *       01 = Link 1
 191                 *       10 = Link 2
 192                 *       11 = reserved
 193                 * [11: 6] Reserved
 194                 * [24:12] PCI I/O Limit Address i
 195                 *       This field defines the end of PCI I/O region n
 196                 * [31:25] Reserved
 197                 */
 198                 PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x01fff000,
 199                 PCI_ADDR(0, 0x18, 1, 0xCC), 0xFE000FC8, 0x00000000,
 200                 PCI_ADDR(0, 0x18, 1, 0xD4), 0xFE000FC8, 0x00000000,
 201                 PCI_ADDR(0, 0x18, 1, 0xDC), 0xFE000FC8, 0x00000000,
 202
 203                 /* PCI I/O Base i Registers
 204                  * F1:0xC0 i = 0
 205                  * F1:0xC8 i = 1
 206                  * F1:0xD0 i = 2
 207                  * F1:0xD8 i = 3
 208                  * [ 0: 0] Read Enable
 209                  *      0 = Reads Disabled
 210                  *      1 = Reads Enabled
 211                  * [ 1: 1] Write Enable
 212                  *      0 = Writes Disabled
 213                  *      1 = Writes Enabled
 214                  * [ 3: 2] Reserved
 215                  * [ 4: 4] VGA Enable
 216                  *      0 = VGA matches Disabled
 217                  *      1 = matches all address < 64K and where A[9:0] is in the
 218                  *      range 3B0-3BB or 3C0-3DF independen of the base & limit registers
 219                  * [ 5: 5] ISA Enable
 220                  *      0 = ISA matches Disabled
 221                  *      1 = Blocks address < 64K and in the last 768 bytes of eack 1K block
 222                  *      from matching agains this base/limit pair
 223                  * [11: 6] Reserved
 224                  * [24:12] PCI I/O Base i
 225                  *      This field defines the start of PCI I/O region n
 226                  * [31:25] Reserved
 227                  */
 228                 PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000003,
 229                 PCI_ADDR(0, 0x18, 1, 0xC8), 0xFE000FCC, 0x00000000,
 230                 PCI_ADDR(0, 0x18, 1, 0xD0), 0xFE000FCC, 0x00000000,
 231                 PCI_ADDR(0, 0x18, 1, 0xD8), 0xFE000FCC, 0x00000000,
 232
 233                 /* Config Base and Limit i Registers
 234                  * F1:0xE0 i = 0
 235                  * F1:0xE4 i = 1
 236                  * F1:0xE8 i = 2
 237                  * F1:0xEC i = 3
 238                  * [ 0: 0] Read Enable
 239                  *      0 = Reads Disabled
 240                  *      1 = Reads Enabled
 241                  * [ 1: 1] Write Enable
 242                  *      0 = Writes Disabled
 243                  *      1 = Writes Enabled
 244                  * [ 2: 2] Device Number Compare Enable
 245                  *      0 = The ranges are based on bus number
 246                  *      1 = The ranges are ranges of devices on bus 0
 247                  * [ 3: 3] Reserved
 248                  * [ 6: 4] Destination Node
 249                  *      000 = Node 0
 250                  *      001 = Node 1
 251                  *      010 = Node 2
 252                  *      011 = Node 3
 253                  *      100 = Node 4
 254                  *      101 = Node 5
 255                  *      110 = Node 6
 256                  *      111 = Node 7
 257                  * [ 7: 7] Reserved
 258                  * [ 9: 8] Destination Link
 259                  *      00 = Link 0
 260                  *      01 = Link 1
 261                  *      10 = Link 2
 262                  *      11 - Reserved
 263                  * [15:10] Reserved
 264                  * [23:16] Bus Number Base i
 265                  *      This field defines the lowest bus number in configuration region i
 266                  * [31:24] Bus Number Limit i
 267                  *      This field defines the highest bus number in configuration regin i
 268                  */
 269                 PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x08000003,
 270                 PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000000,
 271                 PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000,
 272                 PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000,
 273         };
 274
 275         int max;
 276         max = ARRAY_SIZE(register_values);
 277         setup_resource_map(register_values, max);
 278 }