util/ifdtool/ifdtool.h

   1 /* ifdtool - dump Intel Firmware Descriptor information */
   2 /* SPDX-License-Identifier: GPL-2.0-only */
   3
   4 #include <stdint.h>
   5 #include <stdbool.h>
   6 #define IFDTOOL_VERSION "1.2"
   7
   8 enum ifd_version {
   9         IFD_VERSION_1,
  10         IFD_VERSION_2,
  11 };
  12
  13 /* port from flashrom */
  14 enum ich_chipset {
  15         CHIPSET_ICH_UNKNOWN,
  16         CHIPSET_ICH,
  17         CHIPSET_ICH2345,
  18         CHIPSET_ICH6,
  19         CHIPSET_POULSBO, /* SCH U* */
  20         CHIPSET_TUNNEL_CREEK, /* Atom E6xx */
  21         CHIPSET_CENTERTON, /* Atom S1220 S1240 S1260 */
  22         CHIPSET_ICH7,
  23         CHIPSET_ICH8,
  24         CHIPSET_ICH9,
  25         CHIPSET_ICH10,
  26         CHIPSET_PCH_UNKNOWN,
  27         CHIPSET_5_SERIES_IBEX_PEAK,
  28         CHIPSET_6_SERIES_COUGAR_POINT,
  29         CHIPSET_7_SERIES_PANTHER_POINT,
  30         CHIPSET_8_SERIES_LYNX_POINT,
  31         CHIPSET_BAYTRAIL, /* Actually all with Silvermont architecture:
  32                            * Bay Trail, Avoton/Rangeley
  33                            */
  34         CHIPSET_8_SERIES_LYNX_POINT_LP,
  35         CHIPSET_8_SERIES_WELLSBURG,
  36         CHIPSET_9_SERIES_WILDCAT_POINT,
  37         CHIPSET_9_SERIES_WILDCAT_POINT_LP,
  38         CHIPSET_N_J_SERIES_APOLLO_LAKE, /* Apollo Lake: N3xxx, J3xxx */
  39         CHIPSET_N_J_SERIES_GEMINI_LAKE, /* Gemini Lake: N5xxx, J5xxx, N4xxx, J4xxx */
  40         CHIPSET_N_SERIES_JASPER_LAKE, /* Jasper Lake: N6xxx, N51xx, N45xx */
  41         CHIPSET_x6000_SERIES_ELKHART_LAKE, /* Elkhart Lake: x6000 */
  42         CHIPSET_100_200_SERIES_SUNRISE_POINT, /* 6th-7th gen Core i/o (LP) variants */
  43         CHIPSET_300_SERIES_CANNON_POINT, /* 8th-9th gen Core i/o (LP) variants */
  44         CHIPSET_400_SERIES_ICE_POINT, /* 10th gen Core i/o (LP) variants */
  45         CHIPSET_500_600_SERIES_TIGER_ALDER_POINT, /* 11th-12th gen Core i/o (LP)
  46                                                    * variants onwards */
  47         CHIPSET_C620_SERIES_LEWISBURG,
  48         CHIPSET_DENVERTON,
  49 };
  50
  51 enum platform {
  52         PLATFORM_APL,
  53         PLATFORM_CNL,
  54         PLATFORM_LBG,
  55         PLATFORM_EHL,
  56         PLATFORM_GLK,
  57         PLATFORM_ICL,
  58         PLATFORM_JSL,
  59         PLATFORM_SKLKBL,
  60         PLATFORM_TGL,
  61         PLATFORM_ADL,
  62         PLATFORM_IFD2,
  63         PLATFORM_DNV,
  64         PLATFORM_MTL,
  65 };
  66
  67 #define LAYOUT_LINELEN 80
  68
  69 enum spi_frequency {
  70         SPI_FREQUENCY_20MHZ = 0,
  71         SPI_FREQUENCY_33MHZ = 1,
  72         SPI_FREQUENCY_48MHZ = 2,
  73         SPI_FREQUENCY_50MHZ_30MHZ = 4,
  74         SPI_FREQUENCY_17MHZ = 6,
  75 };
  76
  77 enum spi_frequency_500_series {
  78         SPI_FREQUENCY_100MHZ = 0,
  79         SPI_FREQUENCY_50MHZ = 1,
  80         SPI_FREQUENCY_500SERIES_33MHZ = 3,
  81         SPI_FREQUENCY_25MHZ = 4,
  82         SPI_FREQUENCY_14MHZ = 6,
  83 };
  84
  85 enum espi_frequency {
  86         ESPI_FREQUENCY_20MHZ = 0,
  87         ESPI_FREQUENCY_24MHZ = 1,
  88         ESPI_FREQUENCY_30MHZ = 2,
  89         ESPI_FREQUENCY_48MHZ = 3,
  90         ESPI_FREQUENCY_60MHZ = 4,
  91         ESPI_FREQUENCY_17MHZ = 6,
  92 };
  93
  94 enum espi_frequency_500_series {
  95         ESPI_FREQUENCY_500SERIES_20MHZ = 0,
  96         ESPI_FREQUENCY_500SERIES_24MHZ = 1,
  97         ESPI_FREQUENCY_500SERIES_25MHZ = 2,
  98         ESPI_FREQUENCY_500SERIES_48MHZ = 3,
  99         ESPI_FREQUENCY_500SERIES_60MHZ = 4,
 100 };
 101
 102 enum component_density {
 103         COMPONENT_DENSITY_512KB = 0,
 104         COMPONENT_DENSITY_1MB   = 1,
 105         COMPONENT_DENSITY_2MB   = 2,
 106         COMPONENT_DENSITY_4MB   = 3,
 107         COMPONENT_DENSITY_8MB   = 4,
 108         COMPONENT_DENSITY_16MB  = 5,
 109         COMPONENT_DENSITY_32MB  = 6,
 110         COMPONENT_DENSITY_64MB  = 7,
 111         COMPONENT_DENSITY_UNUSED = 0xf
 112 };
 113
 114 // flash descriptor
 115 typedef struct {
 116         uint32_t flvalsig;
 117         uint32_t flmap0;
 118         uint32_t flmap1;
 119         uint32_t flmap2;
 120         uint32_t flmap3; // Exist for 500 series onwards
 121 } __attribute__((packed)) fdbar_t;
 122
 123 // regions
 124 #define MAX_REGIONS 16
 125 #define MAX_REGIONS_OLD 5
 126
 127 enum flash_regions {
 128         REGION_DESC,
 129         REGION_BIOS,
 130         REGION_ME,
 131         REGION_GBE,
 132         REGION_PDR,
 133         REGION_DEV_EXP1,
 134         REGION_BIOS2,
 135         REGION_EC = 8,
 136         REGION_DEV_EXP2,
 137         REGION_IE,
 138         REGION_10GB_0,
 139         REGION_10GB_1,
 140         REGION_PTT = 15,
 141 };
 142
 143 typedef struct {
 144         uint32_t flreg[MAX_REGIONS];
 145 } __attribute__((packed)) frba_t;
 146
 147 // component section
 148 typedef struct {
 149         uint32_t flcomp;
 150         uint32_t flill;
 151         uint32_t flpb;
 152 } __attribute__((packed)) fcba_t;
 153
 154 // pch strap
 155 #define MAX_PCHSTRP 1024
 156
 157 typedef struct {
 158         uint32_t pchstrp[MAX_PCHSTRP];
 159 } __attribute__((packed)) fpsba_t;
 160
 161 /*
 162  * WR / RD bits start at different locations within the flmstr regs, but
 163  * otherwise have identical meaning.
 164  */
 165 #define FLMSTR_WR_SHIFT_V1 24
 166 #define FLMSTR_WR_SHIFT_V2 20
 167 #define FLMSTR_RD_SHIFT_V1 16
 168 #define FLMSTR_RD_SHIFT_V2 8
 169
 170 // master
 171 typedef struct {
 172         uint32_t flmstr1;
 173         uint32_t flmstr2;
 174         uint32_t flmstr3;
 175         uint32_t flmstr4;
 176         uint32_t flmstr5;
 177         uint32_t flmstr6;
 178 } __attribute__((packed)) fmba_t;
 179
 180 // processor strap
 181 typedef struct {
 182         uint32_t data[8];
 183 } __attribute__((packed)) fmsba_t;
 184
 185 // ME VSCC
 186 typedef struct {
 187         uint32_t jid;
 188         uint32_t vscc;
 189 } vscc_t;
 190
 191 typedef struct {
 192         // Actual number of entries specified in vtl
 193         /* FIXME: Rationale for the limit of 8.
 194          *        AFAICT it's 127, cf. flashrom's ich_descriptors_tool). */
 195         vscc_t entry[8];
 196 } vtba_t;
 197
 198 typedef struct {
 199         int base, limit, size;
 200 } region_t;
 201
 202 struct region_name {
 203         const char *pretty;
 204         const char *terse;
 205         const char *filename;
 206         const char *fmapname;
 207 };